JP2009043818A - Electronic circuit apparatus of electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic circuit apparatus which enables mounting of an option board using a high-speed serial transfer interface without having a layout area for a main board. <P>SOLUTION: The electronic circuit apparatus includes: the main board 10 equipped with a plurality of electronic circuit devices 20, 30, with a plurality of connectors 22, 32, and with high-speed serial transfer interfaces 21 and 31 connecting the connectors to the electronic circuit devices, respectively; a first board 50 equipped with a plurality of connectors 52, 53, with high-speed serial transfer interfaces 51 interconnecting the connectors, and with an SSCG that gives a clock to the main side interfaces and to the option side interface; or a second board 60 equipped with an option electronic circuit device 70, with connectors 62, 63, with high-speed serial transfer interfaces 71, 72 connecting respective connectors to a function extending device 70, and with an SSCG that gives a clock to the main side interfaces and to the option side interfaces. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to the deployment of electronic circuit devices on printed circuit boards of electronic equipment.

JP-A-2005-7781 JP-A-2005-88287.

  In the image forming apparatus described in the cited document 1, an option board for function expansion can be additionally connected to the main control board, and when there is a request for outputting an operation manual, the main control unit searches for the added option board. Then, the detected operation manual for the function of the option board is read from the image storage unit and displayed on the display of the operation unit. In the image forming apparatus described in the cited document 2, in order to reduce electromagnetic induction noise generated by motor driving, a basic clock for driving a polygon motor, a drum driving motor, a paper feeding motor, and a fixing motor of a laser printer is set to SSCG ( In order to avoid interference between driven systems due to frequency spread, each generated based on a clock obtained by dividing the same SSC (Spread Spectrum Clock: frequency spread clock). Drive the motor.

  By the way, printed circuit boards (hereinafter referred to as PCB boards) have recently been increasingly demanded for high density, high mounting, and low size. Therefore, for example, by mounting a high-function or additional-function device (electronic circuit, electronic device) on another board (referred to as option), the mounting area ratio of the main PCB can be reduced and the board can be reduced. Has been done. In conventional low-speed (for example, PCI, UART, etc.) buses, the restrictions on the buses and clocks given to the layout of the printed wiring are not so strict, so that they could be easily expanded as optional boards. The constraint here is a standard for the conductor being wound on the surface layer or inner layer of the PCB substrate. However, in high-speed serial interfaces such as PCI-EXPRESS, layout restrictions are more severe than those of conventional buses. Therefore, if the conventional method is used, the layout area of the main board is largely used due to the above restrictions. There is a problem that it ends up.

  FIG. 6 shows connections between devices mounted on the PCB substrate. Generally, when communicating between devices A and B, a bus 51p connecting them and a clock are required. This is shown in FIG. In some cases (depending on the device and bus conditions), connections may be made as shown in FIG. However, in the case of a high-speed serial interface such as PCI-EXPRESS, in order to use a frequency spread clock for reducing EMI (Electro Magnetic Induction) noise called SSC (Spread Spectrum Clock), SSCG 40p and Since there is a restriction that the frequency deviation of the clock between the A device 20p and the B device 30p is within ± 300 ppm, it is common to use the same PLL (Phase Locked Loop) in the same SSCG, and the connection diagram is shown in FIG. 6 Note that ppm means one millionth of the fundamental frequency. The fundamental frequency is, for example, 100 MHz, but may be other than that.

  By the way, when it is desired to add a device such as a C device between the A device 20p and the B device 30p, the main board on which the A and B devices are mounted generally has no space due to the recent demand for high mounting. For this reason, for example, a method in which a C device is mounted on an option board and connected through a connector is often used. This is shown in FIGS.

  In FIG. 7, when it is desired to add the function of the C device, the C device board 60p is mounted. When the function of the C device is not required, the A and B devices are connected by bus by mounting the through board 50p in which the connectors are connected only by the bus ((a) of FIG. 8). The C device function can be added without taking up the area of the main substrate 10p. For reference, FIG. 8A shows a connection diagram in which the through board 50p is mounted on the main board 10p, and FIG. 8B shows a C device board (option board) 60p instead of the through board 50p. Is a connection diagram in which is mounted on the main board 10p.

  By the way, signal lines such as clocks and buses are laid out on the substrate as shown in FIG. 9A and are basically laid out on the surface layer, but when there is no space to lay out, As shown in FIG. 9B, it is laid out in an inner layer other than the surface layer. For example, if there is no other signal, it is possible to lay out only on the surface layer as in Case 1, but if other signal lines must also be laid out at that position, either signal is transferred to Case 2. As in (4), it must be laid out in another layer. For example, when laying out to another layer, it is common to pass through by filling a through-through hole called VIA, which penetrates the upper and lower surface layers.

  However, in the case of a normal low-speed signal line, since it is low-speed, the influence is small even if it is affected by signal degradation or the like, so any connection method of Case 1 to Case 4 may be used (it may be laid out in the inner layer) However, in the case of PCI-EXPRESS, which is a high-speed serial transfer interface, it is a high-speed transmission path and the number of VIAs described above is limited. Since the signal quality is lowered only by providing the VIA, it is desirable to lay out only on the surface layer as much as possible as in Case 1.

  In consideration of the above, as shown in FIG. 7, the clocks A, B, C1, and C2, which have the above constraints, must be laid out, and if the constraints are observed, a large space is required. In some cases, the layout may not be possible. This leads to the recent increase in density.

  An object of the present invention is to enable an option board using a high-speed serial transfer interface to be mounted on a main board without taking up the layout area of the main board.

  In the present invention, the above object is achieved by mounting the SSCG for the high-speed serial transfer interface on the option board instead of the main board.

Specifically, an electronic circuit device of an electronic apparatus according to the present invention is provided with a plurality of main electronic circuit devices (20, 30) and an option board (50/60) for electrical connection to each main electronic circuit device. A main board (10) equipped with a plurality of main side connectors (22, 32), and a main side high-speed serial transfer interface (21, 31) for connecting each main side connector to each main electronic circuit device; and
A plurality of option side connectors (52, 53) for connecting to the main side connector, an option side high speed serial transfer interface (51) for connecting the option side connectors, and the main side and option side high speed serial transfer interface A first option board (50) equipped with an SSCG for providing a clock to; or
Option electronic circuit device (70), multiple option side connectors (62, 63) for connecting to the main side connector, option side high-speed serial transfer interface (71, 72) for connecting each option side connector to the option electronic circuit device And a second option board (60) equipped with an SSCG for supplying a clock to the main side and option side high-speed serial transfer interfaces.

  In addition, in parentheses, symbols attached to corresponding elements or equivalent elements of the embodiments shown in the drawings and described later are added for reference. The same applies to the following.

  In a known technique using a high-speed serial transfer interface, for example, PCI-EXPRESS, for example, it is standardized that SSCG is mounted on a motherboard as a main board and a clock is supplied to an add-in card as an option board from there. (For example, FIG. 8). However, by mounting the SSCG on the option board side as in the present invention (for example, FIG. 2), the number of clock layouts on the main board can be reduced, and the SSCG is also transferred to the option board side. A large space can be secured on the substrate. By replacing at least two types of boards when the function of the C device is necessary and when not necessary, the function of the C device can be added when necessary.

  In order to see the protocol of the high-speed serial transfer interface during debugging, there is a layout pattern called MID-BUS, which is conventionally mounted on a main board. Also, a measuring instrument clock is provided on the main board as a debugging clock (FIG. 10). However, in one embodiment of the present invention, these MID-BUS and instrument clock are mounted on an option board (FIG. 3). Thereby, a wider space can be secured on the main board.

  Conventionally, the SSCG dedicated power supply circuit 80p (FIG. 10) is provided on the main board 10p. However, in one embodiment of the present invention, the SSCG dedicated power supply circuit 64 (FIG. 3) is also provided on the option board. . This also ensures a wider space on the main board.

  One of the embodiments of the present invention (FIG. 4) is an electronic circuit device of a printer that prints a document of a personal computer on paper, and an aspect in which an optional through board is mounted on a main board is dedicated to a printing function. A mode in which an optional scanner ASIC (Application Specific IC) board is mounted on the main board instead of the through board has an image reading / distributing function and a copying function in addition to the printing function. In another embodiment (FIG. 5), the mode in which the optional through board is mounted on the main board is dedicated to image reading and distribution, but the mode in which the optional memory control ASIC board is mounted on the main board in place of the through board. Has a function of storing read images in a large-capacity memory such as an HDD in addition to image reading and distribution. Thus, the present invention can also be applied to electronic circuit devices of image processing apparatuses such as image forming apparatuses, image reading apparatuses, and copying apparatuses.

  Other objects and features of the present invention will become apparent from the following description with reference to the drawings.

Embodiment 1
FIG. 1 shows an electronic circuit arrangement of the main board 10, the first option board 50, and the second option board 60 (option) according to the first embodiment of the present invention. The main board 10 has a plurality of main electronic circuit devices 20 and 30, a plurality of main side connectors 22 and 32 for mounting the option board and electrically connecting to each main electronic circuit device 20 and 30, and each main side connector 22. , 32 are connected to the main electronic circuit devices 20, 30 on the main side high-speed serial transfer interfaces 21, 31.

  The first option board 50 includes a plurality of option side connectors 52 and 53 for connecting to the main side connectors 22 and 32, an option side high-speed serial transfer interface 51 for connecting the option side connectors, and the main side and option This is a through board equipped with an SSCG 40t for supplying a clock to the high-speed serial transfer interfaces 21, 31 and 51 on the side.

  The second option board 60 includes an option electronic circuit device 70, a plurality of option side connectors 62 and 63 for connecting to the main side connector, and an option side high-speed serial transfer interface 71 for connecting each option side connector to the option electronic circuit device. , 72 and an SSCG 40d for supplying a clock to the main-side and option-side high-speed serial transfer interfaces 21, 31, 71, 72, and an optional device board for function expansion.

  The first and second option boards 50 and 60 can be selectively mounted on the main board 10 and can be replaced. In other words, in an aspect of the electronic device that can select an option and having only a basic (minimum) function, the connectors 52 and 53 of the first option board 50 are connected to the connectors 22 and 32 of the main board 10 to connect the connectors shown in FIG. As shown in (a), the first option board 50 is mounted on the main board 10. With this mounting, the SSCG 40t on the first option board 50 is connected to the buses 21 and 31 of the main electronic circuit devices 20 and 30 through the connectors 52 and 53 with the clocks A and B which are SSCs. To give. The main electronic circuit devices 20 and 30 are connected by a bus 21, connectors 22 and 52, a bus 51, connectors 53 and 32, and a bus 31.

  In the function expansion mode having an option expansion function of an electronic device that can select an option, the connectors 62 and 63 of the second option board 60 are connected to the connectors 22 and 32 of the main board 10, so that (b) of FIG. ), The second option board 60 is mounted on the main board 10. With this attachment, the SSCG 40d on the second option board 60 is connected to the buses 21 and 31 of the main electronic circuit devices 20 and 30 through the connectors 62 and 63 by the SSCG 40d as the SSC. To give. On the C device 70 on the second option board 60, the SSCG 40d on the board 60 gives clocks C1 and C2 which are SSCs. The main electronic circuit device 20 and the extended function device 70 are connected by a bus 21, connectors 22, 62 and a bus 71, and the extended function device 70 and the main electronic circuit device 30 are connected by a bus 72, connectors 63, 32 and a bus 31. Has been.

  The high-speed serial transfer interfaces (21, 31, 51, 71, 72) of the present embodiment are all PCI-EXPRESS, and the SSCGs 40t, 40d are a reference clock generator, a spectrum spreader, and a PLL (Phase Locked Loop), respectively. In addition, a frequency divider is provided as necessary, and an SSC having a fundamental frequency of 100 MHz obtained by frequency-spreading the reference clock generated by the reference clock generator with a spectrum spreader is used as clocks A, B, C1, and C2. Output. The frequency deviation of each of the electronic circuit devices 20, 30, and 70 of the clocks A, B, C1, and C2 supplied by the SSCGs 40t and 40d is within ± 300 ppm in accordance with the PCI-EXPRESS standard.

  It is to be noted that a frequency divider for dividing the frequency-spread basic clock is provided in the SSCG, so that SSCs having different frequencies can be given to some devices. In addition, a plurality of PLLs may be provided in the SSCG, and a clock that is frequency-spread by a spectrum spreader may be applied to the plurality of PLLs so that a pulse output from each PLL can be selectively applied to each device.

Embodiment 2
FIG. 3 shows a modification of the second option substrate 60a. This is because the PCI-EXPRESS bus of the function expansion option board 60a is changed to buses 71a and 72a including a PCI-EXPRESS protocol monitoring bus (MID-BUS). A clock output pin is provided so that a Midbus probe (measuring instrument connector) can be attached and detached, and a dedicated power circuit 64 for SSCG is also provided on the option board 60a. Note that the through board (equivalent to 50) used in this embodiment is also provided with a dedicated power supply circuit for SSCG. Other configurations and functions are the same as those in the first embodiment.

  FIG. 4 shows a first example in which the first embodiment is applied to a printing apparatus having an image reading / distributing function and a copying function as extended functions. The A device 20a on the main board 10b communicates with a personal computer or other terminal device (not shown) via the communication interface 2 and responds to a print command given by the personal computer or other terminal device (facsimile etc.). The system controller 20a has a print processing function that converts print information into image image data and outputs the image data to an image data processing ASIC that is the B device 30a.

  In the following, personal computers or other terminal devices are collectively referred to as “personal computers”.

  The system controller 20a also has an image reading / distributing function for sending document reading image data output from the scanner 4 described later to a personal computer or the like. However, as shown in FIG. 4A, when the through board 50, which is the first option board, is connected to the main board 10b, this is recognized and the copying function and the image reading / distributing function are not executed. Then, the operation board 1 is set to the input / output mode for only the printing function. Therefore, the user cannot instruct copying and image reading from the operation board 1. Further, the system controller 20a does not respond to a document image reading instruction from a personal computer or the like.

  In the image data processing ASIC 30a, in addition to a print processing function for converting image data obtained by converting a document (document information) such as a personal computer into an image by the system controller 20a into image data suitable for image formation by the printer 3, Although there is a copy processing function for converting read image data generated by the scanner 4 to be described later into print image data suitable for image formation by the printer 3, as shown in FIG. 4A, a through board 50 is provided on the main board 10b. Is connected, the system controller 20a gives only a print instruction for designating only the print processing function to the image data processing ASIC 30a.

  However, as shown in FIG. 4B, when the option board 60 which is the second option board equipped with the scanner ASIC as the C device 70 is mounted on the main board 10b, the system controller 20a When the ASIC board 60 is recognized, the operation board 1 is set to an input / output mode for the printing function, the image reading / distributing function, and the copying function. The system controller 20a responds to a document image reading instruction from a personal computer or the like.

  When the user designates a copy mode on the operation board 1, sets an original on the scanner 4, designates copy conditions and operates a start key, the scanner 4 reads an image of the original and sends image data to the scanner ASIC 70. The scanner ASIC 70 applies read distortion correction to the image data and applies image area separation or the like to identify whether the copy is illegal or not, and when the copy is not illegal, sends the image data to the image data processing ASIC 30a. The image data processing ASIC 30 a converts the read image data into printing image data that matches the image forming characteristics of the printer 3 and outputs the image data to the printer 3. When the user designates an image reading / distributing function from the operation board 1 or a personal computer, sets a document on the scanner 4, designates a distribution destination, and operates a start key, the scanner 4 reads the image of the document and reads it into image data. Distortion correction is applied and image area separation or the like is applied to identify whether or not the image is illegally read. When the image is not read illegally, it is transmitted to a personal computer or the like or a specified distribution destination via the system controller 20a (and communication interface 2). . In the print function of printing a document (document) from a personal computer or the like with the printer 3, the scanner ASIC 70 outputs the image data generated by the system controller 20a to the image data processing ASIC 30a.

  The scanner ASIC 70 also has an image processing function for image data input / output to / from a personal computer or the like. In the case of image reading and distribution, the scanner ASIC 70 converts the read image data generated by the scanner 4 into JPEG RGB converted image data. Output to the system controller 20a. In the case of image reading and delivery, if the system controller 20a specifies image data of the recording color YMCK to be output to a printer or facsimile, the scanner ASIC 70 reads the read image data generated by the scanner 4 into the image data processing ASIC 30a. The image data is converted into YMCK image data and then output to the system controller 20a.

  FIG. 5 shows a second example in which the first embodiment is applied to an image reading apparatus having a read image storage function as an extended function. The A device 20a on the main board 10b communicates with a personal computer or the like (not shown) via the communication interface 2 and reads an image by the scanner 4 in response to an image reading instruction given by the personal computer or the like. The system controller 20a has an image reading / delivery function for transmitting to the personal computer or the like or a designated delivery destination. This system controller 20a has an HDD (Hard Disk Driver) and other large-capacity memory, which will be described later, an image storage function for storing an image (image data) read by a scanner and an image provided by a personal computer, and a personal computer. There is also an image processing function for image data input / output.

  However, as shown in FIG. 5A, when the through board 50 as the first option board is connected to the main board 10c, the system controller 20a recognizes this, and the image storage function and image The processing function is not executed, and the operation board 1 is set to an input / output mode for only the image reading / distributing function. Therefore, the user cannot instruct image storage or image processing from the operation board 1. The system controller 20a does not respond to an image storage instruction or an image processing instruction from a personal computer or the like.

  The scanner ASIC 30b applies read distortion correction to image data generated by the scanner 4 reading an image on a document, applies image area separation, and the like to identify whether the copy is illegal. Output image data. As shown in FIG. 5A, when the through board 50 is connected to the main board 10c, the image data output from the scanner ASIC 30b is transferred to the system controller 20b through the through board 50, and the controller 20b The data is sent to a personal computer or the like via the communication interface 2.

  As shown in FIG. 5B, when the option board 60b, which is the second option board, equipped with the memory control ASIC as the C device 70 is mounted on the main board 10b, the system controller 20a & When the image processing ASIC board 60b is recognized, the operation board 1 is set to the input / output mode for the image reading / distributing function, the image storing function, and the image processing. The system controller 20a responds to instructions for reading a document image, storing an image, and processing an image from a personal computer or the like.

  When the user designates image reading / distribution on the operation board 1 or a personal computer, inputs the distribution destination and the image processing mode and operates the start key as necessary, the scanner 4 reads the image of the original and reads the image data into the scanner ASIC. Send to 30b. The scanner ASIC 30b applies read distortion correction to the image data and applies image area separation or the like to identify whether or not the image is illegally read. When the image does not become illegally read, the image data is sent to the memory control & image processing ASIC 70. To do. The memory control & image processing ASIC 70 temporarily stores it in its internal or external (for example, HDD 5) memory, and when there is an instruction to convert to JPEG during image processing, it reads the image data read by the scanner. The data is converted into JPEG and sent to the system controller 20b. The system controller 20b transmits image data to a distribution destination when a personal computer or the like that has given a reading instruction or a distribution destination is specified.

  If image storage is specified, as in the case of image reading and delivery described above, the scanned image is temporarily stored, and if image processing is specified, corresponding image processing (for example, JPEG conversion) is performed. When a reading instruction is given to a personal computer or the like or when a distribution destination is specified, image data is transmitted to the distribution destination, and the processed image data is connected to a memory control & image processing ASIC 70 such as an HDD 5. Register in the large memory. After that, when there is a valid transfer instruction for the image registered in the large-capacity memory from the operation board 1 or a personal computer or the like to the system controller 20b, via the memory control & image processing ASIC 70, The designated image (image data) in the large-capacity memory is read out and transmitted to the delivery destination when there is a personal computer or the like to which a transfer instruction is given or a delivery destination is designated. Further, the system controller 20b registers an image sent from the personal computer or the like via the communication interface 2 in the large capacity memory. When image processing is designated, the designated image processing is performed at the time of registration or reading of the image with respect to the large-capacity memory, and then registered or transferred.

  Among the above image processing functions are conversion of image data type, writing / reading of image data to / from image memory, scaling / rotation, editing (trimming, masking, shift, etc.), adjustment of tone, etc. is there. The data type conversion includes conversion of read image data generated by the scanner 4 into JPEG RGB data, conversion of the read image and JPEG data into print color YMCK data for printing or facsimile transmission, On the contrary, conversion of YMCK data by JPEG to RGB data is included. Image adjustment includes brightness, contrast, color tone, and color conversion. The user can designate these image processing by using the operation board 1 or a personal computer, and can manipulate the parameters of the image processing.

FIG. 2 is a block diagram showing an outline of the configuration of a main board 10, a first option board 50, and a second option board 60 according to the first embodiment of the present invention. (A) is a block diagram showing an outline of the electronic circuit device mounted on the first option board 50 on the main board 10 shown in FIG. 1, and (b) is mounted on the second option board 60 on the main board 10. It is a block diagram which shows the outline | summary of an electronic circuit device. It is a block diagram which shows the outline | summary of a structure of the 2nd option board | substrate 60 of 2nd Embodiment of this invention. (A) is a block diagram which shows the outline | summary of the electronic circuit device of 1st form of 1st Example of this invention, (b) is a block diagram which shows the outline | summary of the electronic circuit device of 2nd form. (A) is a block diagram which shows the outline | summary of the electronic circuit device of 1st form of 2nd Example of this invention, (b) is a block diagram which shows the outline | summary of the electronic circuit device of 2nd form. (A) is a block diagram which shows the structural outline of an example of the conventional electronic circuit device, (b) shows another example. It is a block diagram which shows the structure outline | summary of an example of the conventional electronic circuit device which can expand a function. (A) is a block diagram showing a configuration outline of an electronic circuit device in which the through board 50p is mounted on the main substrate 10p shown in FIG. 7, and (b) is an electronic circuit device in which the device board 60p is mounted on the main substrate 10p. It is a block diagram which shows the structure outline | summary. FIG. 4 is an enlarged cross-sectional view of a conventional main board, in which (a) shows a case where signal lines are laid out on the surface on the device mounting side and the number of wires is relatively small, and (b) shows signal lines on the device mounting surface. Shows a case where the number of wirings is relatively large and is laid out on the opposite surface. It is a block diagram which shows the structure outline | summary of another example of the conventional electronic circuit device.

Explanation of symbols

21, 31, 51, 71, 72: PCI-EXPRESS bus 21pa, 31pa, 71a, 72a, which is a high-speed serial transfer interface: PCI-EXPRESS bus including MID-BUS

Claims (10)

A plurality of main electronic circuit devices, a plurality of main side connectors for mounting an option board and electrically connecting to each main electronic circuit device, and a main side high-speed serial transfer interface for connecting each main side connector to each main electronic circuit device A main board equipped with, and
A plurality of option-side connectors for connecting to the main-side connector, an option-side high-speed serial transfer interface for connecting between the option-side connectors, and an SSCG for supplying a clock to the main-side and option-side high-speed serial transfer interface; First option board equipped with
An electronic circuit device for an electronic device. A plurality of main electronic circuit devices, a plurality of main side connectors for mounting an option board and electrically connecting to each main electronic circuit device, and a main side high-speed serial transfer interface for connecting each main side connector to each main electronic circuit device A main board equipped with, and
Option electronic circuit device, a plurality of option side connectors for connecting to the main side connector, an option side high speed serial transfer interface for connecting each option side connector to the option electronic circuit device, and the main side and option side high speed serial transfer A second optional board equipped with an SSCG for providing a clock to the interface;
An electronic circuit device for an electronic device. A plurality of main electronic circuit devices, a plurality of main side connectors for mounting an option board and electrically connecting to each main electronic circuit device, and a main side high-speed serial transfer interface for connecting each main side connector to each main electronic circuit device A main board equipped with, and
A plurality of option-side connectors for connecting to the main-side connector, an option-side high-speed serial transfer interface for connecting between the option-side connectors, and an SSCG for supplying a clock to the main-side and option-side high-speed serial transfer interface; Or an optional electronic circuit device, a plurality of option side connectors for connecting to the main side connector, an option side high-speed serial transfer interface for connecting each option side connector to the option electronic circuit device, and A second option board equipped with an SSCG for supplying a clock to the main side and option side high-speed serial transfer interfaces;
An electronic circuit device for an electronic device. A plurality of main electronic circuit devices, a plurality of main side connectors for mounting an option board and electrically connecting to each main electronic circuit device, and a main side high-speed serial transfer interface for connecting each main side connector to each main electronic circuit device , Equipped with a main board;
A plurality of option-side connectors for connecting to the main-side connector, an option-side high-speed serial transfer interface for connecting between the option-side connectors, and an SSCG for supplying a clock to the main-side and option-side high-speed serial transfer interface; Or an option electronic circuit device, a plurality of option side connectors for connecting to the main side connector, and an option side high-speed serial transfer interface for connecting each option side connector to the option electronic circuit device And a second option board equipped with a SSCG for supplying a clock to the main side and option side high-speed serial transfer interfaces; It was connected by mounting the electronic circuit device of the electronic device.   5. The first option board mounted on the main board can be detached from the main board by detaching the option board connector from the main board connector, and the second option board can be mounted on the main board instead. Electronic circuit device for electronic equipment.   5. The second option board mounted on the main board can be removed from the main board by detaching the option board connector from the main board connector, and the first option board can be mounted on the main board instead. Electronic circuit device for electronic equipment.   The electronic circuit device of the electronic device according to any one of claims 1 to 6, wherein a frequency deviation of a clock supplied from the SSCG in a main electronic circuit device on a main board is within ± 300 ppm.   The electronic circuit device of the electronic device according to any one of claims 1 to 7, wherein a bus for monitoring the protocol of the high-speed serial transfer interface is mounted on the option board.   9. The electronic circuit device of the electronic device according to claim 8, wherein a clock output pin to a protocol observer is provided on the option board; and the SSCG supplies a clock to the clock output pin.   An image processing apparatus comprising the electronic circuit device according to claim 1.

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