JP5257860B2 - Electronics - Google Patents

Description

  The present invention relates to the deployment of electronic circuit devices on printed circuit boards of electronic equipment.

  In the image forming apparatus described in Patent Literature 1, an option board for function expansion can be additionally connected to the main control board, and when there is a request for outputting an operation manual, the main control unit searches for the added option board. Then, the detected operation manual for the function of the option board is read from the image storage unit and displayed on the display of the operation unit. In the image forming apparatus described in Patent Document 2, in order to reduce electromagnetic induction noise generated by motor driving, a basic clock for driving a polygon motor, a drum driving motor, a sheet feeding motor, and a fixing motor of a laser printer is set as SSCG ( In order to avoid interference between driven systems due to frequency spread, each generated based on a clock obtained by dividing the same SSC (Spread Spectrum Clock: frequency spread clock). Drive the motor.

  By the way, printed circuit boards (hereinafter referred to as PCB boards) have recently been increasingly demanded for high density, high mounting, and low size. Therefore, for example, by mounting a high-function or additional-function device (electronic circuit, electronic device) on another board (referred to as option), the mounting area ratio of the main PCB can be reduced and the board can be reduced. Has been done. In conventional low-speed (for example, PCI, UART, etc.) buses, the restrictions on the buses and clocks given to the layout of the printed wiring are not so strict, so that they could be easily expanded as optional boards. The constraint here is a standard for the conductor being wound on the surface layer or inner layer of the PCB substrate. However, in high-speed serial interfaces such as PCI-EXPRESS, the restrictions on the layout are more severe than those of the conventional bus. There is a problem that it ends up.

  FIG. 6 shows connections between devices mounted on the PCB substrate. Generally, when communicating between devices A and B, a bus 51p connecting them and a clock are required. This is shown in FIG. In some cases (depending on the device and bus conditions), the connection may be as shown in FIG. However, in the case of a high-speed serial interface such as PCI-EXPRESS, in order to use a spread spectrum clock for reducing EMI (Electro Magnetic Induction) noise called SSC (Spread Spectrum Clock), SSCG 40p and Since there is a restriction that the frequency deviation of the clock between the A device 20p and the B device 30p is within ± 300 ppm, it is common to use the same PLL (Phase Locked Loop) in the same SSCG, and the connection diagram is shown in FIG. 6 Note that ppm means one millionth of the fundamental frequency. The fundamental frequency is, for example, 100 MHz, but may be other than that.

  By the way, when it is desired to add a device such as a C device between the A device 20p and the B device 30p, the main board on which the A and B devices are mounted generally has no space due to the recent demand for high mounting. For this reason, for example, a method in which a C device is mounted on an option board and connected through a connector is often used. This is shown in FIGS.

  In FIG. 7, when it is desired to add the function of the C device, the C device board 60p is mounted. When the function of the C device is not required, the A and B devices are connected by bus by mounting the through board 50p in which the connectors are connected only by the bus ((a) of FIG. 8). The C device function can be added without taking up the area of the main substrate 10p. For reference, FIG. 8A shows a connection diagram in which the through board 50p is mounted on the main board 10p, and FIG. 8B shows a C device board (option board) 60p instead of the through board 50p. Is a connection diagram in which is mounted on the main board 10p.

  By the way, signal lines such as clocks and buses are laid out on the substrate as shown in FIG. 9A and are basically laid out on the surface layer, but when there is no space to lay out, As shown in FIG. 9B, it is laid out in an inner layer other than the surface layer. For example, if there is no other signal, it is possible to lay out only on the surface layer as in Case 1, but if other signal lines must also be laid out at that position, either signal is transferred to Case 2. As in (4), it must be laid out in another layer. For example, when laying out to another layer, it is common to pass through by filling a through-through hole called VIA, which penetrates the upper and lower surface layers.

  However, in the case of a normal low-speed signal line, since it is low-speed, the influence is small even if it is affected by signal degradation or the like, so any connection method of Case 1 to Case 4 may be used (it may be laid out in the inner layer) However, in the case of PCI-EXPRESS, which is a high-speed serial transfer interface, it is a high-speed transmission path and the number of VIAs described above is limited. Since the signal quality is lowered only by providing the VIA, it is desirable to lay out only on the surface layer as much as possible as in Case 1.

JP-A-2005-7781 JP-A-2005-88287

  In consideration of the above, as shown in FIG. 7, the clocks A, B, C1, and C2, which have the above constraints, must be laid out, and if the constraints are observed, a large space is required. In some cases, the layout may not be possible. This leads to the recent increase in density.

  An object of the present invention is to enable an option board using a frequency spread clock to be mounted on a main board without taking up the layout area of the main board.

  In the present invention, the above object is achieved by mounting the frequency spread clock generating means on the option board instead of the main board.

Specifically, the electronic device of the present invention is
(1) a first electronic circuit board (10) having a first plurality of electronic devices (20, 30) and first connection means (22, 32);
A frequency spread clock generating means (40t) and a second connecting means (52, 53) for generating a clock signal having a spread frequency, or the frequency spread clock generating means (40d) and the second connecting means; And a second electronic circuit board (50/60) selectively mounted on the first electronic circuit board having a second electronic device (70) ;
An electronic device having
The second electronic circuit board (50/60) is formed of the first plurality of electronic devices (20, 30) by the first connection means (22, 32) and the second connection means (62, 63 ). one and a bus connected between the other, said first plurality of electronic devices included a clock signal generated by the spread spectrum clock generating means to the first electronic circuit board (10) via said bus Electronic equipment that outputs to (20, 30) .

  In addition, in parentheses, symbols attached to corresponding elements or equivalent elements of the embodiments shown in the drawings and described later are added for reference. The same applies to the following.

For example, the standard states that a frequency spread clock generating means (SSCG) is mounted on a motherboard as a main board, and a clock signal is supplied from there to an add-in card as an option board (for example, FIG. 8). However, as in the present invention, instead of the first electronic circuit board (10) corresponding to the main board, the second electronic circuit board (50, 60) corresponding to the option board is provided with the frequency spread clock generating means ( 40d / 40t) (for example, FIG. 2), the number of clock layouts on the first electronic circuit board (main board) can be reduced, and the frequency spread clock generation means can be used as the second electronic circuit board (optional). By transferring to the (substrate) side, a wide space can be secured on the first electronic circuit board. When the function of an optional device is required, the function of the optional device can be added when necessary by connecting the second electronic circuit board equipped with the device to the first electronic circuit board by the bus.

(2) When the second electronic circuit board (60) includes the frequency spread clock generation means (40d), the second connection means (62, 63), and the second electronic device (70), The electronic apparatus according to (1), wherein the clock signal generated by the frequency spread clock generating means (40d) is also output to the second electronic device (70).

  (3) The electronic device according to (1) or (2), wherein the bus is a serial transfer interface. For example, PCI-EXPRESS, which is a high-speed serial transfer interface, is used.

  (4) A protocol monitoring bus for the serial transfer interface is mounted on the second electronic circuit board; the electronic device according to (3) above.

In order to see the protocol of the high-speed serial transfer interface during debugging, there is a layout pattern called MID-BUS, which is conventionally mounted on a main board corresponding to the first electronic circuit board. Further, a measuring instrument clock signal is provided on the main board as a debugging clock (FIG. 10). However, in this embodiment (4), these MID-BUS and measuring instrument clock are mounted on the second electronic circuit board corresponding to the option board (FIG. 3). Thereby, a wider space can be secured on the main board.

  (5) There is a clock output pin to the protocol observer on the second electronic circuit board; the frequency spread clock generating means supplies a clock to the clock output pin;

(6) The frequency deviation of the clock signal supplied by the frequency spread clock generating means in the first electronic device of the first electronic circuit board is within ± 300 ppm; any one of (1) to (5) above The electronic device according to one.

  (7) The electronic device according to any one of (1) to (5), wherein a dedicated power supply circuit (64: FIG. 3) of the frequency spread clock generating means is also provided on the second electronic circuit board. This also makes it possible to secure a larger space on the first electronic circuit board corresponding to the main board.

The outline of the configuration of the main board 10 that is the first electronic circuit board and the first option board 50 and the second option board 60 that are each the second electronic circuit board according to the first embodiment of the present invention. FIG. (A) is a block diagram showing an outline of an electronic apparatus in which the first option board 50 is mounted on the main board 10 shown in FIG. 1, and (b) is an electronic in which the second option board 60 is mounted on the main board 10. It is a block diagram which shows the outline | summary of an apparatus. It is a block diagram which shows the outline | summary of a structure of the 2nd option board | substrate 60 of 2nd Embodiment of this invention. (A) is a block diagram which shows the outline | summary of the electronic device of 1st form of 1st Example of this invention, (b) is a block diagram which shows the outline | summary of the electronic device of 2nd form. (A) is a block diagram which shows the outline | summary of the electronic device of 1st form of 2nd Example of this invention, (b) is a block diagram which shows the outline | summary of the electronic device of 2nd form. (A) is a block diagram which shows the structural outline of an example of the conventional electronic device, (b) shows another example. It is a block diagram which shows the structure outline | summary of an example of the conventional electronic device which can expand a function. (A) is a block diagram showing an outline of the configuration of an electronic apparatus in which the through board 50p is mounted on the main board 10p shown in FIG. 7, and (b) is a configuration of the electronic apparatus in which the device board 60p is mounted on the main board 10p. It is a block diagram which shows an outline. FIG. 4 is an enlarged cross-sectional view of a conventional main board, in which (a) shows a case where signal lines are laid out on the surface on the device mounting side and the number of wires is relatively small, and (b) shows signal lines on the device mounting surface. Shows a case where the number of wirings is relatively large and is laid out on the opposite surface. It is a block diagram which shows the structure outline | summary of another example of the conventional electronic device.

  Other objects and features of the present invention will become apparent from the following description with reference to the drawings.

Embodiment 1
FIG. 1 shows a main board 10 that is a first electronic circuit board and a first option board 50 and a second option board 60 (options), each of which is a second electronic circuit board, according to the first embodiment of the present invention. ) Shows an electronic circuit arrangement. The main board 10 has a plurality of main electronic circuit devices 20 and 30, a plurality of main side connectors 22 and 32 for mounting the option board and electrically connecting to each main electronic circuit device 20 and 30, and each main side connector 22. , 32 are connected to the main electronic circuit devices 20, 30 on the main side high-speed serial transfer interfaces 21, 31.

  The first option board 50 includes a plurality of option side connectors 52 and 53 for connecting to the main side connectors 22 and 32, an option side high-speed serial transfer interface 51 for connecting the option side connectors, and the main side and option This is a through board equipped with an SSCG 40t for supplying a clock to the high-speed serial transfer interfaces 21, 31 and 51 on the side.

  The second option board 60 includes an option electronic circuit device 70, a plurality of option side connectors 62 and 63 for connecting to the main side connector, and an option side high-speed serial transfer interface 71 for connecting each option side connector to the option electronic circuit device. , 72 and an SSCG 40d for supplying a clock to the main-side and option-side high-speed serial transfer interfaces 21, 31, 71, 72, and an optional device board for function expansion.

  The first and second option boards 50 and 60 can be selectively mounted on the main board 10 and can be replaced. In other words, in an aspect of the electronic device that can select an option and having only a basic (minimum) function, the connectors 52 and 53 of the first option board 50 are connected to the connectors 22 and 32 of the main board 10 to connect the connectors shown in FIG. As shown in (a), the first option board 50 is mounted on the main board 10. With this mounting, the SSCG 40t on the first option board 50 is connected to the buses 21 and 31 of the main electronic circuit devices 20 and 30 through the connectors 52 and 53 with the clocks A and B which are SSCs. To give. The main electronic circuit devices 20 and 30 are connected by a bus 21, connectors 22 and 52, a bus 51, connectors 53 and 32, and a bus 31.

  In the function expansion mode having an option expansion function of an electronic device that can select an option, the connectors 62 and 63 of the second option board 60 are connected to the connectors 22 and 32 of the main board 10, so that (b) of FIG. ), The second option board 60 is mounted on the main board 10. With this attachment, the SSCG 40d on the second option board 60 is connected to the buses 21 and 31 of the main electronic circuit devices 20 and 30 through the connectors 62 and 63 with the clocks A and B as the SSC. To give. On the C device 70 on the second option board 60, the SSCG 40d on the board 60 gives clocks C1 and C2, which are SSCs. The main electronic circuit device 20 and the extended function device 70 are connected by a bus 21, connectors 22, 62 and a bus 71, and the extended function device 70 and the main electronic circuit device 30 are connected by a bus 72, connectors 63, 32 and a bus 31. Has been.

  All of the high-speed serial transfer interfaces (21, 31, 51, 71, 72) of the present embodiment are PCI-EXPRESS, and the SSCGs 40t, 40d are a reference clock generator, a spectrum spreader, and a PLL (Phase Locked Loop), respectively. ) And, if necessary, a frequency divider, a reference clock generated by the reference clock generator is spread by a spectrum spreader, and an SSC having a fundamental frequency of 100 MHz is converted into clocks A, B, C1, C2 Output as. The frequency deviation of each of the electronic circuit devices 20, 30, and 70 of the clocks A, B, C1, and C2 supplied by the SSCGs 40t and 40d is within ± 300 ppm in accordance with the PCI-EXPRESS standard.

  It is to be noted that a frequency divider for dividing the frequency-spread basic clock is provided in the SSCG, so that SSCs having different frequencies can be given to some devices. In addition, a plurality of PLLs may be provided in the SSCG, and a clock that is frequency-spread by a spectrum spreader may be applied to the plurality of PLLs so that a pulse output from each PLL can be selectively applied to each device.

Embodiment 2
FIG. 3 shows a modification of the second option substrate 60a. This is because the PCI-EXPRESS bus of the function expansion option board 60a is changed to buses 71a and 72a including a PCI-EXPRESS protocol monitoring bus (MID-BUS), and the option board 60a has a connection to the protocol observer. A clock output pin is provided so that a Midbus probe (measuring instrument connector) can be attached and detached, and a dedicated power circuit 64 for SSCG is also provided on the option board 60a. Note that the through board (50 equivalent) used in this embodiment is also provided with a dedicated power supply circuit for SSCG. Other configurations and functions are the same as those in the first embodiment.

Example 1
FIG. 4 shows a first example in which the first embodiment is applied to a printing apparatus having an image reading / distributing function and a copying function as extended functions. The A device 20a on the main board 10b communicates with a personal computer or other terminal device (not shown) via the communication interface 2 and responds to a print command given by the personal computer or other terminal device (facsimile etc.). The system controller 20a has a print processing function that converts print information into image image data and outputs the image data to an image data processing ASIC that is the B device 30a.

  In the following, personal computers or other terminal devices are collectively referred to as “personal computers”.

  The system controller 20a also has an image reading / distributing function for sending document reading image data output from the scanner 4 described later to a personal computer or the like. However, as shown in FIG. 4A, when the through board 50, which is the first option board, is connected to the main board 10b, this is recognized and the copying function and the image reading / distributing function are not executed. Then, the operation board 1 is set to the input / output mode for only the printing function. Therefore, the user cannot instruct copying and image reading from the operation board 1. Further, the system controller 20a does not respond to a document image reading instruction from a personal computer or the like.

  In the image data processing ASIC 30a, in addition to a print processing function for converting image data obtained by converting a document (document information) such as a personal computer into an image by the system controller 20a into image data suitable for image formation by the printer 3, Although there is a copy processing function for converting read image data generated by the scanner 4 to be described later into print image data suitable for image formation by the printer 3, as shown in FIG. 4A, a through board 50 is provided on the main board 10b. Is connected, the system controller 20a gives only a print instruction for designating only the print processing function to the image data processing ASIC 30a.

  However, as shown in FIG. 4B, when the option board 60 which is the second option board equipped with the scanner ASIC as the C device 70 is mounted on the main board 10b, the system controller 20a When the ASIC board 60 is recognized, the operation board 1 is set to an input / output mode for the printing function, the image reading / distributing function, and the copying function. The system controller 20a responds to a document image reading instruction from a personal computer or the like.

  When the user designates a copy mode on the operation board 1, sets an original on the scanner 4, designates copy conditions and operates a start key, the scanner 4 reads an image of the original and sends image data to the scanner ASIC 70. The scanner ASIC 70 applies read distortion correction to the image data and applies image area separation or the like to identify whether the copy is illegal or not, and when the copy is not illegal, sends the image data to the image data processing ASIC 30a. The image data processing ASIC 30 a converts the read image data into printing image data that matches the image forming characteristics of the printer 3 and outputs the image data to the printer 3. When the user designates an image reading / distributing function from the operation board 1 or a personal computer, sets a document on the scanner 4, designates a distribution destination, and operates a start key, the scanner 4 reads the image of the document and reads it into image data. Distortion correction is applied and image area separation or the like is applied to identify whether or not the image is illegally read. When the image is not read illegally, it is transmitted to a personal computer or the like or a specified distribution destination via the system controller 20a (and communication interface 2). . In the print function of printing a document (document) from a personal computer or the like with the printer 3, the scanner ASIC 70 outputs the image data generated by the system controller 20a to the image data processing ASIC 30a.

The scanner ASIC 70 also has an image processing function for image data input / output to / from a personal computer or the like. In the case of image reading and distribution, the scanner ASIC 70 converts the read image data generated by the scanner 4 into JPEG RGB converted image data. Output to the system controller 20a. In the case of image reading and delivery, if the system controller 20a specifies image data of the recording color YMCK to be output to a printer or facsimile, the scanner ASIC 70 reads the read image data generated by the scanner 4 into the image data processing ASIC 30a. The image data is converted into YMCK image data and then output to the system controller 20a.
-Example 2-
FIG. 5 shows a second example in which the first embodiment is applied to an image reading apparatus having a read image storage function as an extended function. The A device 20a on the main board 10b communicates with a personal computer or the like (not shown) via the communication interface 2 and reads an image by the scanner 4 in response to an image reading instruction given by the personal computer or the like. The system controller 20a has an image reading / delivery function for transmitting to the personal computer or the like or a designated delivery destination. This system controller 20a has an HDD (Hard Disk Driver) and other large-capacity memory, which will be described later, an image storage function for storing an image (image data) read by a scanner and an image provided by a personal computer, and a personal computer. There is also an image processing function for image data input / output.

  However, as shown in FIG. 5A, when the through board 50 as the first option board is connected to the main board 10c, the system controller 20a recognizes this, and the image storage function and image The processing function is not executed, and the operation board 1 is set to an input / output mode for only the image reading / distributing function. Therefore, the user cannot instruct image storage or image processing from the operation board 1. The system controller 20a does not respond to an image storage instruction or an image processing instruction from a personal computer or the like.

  The scanner ASIC 30b applies read distortion correction to image data generated by the scanner 4 reading an image on a document, applies image area separation, and the like to identify whether the copy is illegal. Output image data. As shown in FIG. 5A, when the through board 50 is connected to the main board 10c, the image data output from the scanner ASIC 30b is transferred to the system controller 20b through the through board 50, and the controller 20b The data is sent to a personal computer or the like via the communication interface 2.

  As shown in FIG. 5B, when the option board 60b, which is the second option board, equipped with the memory control ASIC as the C device 70 is mounted on the main board 10b, the system controller 20a & When the image processing ASIC board 60b is recognized, the operation board 1 is set to the input / output mode for the image reading / distributing function, the image storing function, and the image processing. The system controller 20a responds to instructions for reading a document image, storing an image, and processing an image from a personal computer or the like.

  When the user designates image reading / distribution on the operation board 1 or a personal computer, inputs the distribution destination and the image processing mode and operates the start key as necessary, the scanner 4 reads the image of the original and reads the image data into the scanner ASIC. Send to 30b. The scanner ASIC 30b applies read distortion correction to the image data and applies image area separation or the like to identify whether or not the image is illegally read. When the image does not become illegally read, the image data is sent to the memory control & image processing ASIC 70. To do. The memory control & image processing ASIC 70 temporarily stores it in its internal or external (for example, HDD 5) memory, and when there is an instruction to convert to JPEG during image processing, it reads the image data read by the scanner. The data is converted into JPEG and sent to the system controller 20b. The system controller 20b transmits image data to a distribution destination when a personal computer or the like that has given a reading instruction or a distribution destination is specified.

  If image storage is specified, as in the case of image reading and delivery described above, the scanned image is temporarily stored, and if image processing is specified, corresponding image processing (for example, JPEG conversion) is performed. Then, when there is a personal computer or the like to which a reading instruction is given or a distribution destination is specified, the image data is transmitted to the distribution destination, and the image processed data is connected to the memory control & image processing ASIC 70 such as the HDD 5 Register in the large memory. After that, when there is a valid transfer instruction for the image registered in the large-capacity memory from the operation board 1 or a personal computer or the like to the system controller 20b, via the memory control & image processing ASIC 70, The designated image (image data) in the large-capacity memory is read out and transmitted to the delivery destination when there is a personal computer or the like to which a transfer instruction is given or a delivery destination is designated. Further, the system controller 20b registers an image sent from the personal computer or the like via the communication interface 2 in the large capacity memory. When image processing is designated, the designated image processing is performed at the time of registration or reading of the image with respect to the large-capacity memory, and then registered or transferred.

  Among the above image processing functions are conversion of image data type, writing / reading of image data to / from image memory, scaling / rotation, editing (trimming, masking, shift, etc.), adjustment of tone, etc. is there. The data type conversion includes conversion of read image data generated by the scanner 4 into JPEG RGB data, conversion of the read image and JPEG data into print color YMCK data for printing or facsimile transmission, On the contrary, conversion of YMCK data by JPEG to RGB data is included. Image adjustment includes brightness, contrast, color tone, and color conversion. The user can designate these image processing by using the operation board 1 or a personal computer, and can manipulate the parameters of the image processing.

21, 31, 51, 71, 72: high-speed serial transfer interfaces
PCI-EXPRESS buses 21pa, 31pa, 71a, 72a: including MID-BUS
PCI-EXPRESS bus

Claims (7)

A first electronic circuit board having a first plurality of electronic devices and first connecting means;
The frequency spreading clock generating means for generating a clock signal having a frequency spread and the second connecting means, or the frequency spreading clock generating means, the second connecting means, and the second electronic device. A second electronic circuit board selectively mounted on one electronic circuit board ;
An electronic device having
The second electronic circuit board, said first connecting means and a bus connection with the one and the other of said first plurality of electronic devices by the second connecting means, caused by the spread spectrum clock generating means An electronic apparatus that outputs the clock signal to the first plurality of electronic devices included in the first electronic circuit board via the bus. When the second electronic circuit board has the frequency spread clock generation means, the second connection means, and the second electronic device, the clock signal generated by the frequency spread clock generation means is used as the second electronic device. The electronic device according to claim 1, wherein the electronic device is also output.   The electronic device according to claim 1, wherein the bus is a serial transfer interface.   The electronic device according to claim 3, wherein a protocol monitoring bus of the serial transfer interface is mounted on the second electronic circuit board. 5. The electronic device according to claim 4, wherein there is a clock output pin to a protocol observer on the second electronic circuit board; and the frequency spread clock generating means supplies a clock signal to the clock output pin. 6. The frequency deviation of the clock signal supplied by the frequency spread clock generator in the first plurality of electronic devices of the first electronic circuit board is within ± 300 ppm; The electronic device described.   The electronic apparatus according to any one of claims 1 to 5, wherein a dedicated power supply circuit for the frequency spread clock generating means is also provided on the second electronic circuit board.

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