JP2005250575A - Inspection method for storage system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately and easily inspect transmission when data and a clock signal designating timing of the data input are transmitted in parallel. <P>SOLUTION: When inspection of transmission, in which the data and the clock signal designating input timing of the data are transmitted in parallel, is carried out in inspection of the storage system having a plurality of disk drive devices, the data having pulse waveform temporarily changed to a predetermined condition by the predetermined data output timing and the clock signal are outputted on the transmission side of the transmission. On the receipt side of the transmission, the data and the clock signal are fetched in, and by the predetermined data input timing generated synchronously with the fetched-in clock signal, the inputted data are latched. Based on the latched data, it is inspected whether the data are transmitted normally or not. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a storage system inspection method, and is particularly suitable for application to a storage system inspection that is used as a large-capacity data storage device in an information processing system and requires high reliability and a high-speed response to an input / output request. Technology.

  Conventionally, a storage system called RAID (Redundant Array of Inexpensive Disks) in which a large number of hard disk drive devices as storage devices are prepared and data is distributed and stored in the many hard disk devices has been put into practical use. Has been.

  This storage system is composed of not only hard disk drive devices that store data but also conversion units and control units that function as drive device interfaces, and each unit is connected by a bus or the like to transfer data to each other. Thus, the system configuration is such that externally input data is stored and stored data is read.

  Since the data storage itself is performed in a distributed manner on each hard disk drive device, if the data transfer to each drive device is not correctly synchronized, the data stored dispersedly in each hard disk drive device is read and assembled correctly. Therefore, it is essential that the data transfer in each part in the storage system can be performed correctly. Therefore, it is necessary to inspect whether data transfer in each part of the storage system can be performed correctly at the time of manufacturing the storage system or at the time of maintenance inspection.

  Conventionally, as a test of a printed circuit board on which a component is mounted, there are cases where only an appearance inspection is supported, an electrical connection test such as an in-circuit test is performed, and further, an operation test is incorporated into an actual device. . As a feature of each test method, in the appearance inspection, the inspection is performed with the expectation that it can be seen by some method (eg, eye, laser, X-ray, etc.), and the connection state is confirmed. For this reason, it is difficult to detect a failure such as a recent BGA (Ball Grid Array) type connection method that cannot be directly seen, but if it can be detected, it can be repaired as it is.

  In the in-circuit test method, a test pad for contacting an inspection pin called a sword pin is provided on a printed circuit board, and a function test for each component is performed to determine the quality of the printed circuit board. In this method, since a test is performed for each component, it is relatively easy to point out a defective part. However, in recent years, with the increase in the density of printed circuit boards, it has become difficult to install test pads.

  The method of performing an operation test by incorporating it in an actual apparatus can be determined whether it operates or not, but it is difficult to point out a repair point when it does not operate. Also, it is often difficult to realize all the operation patterns.

Therefore, at present, the quality of the printed circuit board is usually guaranteed by combining these three methods. In order to eliminate the need to install a test pad for the in-circuit test method, a method that employs a part having a function standardized by JTAG (Joint Test Action Group) and performs a test using the protocol is also employed. This method (standard) is adopted by the Institute of Electrical and Electronics Engineers, INC. (IEEE), and is defined and operated as an ANSI / IEEE1149.1 standard. Japanese Patent Application Laid-Open No. H10-228561 discloses a process for testing by a protocol standardized by JTAG.
JP-A-5-164826

  A specific example of a test defined and operated as a conventional ANSI / IEEE1149.1 standard will be described. In ANSI / IEEE1149.1, a circuit for testing a printed circuit board is incorporated in a component, and generally has a configuration shown in FIG. In this example, boundary scan cells 110 are individually arranged in a plurality of data input units and a plurality of data output units included in the internal logic circuit, and control of a boundary scan control circuit (TAP: Test Access Port) 111 is performed. Thus, data set to each data output unit and data input to each data input unit can be set to a register.

  FIG. 13 is a flowchart showing the flow of test processing defined as ANSI / IEEE1149.1 standard. Since the test procedure itself shown in this flowchart is not directly related to the present invention, it will not be described in detail here.

  FIG. 14 is a diagram showing an example of a printed circuit board in which the boundary scan cell shown in FIG. 12 is incorporated. Two components 113 having ANSI / IEEE1149.1 functions are arranged on the printer circuit board 112. An output boundary list cancel 114 of one component 113 and an input boundary list of the other component 113 are arranged. The cancel 115 is connected with the wiring patterns 116 to 118 of the printed circuit board.

  FIG. 15 is an example of a configuration diagram of the input side boundary scan cell. The data supplied from the preceding boundary cancel is selected by the selector, set in the internal flip-flops 201 and 202, and supplied to the subsequent boundary cancel. FIG. 16 is an example of a configuration diagram of the output side boundary scan cell. The data supplied from the preceding boundary cancel is selected by the selector, set in the internal flip-flops 203 and 204, and supplied to the subsequent boundary cancel. During the test, the sequencer circuit called TAP (Test Access Port) controls the circuits of FIGS. 15 and 16, and the value changes in synchronization with the test clock (TCK).

  FIG. 17 shows the state transition of the conventional sequencer in the circuit configuration shown in FIG. For example, in the printed circuit board shown in FIG. 14, in order to detect a defect of the wiring 116 (pattern disconnection, soldering failure of both end parts, etc.), the output side boundary scan cell 114 has a low (or low) level (or The high level (or low level), which is the opposite value, is set in the boundary scan cell 115 on the input side. This operation is performed by Shift-DR of the TAP sequencer as shown in the state of FIG. After that, by shifting to the Update-DR state, the boundary scan cell value is propagated (output) to the component terminal. Furthermore, if the state of the sequencer is shifted from Select-DR-Scan to Capture-DR, a low level (or high level) that is a signal value can be taken into the boundary scan cell on the input side. At this time, if there is a defect, the low level (or high level) cannot be taken in correctly, so that the value of the boundary scan cell does not change, and the defect can be found. Actually, the captured value of the boundary scan is shifted to TDO in Shift-DR to detect a defect. The other wirings 117 and 118 can be similarly tested at the same time. Further, by setting the signal levels of adjacent wirings to different levels, it is possible to detect a short circuit failure between the wirings.

  In this way, in this test method, each component used outputs and inputs data in synchronization with the test clock (TCK) to determine the presence / absence of a defect. It takes more than a cycle. Therefore, in this test method, if the TCK is ideally speeded up, an abnormality in an increase in delay from data output to input can be detected. However, in a system that issues a skew such that data and a clock signal instructing the timing for fetching the data are transmitted in parallel, an abnormality in the skew cannot be detected. There is no guarantee to pass the operation test.

  For this reason, even if the boundary scan test method (ANSI / IEEE1149.1) is introduced because it is easy to identify a defect, data and a clock signal instructing the timing for fetching the data are transmitted in parallel. Because of the transmission method, a defect cannot be detected, and when it is incorporated in an actual apparatus, it does not operate, and as a result, it takes time to specify the defect position.

  The present invention has been made in view of the above points, and it is possible to accurately and easily check the transmission of data and a clock signal instructing the timing for fetching the data in parallel. With the goal.

  The present invention is a case in which a storage system having a plurality of disk drive devices is inspected, and in the storage system, an inspection is performed in which data and a clock signal instructing the timing for fetching the data are transmitted in parallel. When transmitting, the transmission side outputs data and a clock signal having a pulse waveform that temporarily changes to a predetermined state at a predetermined data output timing, and the transmission side receives the data and the clock signal. The fetched data is latched at a predetermined data input timing generated in synchronization with the fetched clock signal, and it is inspected whether the data is correctly transmitted based on the latched data.

  According to the present invention, since it is possible to detect a skew defect with the same protocol as a normal boundary scan test, it is easy to specify the position of the defect.

  In this case, when the latched data is data that has temporarily changed to a predetermined state, it can be easily determined by determining that the data is correctly transmitted.

  A pulse waveform that temporarily changes to a predetermined state changes from a low level to a high level for a short time and then returns to a low level, or from a high level to a low level for a short time to a high level. By using the returning pulse waveform, a temporary waveform change can be easily detected.

  In addition, a circuit having a function of generating a pulse waveform that temporarily changes to a predetermined state is mounted in advance on the transmission side, thereby enabling easy inspection.

  In addition, the transmission side and the reception side are equipped with a boundary scan cell, and are inspections of data transmission between both boundary scan cells, so that the same test as in the case of testing according to the protocol standardized by the conventional JTAG, More accurate.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a diagram showing an example of the overall configuration of a storage system to which the inspection of this example is applied. The storage system 500 includes a plurality of protocol conversion units 510a, 510b,... 510c, a plurality of cache control units 520a, 520b,... 520c, and a management unit 540, and a management terminal 550 via the interface 546 to the management unit 540. Is connected. The protocol conversion units 510a to 510c, the cache control units 520a to 520c, and the management unit 540 are connected to each other through an interconnection network, and are configured to transmit data to each other.

  Each protocol conversion unit 510a to 510c is connected to the fiber channel switch 530 via the port 511, and is connected to a host or the like via the fiber channel. Each protocol conversion unit 510 a to 510 c includes a control processor 512, a memory 513, and a transfer control unit 514.

  Each cache control unit 520 a to 520 c includes a transfer control unit 521, a control processor 522, a memory 523, a disk cache 524, and a control memory 525, and a plurality of hard disk drive devices 527 are connected via a port 526. It is.

  The management unit 540 includes a transfer control unit 541, a control processor 542, a memory 543, a storage device 544, a control memory 545, and an interface 546.

  In the present embodiment, the transmission of the data and the clock signal instructing the timing for fetching the data between the units in the storage system 500 having the configuration shown in FIG. The inspection is to be performed. The transmission here is, for example, transmission between blocks such as transmission between a protocol conversion unit and a cache control unit, transmission between a plurality of substrates in one block, and the same substrate. It can be applied to any of transmissions among a plurality of components.

  FIG. 2 is a transmission configuration example from the component 1 to the component 2 in the present embodiment. In the output side component, at the timing (Update-DR) at which the data of the boundary scan test is output (Update-DR), 0 → 1 → 0 or 0 depending on the value of the boundary scan cell corresponding to the data signal at the speed corresponding to the data transmission speed. A circuit 105 that outputs a pulse waveform of 1 → 0 → 1 is added after the boundary scan cell 101. Further, a circuit 106 that outputs a waveform of 0 or 0 → 1 is added to the subsequent stage of the boundary scan cell 102 according to the value of the corresponding boundary scan cell. The output data of the circuit 105 and the output clock signal of the circuit 106 are output via the output buffer 108.

  The input-side component 2 adds a circuit 107 that latches the result by the transmitted data and clock and transfers the result to the boundary scan cell at the timing (Capture-DR) at which the boundary scan test data is input. To do. That is, the data input through the input buffer 109 is supplied to the circuit 107 and the output is sent to the boundary scan cell 103.

  FIG. 3 is a flowchart showing an example of an inspection process inside the storage system 500 of this example. First, an acceptance inspection is performed (step S11), the printed circuit board is assembled (step S12), an appearance inspection is performed on the printed circuit board (step S13), and an in-circuit inspection is performed (step S14). The inspection here is an inspection using the ANSI / IEEE1149.1 standard, and the specific inspection in this example described below also corresponds to the inspection here. Thereafter, an operation test is performed on the printed circuit board alone (step S15), a device as the storage system 500 is assembled (step S16), and a final device inspection (shipment inspection) is performed (step S17).

  FIG. 4 is a diagram showing a configuration example of the circuit 105 added to the output-side (transmission-side) component 1 shown in FIG. This circuit includes a synchronization circuit 601 to which a system clock is supplied, and an arithmetic circuit block 610 for obtaining a predetermined pulse change after a period synchronized by the synchronization circuit 601. The arithmetic circuit block 610 has two flip-flops 611 and 612. The output of the arithmetic circuit block 610 is sequentially set to the selectors 602, 603, and 604 and output.

  FIG. 5 is a waveform diagram showing an output example of the circuit of FIG. This waveform diagram is a waveform of the output pin when the data boundary scan cell outputs a high level, and one pulse corresponding to the system clock is output. When the boundary scan cell value corresponding to the parallel transfer clock is at the low level, the data boundary scan cell value is output as it is.

  FIG. 6 is a configuration example of the circuit 106 (FIG. 2) that controls the parallel transfer clocks. It is composed of a synchronization circuit 701 to which a system clock is supplied, two flip-flops 703 and 704 that are set after a period synchronized by the synchronization circuit 701, and a selector 705 that selects the output of the flip-flop 704. .

  FIG. 7 is a waveform of the output pin when the boundary scan cell of the parallel transfer clock outputs a high level in the circuit of FIG. When the corresponding boundary scan cell is low level, the low level is always output.

  FIG. 8 is a configuration example of the control circuit 107 (FIG. 2) added to the input side component. The flip-flop 801 sets the data input to the input pin with the clock obtained at the parallel clock input pin, selects it with the selector 802, and sends it to the boundary scan cell.

  FIG. 9 shows the waveforms of the respective parts when the boundary scan cell value of the data is low and the boundary clock cancel value of the parallel clock is high. A low pulse is generated in the data path in synchronization with the system clock, and a rising edge is generated in the clock path. This is acquired on the receiving side. The final boundary-side cancel value on the receiving side is standard ANSI / IEEE1149.1. It is the same as the value to be imported. The same applies to the case where the boundary detection cancel value of the data is high and the boundary scan cancellation value of the parallel clock is high, and the boundary detection cancel value on the receiving side is the value taken in by standard ANSI / IEEE1149.1. It will be the same. On the other hand, when the boundary clock cancellation value of the parallel clock is low, the propagating waveform matches the standard ANSI / IEEE1149.1, and in any case, the same inspection as the standard ANSI / IEEE1149.1 is performed. Test with data.

  In the case of the example of FIG. 9, it can be seen that the circuit 105 is temporarily (only for one clock period) taken in at the timing of changing from the high level to the low level.

  Next, FIG. 10 shows an example when the clock path is delayed. This waveform is a case where the value of the boundary scan cell of the data is low and the value of the boundary scan cell of the parallel clock is high. When the clock path is delayed more than expected, the additional circuit 107 on the receiving side takes in the next high level instead of the low level that is the original data, so that the boundary scan cell 103 is compared with the normal case (FIG. 9). Defectiveness can be detected by the difference in the values taken in. Similarly, when the data path is delayed, a value different from the original data is taken in, so that a defect can be detected.

  As described above, the present invention can be applied to cases other than the case where both the transmission-side component and the reception-side component are on the same printed circuit board. That is, for example, as shown in FIG. 11, a transmission-side component 301 and a reception-side component 302 are on different printed circuit boards 303 and 303, and a connector 305 is interposed between the respective printed circuit boards 303 and 303. The present invention can also be applied to the case where the third printed circuit board 304 or the cable is used to transmit the data path and the clock path.

  In addition, for example, a variable delay may be inserted into the output buffer 108 or the input buffer 109 or a path including them, and may be actively changed during a test to simulate asynchronous component variations. As a result, the operation margin can be easily confirmed.

1 is a block diagram showing a configuration example of a storage system according to an embodiment of the present invention. 1 is a schematic diagram of a circuit that performs an inspection according to an embodiment of the present invention. FIG. It is the flowchart which showed the example of the test | inspection process by one embodiment of this invention. It is a block diagram of an additional circuit example on the data output side according to an embodiment of the present invention. It is a wave form diagram by the side of the data output by one embodiment of this invention. It is a block diagram of an example of an additional circuit on the clock output side according to an embodiment of the present invention. It is a wave form diagram by the side of the clock output by one embodiment of this invention. It is a block diagram of an example of an additional circuit on the data input side according to the embodiment of the present invention. It is a wave form chart at the time of normal by one embodiment of the present invention. It is the wave form diagram which showed the mechanism of the defect (clock path delay) detection by one embodiment of this invention. It is a block diagram by other embodiment of this invention. It is a block diagram of the component which supported the conventional ANSI / IEEE1149.1. It is a state transition diagram of ANSI / IEEE1149.1. It is a block diagram of an example of the printed circuit board using ANSI / IEEE1149.1. It is a block diagram of an example of the input side boundary scan cell. It is a block diagram of an example of the output side boundary scan cell. It is a wave form diagram which shows the mechanism of the defect detection in ANSI / IEEE1149.1.

Explanation of symbols

  101 ... Boundary scan (for data output), 102 ... Boundary scan (for parallel clock output), 103 ... Boundary scan (for data input), 104 ... Boundary scan (for parallel clock input), 105 ... Data output control circuit 106 ... Parallel clock control circuit 107 ... Data input control circuit 108 ... Output buffer 109 ... Input buffer 110 ... Boundary scan cell 111 ... Boundary scan control circuit (TAP: Test Access) 112) printer circuit board, 113 ... component having ANSI / IEEE1149.1 function, 114 ... output boundary scan cancel, 115 ... input boundary scan cancel, 116-118 ... printed circuit board wiring pattern, 201-204 ... Boundary Canceled internal flip-flop, 301... Output side component having the function of the present invention, 302... Input side component having the function of the present invention, 303... Printed circuit board mounted with the component having the function of the present invention, 304 ... Relay printed circuit board or connection cable for connecting two printed circuit boards, 305 ... Connector for connecting two printed circuit boards

Claims (10)

A method for inspecting a storage system having a plurality of disk drive devices, wherein the storage system inspects data and a clock signal instructing a timing for fetching the data in parallel. In the method
On the transmission side of the transmission, at a predetermined data output timing, the data having a pulse waveform that temporarily changes to a predetermined state and the clock signal are output,
On the receiving side of the transmission, the data and the clock signal are fetched, and the fetched data is latched at a predetermined data input timing generated in synchronization with the fetched clock signal, and correctly based on the latched data. A method for inspecting a storage system, comprising inspecting whether data has been transmitted. The storage system inspection method according to claim 1,
A storage system inspection method, wherein when the latched data is data that has temporarily changed to a predetermined state, it is determined that the data is correctly transmitted. The storage system inspection method according to claim 1,
The method of testing a storage system, wherein the pulse waveform that temporarily changes to a predetermined state is a pulse waveform that changes from a low level to a high level for a short time and returns to a low level. The storage system inspection method according to claim 1,
The storage system inspection method, wherein the pulse waveform that temporarily changes to a predetermined state is a pulse waveform that changes from a high level to a low level for a short time and then returns to a high level. The storage system inspection method according to claim 1,
A storage system inspection method, wherein a circuit having a function of generating a pulse waveform that temporarily changes to a predetermined state is mounted on the transmission side in advance. The storage system inspection method according to claim 1,
An inspection method for a storage system, wherein the transmission side and the reception side include a boundary scan cell and a data transmission test is performed between the boundary scan cells. The storage system inspection method according to claim 1,
An inspection method for a storage system, which is an inspection of data transmission from a transmission side to a reception side configured on the same circuit board in the storage system. The storage system inspection method according to claim 1,
An inspection method for a storage system, which is an inspection of data transmission from a transmission side on a first circuit board in a storage system to a reception side on a second circuit board. The storage system inspection method according to claim 8,
A method for inspecting a storage system, wherein data transmission is performed between the first circuit board and the second circuit board via a third circuit board. The storage system inspection method according to claim 8,
A method for inspecting a storage system, wherein data transmission is performed via a predetermined cable between the first circuit board and the second circuit board.

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