JP2009043785A - Method of fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of fabricating semiconductor device in which crystallinity of group III-V compound semiconductor crystal containing nitrogen atoms and arsenic atoms can be made excellent. <P>SOLUTION: The method of fabricating the semiconductor device having a group III-V compound semiconductor layer containing nitrogen atoms and arsenic atoms includes: a growth step S1 of growing the group III-V compound semiconductor layer on a substrate; a first heat treatment step S2 of producing a first atmosphere containing arsenic atoms at a periphery of the group III-V compound semiconductor layer and heat-treating the group III-V compound semiconductor layer at first temperature higher than growth temperature of the growth step; and a second heat treatment step S3 of producing a second atmosphere containing no hydrogen compound or a vacuum atmosphere at the periphery of the group III-V compound semiconductor layer and heat-treating the group III-V compound semiconductor layer at second temperature lower than the first temperature. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  When forming the compound semiconductor layer on the substrate, the compound semiconductor crystal is grown on the substrate, and then heat treatment (annealing) is performed on the compound semiconductor crystal. Thereby, the crystallinity of the compound semiconductor crystal is improved, and a semiconductor layer having good optical characteristics can be obtained.

For example, Patent Document 1 describes performing annealing in a nitrogen atmosphere after the growth of a GaInNAs layer. Patent Document 2 describes that after an AlGaAs layer, a GaInNAs layer, and an AlGaAs layer are sequentially grown on a GaAs substrate, heat treatment is performed in a nitrogen gas atmosphere. Non-Patent Document 1 describes that annealing is performed in a tertiary butylarsine (TBAs) atmosphere in a furnace in which the GaInNAs crystal is grown in order to improve the crystallinity of the GaInNAs crystal.
JP 2002-118329 A JP 2002-319548 A T. Hakkarainen etal., “GaInNAs quantum well structures for 1.55 μm emission on GaAs by atomic pressure metalorganic vapor phase epitaxy”, Journal of CrystalGrowth 234 pp631-636 (2002)

  Conventionally, when a heat treatment is performed on a compound semiconductor crystal, it has been generally performed only once in a certain atmosphere as described in the above-mentioned documents. However, the present inventor has found that the crystallinity of a group III-V compound semiconductor crystal containing nitrogen atoms (N) and arsenic atoms (As) cannot be sufficiently improved by such a conventional heat treatment method.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of improving the crystallinity of a III-V compound semiconductor crystal containing nitrogen atoms and arsenic atoms. To do.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a III-V group compound semiconductor layer containing nitrogen atoms and arsenic atoms as group V elements. A growth step of growing a group V compound semiconductor layer on the substrate, and a first atmosphere containing arsenic atoms around the group III-V compound semiconductor layer, and at a first temperature higher than the growth temperature in the growth step III- A first heat treatment step for heat-treating the group V compound semiconductor layer; and a second temperature lower than the first temperature, wherein the periphery of the III-V compound semiconductor layer is a second atmosphere or a vacuum atmosphere not containing a hydrogen compound. And a second heat treatment step for heat treating the III-V compound semiconductor layer.

  The present inventor has found that there are the following two patterns in the disappearance process of crystal defects caused by heat treatment of a group III-V compound semiconductor crystal containing nitrogen atoms and arsenic atoms. That is, (1) general point defects such as interstitial atoms diffused by thermal energy and settled in normal lattice sites, or vacancy defects diffused by thermal energy and desorbed from III-V compound semiconductor crystals. And (2) the disappearance process of hydrogen-induced defects in which the bonds between hydrogen atoms and nitrogen atoms that induce defects are dissociated by thermal energy and the hydrogen atoms are desorbed from the III-V compound semiconductor crystal, It is two. Therefore, in the above-described method for manufacturing a semiconductor device, as a first heat treatment step, heat treatment at a relatively high temperature is performed in a first atmosphere containing arsenic atoms. By performing the heat treatment at a relatively high temperature in this way, the above-described annihilation process (1) can be caused and general point defects can be reduced. Further, by performing the heat treatment in the first atmosphere containing arsenic atoms, desorption of arsenic atoms accompanying high-temperature heat treatment can be suppressed.

  However, when this first atmosphere further contains active hydrogen, desorption of hydrogen atoms as in the above annihilation process (2) cannot be expected. Therefore, in the above-described method for manufacturing a semiconductor device, as a second heat treatment step, heat treatment at a relatively low temperature is performed in a second atmosphere or a vacuum atmosphere that does not contain a hydrogen compound. By performing the heat treatment in an atmosphere that does not contain a hydrogen compound or in a vacuum atmosphere in this manner, the above-described annihilation process (2) can be caused to reduce hydrogen-induced defects. Moreover, desorption of arsenic atoms can be suppressed by performing heat treatment at a relatively low temperature.

  As described above, according to the method for manufacturing a semiconductor device described above, the two defect annihilation processes described above can be sufficiently generated, so that the crystallinity of the III-V group compound semiconductor crystal containing nitrogen atoms and arsenic atoms can be improved. Compared with the conventional heat treatment method, it can be made extremely good.

In addition, in the semiconductor device manufacturing method, the first atmosphere is obtained by supplying at least one of tertiarybutylarsine and arsine around the III-V compound semiconductor layer in the first heat treatment step. May be a feature. Thus, by using tertiary butylarsine (TBAs) and arsine (AsH ₃ ), which are often used for the growth of III-V compound semiconductors containing arsenic (As), the first atmosphere containing As can be easily formed. Can be realized.

  The method for manufacturing a semiconductor device may be characterized in that the second atmosphere is an atmosphere made of at least one kind of gas among hydrogen gas, nitrogen gas, and inert gas. By forming the second atmosphere with a stable gas that does not decompose even at a high temperature, such as hydrogen gas, nitrogen gas, and inert gas, the second heat treatment step can be suitably performed. In addition, the inert gas here refers to the gas which consists of noble gas elements, such as argon.

  Further, the method for manufacturing a semiconductor device may be characterized in that when the temperature is lowered after the heat treatment in the first heat treatment step, the temperature lowering process is performed in an atmosphere containing no hydrogen compound. When a hydrogen compound is contained in the atmosphere during the temperature lowering treatment, active hydrogen separated from the hydrogen compound is mixed into the compound semiconductor crystal, and hydrogen-induced defects increase. Therefore, an increase in hydrogen-induced defects can be suppressed by performing the temperature lowering process in an atmosphere containing no hydrogen compound.

  The semiconductor device manufacturing method may be characterized in that the first heat treatment step is performed in a growth furnace subsequent to the growth step, and the second heat treatment step is performed in a furnace different from the growth furnace. Thereby, each of the first atmosphere in the first heat treatment step and the second atmosphere in the second heat treatment step can be easily realized.

  According to the semiconductor device manufacturing method of the present invention, the crystallinity of the nitrogen atom and the III-V group compound semiconductor crystal containing the nitrogen atom can be improved.

  Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(Embodiment)
FIG. 1 is a flowchart showing an embodiment of a method for manufacturing a semiconductor device according to the present invention. This manufacturing method is a method of manufacturing a semiconductor device having a III-V group compound semiconductor layer containing nitrogen atoms (N) and arsenic atoms (As). As shown in FIG. 1, the manufacturing method according to the present embodiment includes a growth step S1, a first heat treatment step S2, a second heat treatment step S3, and a post-step S4 for manufacturing a semiconductor device. In the growth step S1, for example, a compound semiconductor layer made of a III-V group compound semiconductor crystal such as GaInNAs is grown on the substrate. In the first heat treatment step S2, the periphery of the compound semiconductor layer grown in the growth step S1 is set to an atmosphere containing arsenic atoms (first atmosphere), and a temperature higher than the growth temperature of the compound semiconductor layer in the growth step S1 (first step). The compound semiconductor layer is heat-treated at a temperature of 1). In the second heat treatment step S3, the periphery of the compound semiconductor layer is made an atmosphere not containing a hydrogen compound (second atmosphere) or a vacuum atmosphere, and a temperature lower than the heat treatment temperature (first temperature) in the first heat treatment step S2 ( The compound semiconductor layer is heat-treated at a second temperature. Hereinafter, these steps will be described in detail.

  FIG. 2 is a side sectional view showing a wafer product 10 having a single quantum well layer as an example of a substrate product produced by the growth step S1. Referring to FIG. 2, in the wafer product 10, an n-type buffer layer 12, an n-type cladding layer 13, a lower barrier layer / SCH layer 14, a well layer 15, an upper barrier layer / SCH layer 16, p A mold cladding layer 17 and a p-type contact layer 18 are sequentially stacked.

The substrate 11 is a wafer made of an n-type (first conductivity type) III-V group compound semiconductor, and is made of, for example, n-type GaAs. The surface orientation of the substrate 11 is preferably (100), more preferably an off angle of about 2 °. The n-type impurity concentration of the substrate 11 is, for example, 1 × 10 ¹⁸ [cm ⁻³ ]. The n-type buffer layer 12 is a layer made of an n-type III-V group compound semiconductor grown on the main surface 11a of the substrate 11, and has, for example, the same composition (n-type GaAs) as the substrate 11. Yes. A suitable layer thickness of the n-type buffer layer 12 is, for example, 0.2 [μm], and a suitable n-type impurity concentration of the n-type buffer layer 12 is, for example, 2 × 10 ¹⁸ [cm ⁻³ ].

The n-type cladding layer 13 is a layer made of an n-type III-V group compound semiconductor grown on the n-type buffer layer 12, and is made of, for example, AlGaAs. A suitable layer thickness of the n-type cladding layer 13 is, for example, 1.5 [μm], and a suitable n-type impurity concentration of the n-type cladding layer 13 is, for example, 7 × 10 ¹⁷ [cm ⁻³ ]. The lower barrier layer / SCH layer 14 is a layer made of an undoped III-V group compound semiconductor grown on the n-type cladding layer 13, and is made of, for example, GaAs. A suitable layer thickness of the lower barrier layer / SCH layer 14 is, for example, 0.14 [μm].

  The well layer 15 is a layer (compound semiconductor layer in the claims) made of an undoped III-V compound semiconductor grown on the lower barrier / SCH layer 14 and contains nitrogen atoms and arsenic atoms. As an example, the well layer 15 is made of GaInNAs crystal. The thickness of the well layer 15 is, for example, 7 [nm].

The upper barrier / SCH layer 16 is a layer made of an undoped III-V compound semiconductor grown on the well layer 15 and is made of, for example, GaAs. A suitable layer thickness of the upper barrier layer / SCH layer 16 is, for example, 0.14 [μm]. The p-type cladding layer 17 is a layer made of a p-type III-V group compound semiconductor grown on the upper barrier layer / SCH layer 16, and is made of, for example, AlGaAs. A suitable layer thickness of the p-type cladding layer 17 is, for example, 1.5 [μm], and a suitable p-type impurity concentration of the p-type cladding layer 17 is, for example, 1 × 10 ¹⁸ [cm ⁻³ ]. The p-type contact layer 18 is a layer made of a p-type III-V group compound semiconductor grown on the p-type cladding layer 17, and is made of, for example, GaAs. A suitable layer thickness of the p-type contact layer 18 is, for example, 0.2 [μm], and a suitable p-type impurity concentration of the p-type contact layer 18 is, for example, 7 × 10 ¹⁸ [cm ⁻³ ].

In the growth step S1, the n-type buffer layer 12, the n-type cladding layer 13, the lower barrier layer / SCH layer 14, the well layer 15, the upper barrier layer / SCH layer 16, the p-type cladding layer 17, and the p-type contact layer described above. 18 is grown by, for example, metal-organic vapor phase epitaxy (MOVPE). At this time, as source gas corresponding to each element of Al, Ga, In, N, and As, for example, trimethylaluminum (TMAl), triethylgallium (TEGa), trimethylindium (TMIn), dimethylhydrazine (DMHy), tarsha may supplying-butyl arsine (TBAs) or arsine (AsH _3). Further, for example, tetraethylsilane (TeESi) may be supplied as a source gas of Si that is an n-type dopant, and diethylzinc (DEZn) may be supplied as a source gas of Zn that is a p-type dopant.

  Next, the first heat treatment step S2 and the second heat treatment step S3 will be described. In the first heat treatment step S2, the periphery of the wafer product 10 produced in the growth step S1 is set to an atmosphere (first atmosphere) containing arsenic atoms (As), and the temperature (first temperature) higher than the growth temperature in the growth step S1. The semiconductor layers 12 to 18 are heat-treated at a temperature of 1). In the second heat treatment step S3, the periphery of the wafer product 10 is set to an atmosphere not containing a hydrogen compound (second atmosphere) or a vacuum atmosphere, and a temperature lower than the treatment temperature in the first heat treatment step S2 (second step). The semiconductor layers 12 to 18 (particularly, the well layer 15) are heat-treated at a temperature.

When realizing the first atmosphere in the first heat treatment step S2, it is preferable to continue supplying the arsenic source gas even during the heat treatment. For example, the wafer product 10 may be heat-treated while supplying tertiary butylarsine (TBAs) or arsine (AsH ₃ ), which is an As source gas, into the furnace. Therefore, the first heat treatment step S2 can be continued in the same furnace as the growth furnace in which the semiconductor layers 12 to 18 are grown in the growth step S1 (so-called in-situ annealing).

Further, when realizing the second atmosphere in the second heat treatment step S3, for example, at least of inert gas such as argon gas (Ar), nitrogen gas (N ₂ ), and hydrogen gas (H ₂ ) An atmosphere composed of one kind of gas is preferable. In the second heat treatment step S3, the wafer product 10 is sandwiched between III-V compound substrates (eg, GaAs substrates) in order to prevent the group V atoms from detaching from the semiconductor layers 12 to 18 as much as possible. It is preferable to perform the heat treatment in the state.

  Here, FIG. 3 is a graph showing an example of the transition of the treatment temperature and the supply gas in the growth step S1, the first heat treatment step S2, and the second heat treatment step S3.

In the growth step S1, after the substrate 11 is placed in the MOVPE growth furnace, an arsenic source gas such as TBAs or AsH ₃ is supplied into the growth furnace, and the temperature in the growth furnace is set to a predetermined growth temperature as shown in FIG. The temperature is raised to (510 ° C. in the figure) (section A in the figure). When a predetermined growth temperature is reached, the semiconductor layer (n-type buffer layer 12, n-type buffer layer 12, n-type buffer layer 12) is supplied by further supplying a group III source gas such as TEGa, TMAl, TMIn and a group V source gas such as DMHy while maintaining the temperature The cladding layer 13, the lower barrier layer / SCH layer 14, the well layer 15, the upper barrier layer / SCH layer 16, the p-type cladding layer 17, and the p-type contact layer 18) are grown (section B). For example, each semiconductor layer is grown by the following procedure.
(1) TBAs and TEGa are supplied to grow a GaAs layer as the n-type buffer layer 12.
(2) TBAs, TEGa, and TMAl are supplied to grow an AlGaAs layer as the n-type cladding layer 13.
(3) TBAs and TEGa are supplied to grow a GaAs layer as the lower barrier / SCH layer 14.
(4) TBAs, TEGa, TMIn, and DMHy are supplied to grow a GaInNAs layer as the well layer 15.
(5) TBAs and TEGa are supplied to grow a GaAs layer as the upper barrier layer / SCH layer 16.
(6) Supply TBAs, TEGa, and TMAl to grow an AlGaAs layer as the p-type cladding layer 17.
(7) Supply TBAs and TEGa to grow a GaAs layer as the p-type contact layer 18.
Thus, the wafer product 10 shown in FIG. 2 is formed. The growth temperature of each semiconductor layer is preferably 450 ° C. or higher and 700 ° C. or lower, and a typical growth temperature is 510 ° C.

  Subsequently, in a state where the wafer product 10 is installed in the MOVPE growth furnace, the process proceeds to the first heat treatment step S2. In the first heat treatment step S2, the atmosphere in the growth furnace is the first atmosphere described above. Then, the temperature in the growth furnace is further raised to a predetermined first temperature (650 ° C. in the figure) under the first atmosphere (section C). When the predetermined first temperature is reached, the semiconductor layer of the wafer product 10 is heat-treated for a predetermined time while maintaining the temperature (section D). The predetermined first temperature is preferably 575 ° C. or more and 700 ° C. or less, and most preferably 650 ° C.

When the heat treatment for a predetermined time is completed in the first heat treatment step S2, the temperature in the growth furnace is lowered (section E). At this time, it is preferable that supply of hydrogen compounds such as TBAs and AsH ₃ is stopped.

  Subsequently, the wafer product 10 is transferred to a furnace (hereinafter referred to as a heat treatment furnace) different from the MOVPE growth furnace, and a second heat treatment step S3 is performed. In the second heat treatment step S3, the atmosphere in the heat treatment furnace is the second atmosphere described above. Then, the temperature in the heat treatment furnace is raised to a predetermined second temperature (500 ° C. in the drawing) in the second atmosphere (section F). When the predetermined second temperature is reached, the semiconductor layer (especially the well layer 15) of the wafer product 10 is heat-treated for a predetermined time while maintaining the temperature (section G). The predetermined second temperature is preferably 500 ° C. or higher and lower than 650 ° C., and 500 ° C. is most preferable.

  When the heat treatment for a predetermined time is completed in the second heat treatment step S3, the temperature in the heat treatment furnace is lowered (section H). It should be noted that the second atmosphere described above may be maintained during the temperature lowering process.

  After the above steps (growth step S1, first heat treatment step S2, and second heat treatment step S3), a semiconductor device is manufactured by processing the wafer product 10 (step S4 shown in FIG. 1). As an example of the semiconductor device, a manufacturing method of the gain guide type laser element 30 shown in FIG. 4 will be described. First, a stripe-like resist pattern is formed on the p-type contact layer 18 shown in FIG. 2 by a normal photolithography technique. To do. Next, by removing the portion of the p-type contact layer 18 that is not covered with the resist pattern by etching, the p-type contact layer 18 is formed in a stripe shape as shown in FIG. Then, after an insulating film 32 such as SiN is formed on the entire surface of the wafer product 10 by plasma CVD, only the insulating film 32 on the p-type contact layer 18 is removed. Subsequently, a metal anode electrode 34 is formed on the p-type contact layer 18, and a metal cathode electrode 36 is formed on the back surface of the substrate 11. Finally, the gain product laser element 30 shown in FIG. 4 is completed by dividing the wafer product into chips.

  The effects of the semiconductor device fabrication method according to the present embodiment will be explained. As already described in the section [Means for Solving the Problems], there are the following two patterns in the annihilation process of crystal defects caused by heat treatment of a group III-V compound semiconductor crystal containing nitrogen atoms and arsenic atoms. . That is, (1) general point defects such as interstitial atoms diffused by thermal energy and settled in normal lattice sites, or vacancy defects diffused by thermal energy and desorbed from III-V compound semiconductor crystals. And (2) bonds between hydrogen atoms and nitrogen atoms that induce defects (hereinafter referred to as NH bonds) are dissociated by thermal energy, and the hydrogen atoms are desorbed from the group III-V compound semiconductor crystal. Two processes are the disappearance process of hydrogen-induced defects. The N—H bond (2) is deposited in the crystal without breaking the N—H bond of the source gas such as DMHy used when growing a III-V compound semiconductor crystal containing a nitrogen atom (N). This is presumed to be caused by

  In the semiconductor device fabrication method according to the present embodiment, after each semiconductor layer is grown on the substrate, the first heat treatment step S2 is performed at a relatively high temperature (first temperature) in a first atmosphere containing As. The heat treatment is performed. As described above, by performing the heat treatment at a relatively high temperature in the first heat treatment step S2, the annihilation process (1) is caused, and general point defects contained in each semiconductor layer such as the GaInNAs well layer 15 can be reduced. . Furthermore, by performing the heat treatment in the first atmosphere containing As, as shown in FIG. 5A, it is possible to suppress As from being desorbed from the GaInNAs well layer 15 and the like due to the high-temperature heat treatment.

このＴＢＡｓが熱分解すると、Ａｓ、Ｈ（活性水素）、Ｃ、およびＣＨ_３が生成する。したがって、図５（ａ）に示すように炉内に水素分圧も付加されるので、上記消滅過程（二）によってＧａＩｎＮＡｓ井戸層１５から水素原子が脱離することは期待できない。 In order to realize the first atmosphere, for example, a source gas of arsenic atoms (TBAs, AsH _3, etc.) may be supplied. In this case, active hydrogen (hydrogen ions or the like) separated from the source gas is further included in the first atmosphere. For example, TBAs are represented by the following chemical formula:

When these TBAs are thermally decomposed, As, H (active hydrogen), C, and CH ₃ are generated. Therefore, as shown in FIG. 5 (a), a hydrogen partial pressure is also applied to the furnace, so that it cannot be expected that hydrogen atoms are desorbed from the GaInNAs well layer 15 by the annihilation process (2).

Therefore, in the method for fabricating the semiconductor device according to the present embodiment, as the second heat treatment step S3, the second heat treatment step S3 is performed at a relatively low temperature (second phase) in a second atmosphere or a vacuum atmosphere that does not contain a hydrogen compound such as TBAs and AsH ₃ . Temperature). As described above, by performing the heat treatment in an atmosphere not containing a hydrogen compound or in a vacuum atmosphere, the annihilation process (2) is caused in the GaInNAs well layer 15 as shown in FIG. Can be reduced. In addition, desorption of As can be suppressed by performing heat treatment at a relatively low temperature.

  As described above, according to the method for fabricating the semiconductor device according to the present embodiment, two defect annihilation processes can be sufficiently generated. Therefore, a group III-V compound semiconductor crystal containing nitrogen atoms and arsenic atoms (for example, The crystallinity of the GaInNAs well layer 15) can be made very good compared with the conventional heat treatment method.

Further, as in the present embodiment, when As is included as a group V atom other than nitrogen in the composition of each semiconductor layer of the wafer product 10, the wafer product is subjected to the first heat treatment step S2. A first atmosphere may be obtained by supplying at least one of TBAs and AsH ₃ around 10. The first atmosphere containing As can be easily realized by using TBAs and AsH ₃ that are often used for the growth of compound semiconductors containing As. In addition to TBAs and AsH ₃ , arsenic raw materials include diethyl arsenide hydrogen ((C ₂ H ₅ ) ₂ AsH), ethylarsine ((C ₂ H ₅ ) AsH ₂ ), triethyl arsenic ((C ₂ H ₅ ) Organic arsenic source gases such as ₃ As), trimethyl arsenic ((CH ₃ ) ₃ As), and trisdimethylamino arsenic ((C ₆ H ₁₈ ) N ₃ As) can be used.

  Further, as in the present embodiment, the second atmosphere in the second heat treatment step S3 may be an atmosphere composed of at least one kind of gas such as an inert gas such as argon, hydrogen gas, and nitrogen gas. Since these gases have a stable property that does not decompose even at high temperatures, the second heat treatment step S3 can be suitably performed.

Further, as in the present embodiment, when the temperature is lowered after finishing the heat treatment in the first heat treatment step S2, the temperature lowering treatment may be performed in an atmosphere that does not contain a hydrogen compound such as TBAs or AsH ₃ . When a hydrogen compound is contained in the atmosphere during the temperature lowering process, as shown in FIG. 6, active hydrogen separated from the hydrogen compound is mixed into the group III-V compound semiconductor crystal (for example, GaInNAs well layer 15), Hydrogen-induced defects increase. Therefore, an increase in hydrogen-induced defects can be suppressed by performing the temperature lowering process in the first heat treatment step S2 in an atmosphere not containing a hydrogen compound.

  Further, as in the present embodiment, the treatment temperature (first temperature) in the first heat treatment step S2 is 650 [° C.] or higher, and the treatment temperature (second temperature) in the second heat treatment step S3 is 650. It is good that it is less than [° C.]. By setting the first temperature to 650 [° C.] or higher, the above-described defect disappearance process (1) can be suitably generated. Further, by setting the second temperature to less than 650 [° C.], the defect disappearance process (2) can be suitably generated while suppressing As desorption.

  Further, as in the present embodiment, the first heat treatment step S2 is performed in the growth furnace subsequent to the growth step S1, and the second heat treatment step S3 is performed in a furnace (heat treatment furnace) different from the growth furnace. Good. Thereby, it is possible to easily realize each of the first atmosphere in the first heat treatment step S2 and the second atmosphere in the second heat treatment step S3.

  The inventor of the present invention actually confirmed the above-described effects by the first heat treatment step S2 and the second heat treatment step S3 by actually fabricating a semiconductor device. The results will be described below.

<First embodiment>
As shown in FIG. 7, an undoped GaAs buffer layer 52, an undoped GaInNAs well layer 53, and an undoped GaAs buffer layer 54 are sequentially grown on an n-type GaAs wafer 51 by a low pressure MOVPE method to obtain a GaInNAs / GaAs single quantum well structure. Two wafer products 50 having the above were produced (growth process). In this wafer product 50, the thickness of the well layer 53 was 7 [nm], and the composition was Ga _0.66 In _0.34 N _0.01 As _0.99 . With this composition, the photoluminescence (PL) wavelength of the well layer 53 is 1250 [nm]. TEGa, TMIn, DMHy, and TBAs were used as Ga, In, N, and As source gases for the well layer 53, respectively. As the wafer 51, a Si-doped GaAs wafer having a plane orientation of (100) and an off angle of 2 ° was used. The growth temperature of the well layer 53 was 510 ° C., the growth rate of the well layer 53 was 0.9 [μm / h], and the flow rates and flow ratios of TEGa, TMIn, DMHy, and TBAs were as shown in Table 1 below. . The growth pressure of the well layer 53 was 10.1 [kPa] (76 [Torr]).

  One of the two wafer products 50 thus produced was subjected to heat treatment in the MOVPE growth furnace following the growth of each semiconductor layer (buffer layer 52, well layer 53, buffer layer 54) ( First heat treatment step). As heat treatment conditions at this time, the heat treatment temperature (first temperature) was 650 ° C. and the heat treatment time was 10 minutes so that the PL strength of the well layer 53 was maximized. Further, in order to prevent As from being detached from the surface of the wafer product 50 during the heat treatment, the heat treatment was performed in a TBAs atmosphere (first atmosphere). After the heat treatment, the temperature was lowered in a hydrogen atmosphere without flowing the TBAs raw material in order to prevent mixing of hydrogen.

  Thereafter, the wafer product 50 was taken out of the growth furnace and divided into four, and heat treatment was performed using a heat treatment furnace different from the growth furnace (second heat treatment step). At that time, in order to prevent As from detaching from the surface of the wafer product 50 as much as possible, heat treatment was performed with the wafer product 50 sandwiched between two GaAs substrates. Further, the periphery of the wafer product 50 is a nitrogen gas atmosphere (second atmosphere), and the heat treatment temperatures (second temperatures) of the wafer product 50 divided into four parts are 500 ° C., 550 ° C., 600 ° C., and 650 ° C., respectively. It was. The heat treatment time was 15 seconds each.

  The remaining one of the two wafer products 50 produced in the growth process is taken out of the growth furnace after the growth of each semiconductor layer (buffer layer 52, well layer 53, buffer layer 54), and is separate from the growth furnace. The heat treatment was performed only in the heat treatment furnace. At that time, similarly to the above-described second heat treatment step, the wafer product 50 was divided into four and subjected to heat treatment. Further, heat treatment was performed with the wafer product 50 sandwiched between two GaAs substrates. The periphery of the wafer product 50 was a nitrogen gas atmosphere, and the heat treatment temperatures of the four divided wafer products 50 were 500 ° C., 550 ° C., 600 ° C., and 650 ° C., respectively. The heat treatment time was 15 seconds each.

  After going through the above steps, the optical properties of each wafer product 50 were evaluated by room temperature PL measurement. FIG. 8 is a graph showing the correlation between the PL intensity and the heat treatment temperature in each heat treatment method. In FIG. 8, a graph G1 shows the characteristics of the wafer product 50 that has undergone the first and second heat treatment steps, and a graph G2 shows the characteristics of the wafer product 50 that has been heat-treated only in the heat treatment furnace. In FIG. 8, the relative value with respect to the reference intensity is shown as the PL intensity. For reference, FIG. 8 also shows the case (graph G3) in which only the heat treatment in the TBAs atmosphere is performed subsequent to the growth of each semiconductor layer (buffer layer 52, well layer 53, buffer layer 54). Hereinafter, each heat processing method is evaluated based on each graph G1-G3.

(1) When only heat treatment is performed in a TBAs atmosphere (graph G3)
When only heat treatment is performed in a TBAs atmosphere, it is possible to raise the temperature to a relatively high temperature while suppressing the formation of defects due to As desorption. The point defect can be eliminated. Thereby, the luminous efficiency in the GaInNAs crystal is increased, and the optical characteristics (PL intensity) are improved. The optimum temperature is 650 ° C. If the temperature is further increased, the interdiffusion of atoms at the quantum well interface becomes remarkable, the crystal structure is disturbed, crystal defects increase, and the optical characteristics (PL intensity) deteriorate rapidly.

  However, when heat treatment is performed in a TBAs atmosphere, the TBAs are thermally decomposed during the treatment to generate active hydrogen. Therefore, the hydrogen partial pressure in the atmosphere is increased, and the hydrogen atoms in the GaInNAs crystal are suppressed from leaving the crystal. Therefore, the effect of reducing hydrogen-induced defects cannot be expected with heat treatment in a TBAs atmosphere.

(2) When only heat treatment is performed in a nitrogen gas atmosphere (graph G2)
When only the heat treatment is performed in a nitrogen gas atmosphere, the hydrogen partial pressure is low in the nitrogen gas atmosphere, so that hydrogen atoms are easily desorbed from the GaInNAs crystal. It is considered that a hydrogen atom exists as an N—H bond in the GaInNAs crystal, and the hydrogen atom is desorbed from the GaInNAs crystal when this N—H bond is broken. The temperature at which the N—H bond can be dissociated is 500 ° C. or higher. Moreover, a hydrogen atom couple | bonds with a nitrogen atom, and forms a crystal defect. Therefore, the optical characteristics of the GaInNAs crystal can be improved by desorbing hydrogen atoms at a temperature of 500 ° C. or higher.

  Referring to the graph G2 in FIG. 8, the PL intensity increases as the heat treatment temperature increases from 500 ° C., which is due to the effect that hydrogen atoms are eliminated and hydrogen-induced defects are reduced, and the point defect disappearance effect due to heat. It is. However, in the graph G2, the PL intensity becomes maximum at a heat treatment temperature of 600 ° C., and the optical characteristics deteriorate at higher temperatures. This means that a new defect is formed by desorption of As from the GaAs crystal by a high-temperature heat treatment, and it is difficult to completely eliminate the point defect only by performing the heat treatment in a nitrogen gas atmosphere.

(3) When going through the first and second heat treatment steps (graph G1)
In the heat treatment in the TBAs atmosphere (first heat treatment step), by raising the temperature around the wafer product 50 to 650 ° C., point defects such as interstitial atoms and vacancies acting as non-radiative recombination centers Can be extinguished. Then, by performing heat treatment (second heat treatment step) at 500 ° C. or higher in a nitrogen atmosphere, hydrogen atoms can be desorbed from the GaInNAs crystal. By these steps, both point defects and hydrogen-induced defects can be efficiently removed. In particular, when the processing temperature (second temperature) in the second heat treatment step is less than 600 ° C., the PL intensity is dramatically increased. To improve. When the second temperature is higher than 600 ° C., it is considered that the PL intensity decreases because new crystal defects are formed due to thermal overload. Therefore, in the second heat treatment step, it is desirable that the heat treatment temperature be 500 ° C. or higher and as low as possible.

  That is, according to the present embodiment, the crystallinity of the III-V group compound semiconductor crystal containing N and As is extremely improved by performing the first and second heat treatment steps to sufficiently generate two defect disappearance processes. It turns out that it can do well.

<Second Embodiment>
Next, two wafer products 10 having the structure shown in FIG. 2 were produced by a reduced pressure MOVPE method (growth process). In this wafer product 10, the thickness of the well layer 15 was set to 7 [nm], and the composition thereof was Ga _0.66 In _0.34 N _0.01 As _0.99 . The barrier / SCH layers 14 and 16 are made of GaAs, and the layer thickness is 140 [nm]. The n-type cladding layer 13 and the p-type cladding layer 17 were formed of AlGaAs with an Al composition of 30%, and were doped with Si and Zn, respectively. The layer thicknesses of the cladding layers 13 and 17 were 1.5 [μm]. The p-type contact layer 18 was formed of GaAs and its thickness was 0.2 [μm]. TEGa, TMIn, DMHy, and TBAs were used as source gases for Ga, In, N, and As, respectively, and TeESi, DEZn were used as source gases for n-type and p-type dopants (Si, Zn), respectively. As the substrate 11, a Si-doped GaAs wafer having a plane orientation of (100) and an off angle of 2 ° was used. The growth temperature of the well layer 53 was set to 510 ° C., the growth rate of the well layer 53 was set to 0.9 [μm / h], and the flow rates and flow ratios of TEGa, TMIn, DMHy, and TBAs were as shown in Table 1 above. . The growth pressure of the well layer 53 was 10.1 [kPa] (76 [Torr]).

  The two wafer products 10 thus produced were subjected to heat treatment in the MOVPE growth furnace following the growth of each semiconductor layer (first heat treatment step). The heat treatment conditions at this time were a heat treatment temperature (first temperature) of 650 ° C. and a heat treatment time of 10 minutes. Further, in order to prevent As from being detached from the surface of the wafer product 10 during the heat treatment, the heat treatment was performed in a TBAs atmosphere (first atmosphere). After the heat treatment, the temperature was lowered in a hydrogen atmosphere without flowing the TBAs raw material in order to prevent mixing of hydrogen.

  Subsequently, one of the two wafer products 10 was subjected to heat treatment using a heat treatment furnace different from the growth furnace (second heat treatment step). At that time, in order to prevent As from detaching from the surface of the wafer product 10 as much as possible, heat treatment was performed in a state where the wafer product 10 was sandwiched between two GaAs substrates. Further, the wafer product 10 was surrounded by a nitrogen gas atmosphere (second atmosphere), the heat treatment temperature (second temperature) was 500 ° C., and the heat treatment was performed for 15 seconds.

  Thereafter, the two wafer products 10 were processed to produce the gain guide type laser device 30 shown in FIG. First, a resist pattern was formed on the p-type contact layer 18 by photolithography, and the contact layer 18 was processed into a stripe shape by etching. At this time, the stripe width of the contact layer 18 was set to 5 [μm]. Then, a SiN insulating film 32 was formed on the entire surface of the wafer by plasma CVD, and the SiN insulating film 32 on the contact layer 18 was removed by photolithography and hydrofluoric acid etching. Thereafter, an anode electrode is formed on the contact layer 18 and a cathode electrode is formed on the back surface of the substrate 11, and then the wafer product is cleaved into a bar shape having a width of 300 [μm] (ie, resonator length). The laser characteristics were evaluated.

FIG. 9 shows the current-light output characteristics of the gain guide type laser device 30 manufactured in this way. In FIG. 9, graph G4 shows current-light output characteristics when both the first and second heat treatment steps are performed, and graph G5 shows current-light when only the first heat treatment step is performed. Output characteristics are shown. As can be seen from FIG. 9, the threshold current Ith ₁ of the laser element subjected to both the first and second heat treatment steps is lower than the threshold current Ith ₂ of the laser element subjected to only the first heat treatment step. became. In addition, the slope efficiency of the laser element subjected to both the first and second heat treatment steps was higher than the slope efficiency of the laser element subjected to only the first heat treatment step. From these results, the crystallinity of the III-V group compound semiconductor crystal containing N and As can be made extremely good by performing the first and second heat treatment steps to sufficiently generate two defect disappearance processes. Indicated.

  The method for manufacturing a semiconductor device according to the present invention is not limited to the above-described embodiments and modifications, and various other modifications are possible. For example, the semiconductor device manufactured by the manufacturing method of the present invention is not limited to the gain guide type laser element shown in FIG. 4, but a semiconductor optical amplifier, a semiconductor optical modulator, a photodiode, a solar cell, a sensor, etc. It can be applied to all semiconductor devices using III-V compound semiconductor crystals containing nitrogen atoms and arsenic atoms.

FIG. 1 is a flowchart showing an embodiment of a method for manufacturing a semiconductor device according to the present invention. FIG. 2 is a side sectional view showing a wafer product having a single quantum well layer as an example of a substrate product produced by a growth process. FIG. 3 is a graph showing an example of the transition of the treatment temperature and the supply gas in the growth step, the first heat treatment step, and the second heat treatment step. FIG. 4 is a side sectional view showing a configuration of a gain guide type laser element as an example of a semiconductor device manufactured from a substrate product. FIG. 5A shows a state in which the arsenic atmosphere suppresses arsenic atoms from desorbing from the GaInNAs well layer or the like due to high-temperature heat treatment. FIG. 5B shows how the hydrogen-induced defects disappear in the GaInNAs well layer. FIG. 6 shows a state where active hydrogen separated from a hydrogen compound is mixed in the GaInNAs well layer and hydrogen-induced defects increase when a hydrogen compound is contained in the atmosphere during the temperature lowering process in the first heat treatment step. Show. FIG. 7 is a side sectional view showing the structure of a wafer product having a GaInNAs / GaAs single quantum well structure manufactured in the first embodiment. FIG. 8 is a graph showing the correlation between the PL intensity of the wafer product manufactured in the first embodiment and the heat treatment temperature. FIG. 9 is a graph showing the current-light output characteristics of the gain guide type laser device fabricated in the second embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,50 ... Wafer product, 11 ... Substrate, 12 ... N-type buffer layer, 13 ... N-type cladding layer, 14 ... Lower barrier layer / SCH layer, 15, 53 ... Well layer, 16 ... Upper barrier layer / SCH layer 17 ... p-type cladding layer, 18 ... p-type contact layer, 30 ... gain guide type laser element, 32 ... insulating film, 34 ... anode electrode, 36 ... cathode electrode, 51 ... wafer, 52, 54 ... buffer layer.

Claims (5)

A method for producing a semiconductor device having a III-V compound semiconductor layer containing a nitrogen atom and an arsenic atom as a group V element,
A growth step of growing the III-V compound semiconductor layer on a substrate;
A first atmosphere containing the arsenic atoms is formed around the III-V compound semiconductor layer, and the III-V compound semiconductor layer is heat-treated at a first temperature higher than a growth temperature in the growth step. A heat treatment step;
A second atmosphere or a vacuum atmosphere not containing a hydrogen compound is formed around the III-V group compound semiconductor layer, and the III-V group compound semiconductor layer is heat-treated at a second temperature lower than the first temperature. A method for manufacturing a semiconductor device, comprising: a heat treatment step.   In the first heat treatment step, at least one of tertiary butyl arsine and arsine is supplied to the periphery of the III-V compound semiconductor layer to form the first atmosphere. Item 2. A method for manufacturing a semiconductor device according to Item 1.   3. The method for manufacturing a semiconductor device according to claim 1, wherein the second atmosphere is an atmosphere made of at least one kind of gas among hydrogen gas, nitrogen gas, and inert gas. 4.   4. The semiconductor device according to claim 1, wherein when the temperature is lowered after finishing the heat treatment in the first heat treatment step, the temperature lowering treatment is performed in an atmosphere containing no hydrogen compound. 5. Manufacturing method.   5. The method according to claim 1, wherein the first heat treatment step is performed in a growth furnace subsequent to the growth step, and the second heat treatment step is performed in a furnace different from the growth furnace. A method for manufacturing a semiconductor device according to claim 1.

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