JP2009038559A - Semiconductor integrated circuit, imaging system, and signal converting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve image quality by performing noise reduction in outputting digital image data, by reducing the number of bits to be converted in switching after code conversion even in a case where image or the like that is monochrome but has a gradation change is picked up. <P>SOLUTION: A semiconductor integrated circuit includes: an amplifier circuit 22 for amplifying an analog color video signal input from an imaging element 10; an A/D conversion circuit 23 for converting the video signal amplified by the amplifier circuit 22 into a digital signal; an adjacent color difference data generating circuit 41 for generating color difference data by taking a differential between adjacent data in different data streams of color information; and a code converting means 42 for converting the code of the color difference data generated by the adjacent color difference data generating circuit 41 into a code which reduces the number of bits to be changed in switching between preceding and following codes. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for reducing noise energy generated by transmission of digital image data using a code conversion method in an imaging system using an imaging element such as an image sensor. More specifically, the present invention relates to a semiconductor integrated circuit having such a function, an imaging system, and a signal conversion method. The technique of the present invention is useful as a technique for reducing noise energy with a digital interface of an internal LSI in, for example, a digital camera or a video camera.

  In recent years, there has been a remarkable transition from analog technology to digital technology in the camera industry. In particular, digital still cameras that do not require film or development are booming, and camera-equipped mobile phones dominate. Also, there are remarkable things in increasing the number of pixels in a digital still camera and improving the image quality by image processing.

  An analog front-end device (large-scale semiconductor) that converts a video signal (analog charge signal) output from a solid-state image sensor (image sensor) into digital data corresponding to the analog charge signal and outputs the digital still camera Integrated circuit).

  Digital data output by the analog front-end device is subjected to various image processing such as luminance signal processing, color separation, and color matrix processing by a signal processing circuit such as a DSP (Digital Signal Processor). The solid-state imaging device, the DSP, and the analog front end device are each formed as a semiconductor integrated circuit and mounted on a printed wiring board.

  FIG. 16 is a block diagram showing a schematic configuration of an AD conversion LSI used in an imaging system according to a conventional technique (see Patent Document 1), and FIG. 21 is a conventional imaging system (electronic still camera or video) solved by the conventional technique. It is a figure explaining the problem of a camera.

  First, problems of the conventional technology will be described with reference to FIG. This imaging system includes a CCD (Charge Coupled Device) 91, an AD conversion LSI 92, and a DSP 93 as imaging elements. The CCD 91, the AD conversion LSI 92, and the DSP 93 are each composed of a semiconductor integrated circuit and mounted on the printed wiring board 100. Reference numeral 101 denotes a display. The CCD 91 outputs an analog video signal obtained by imaging to the AD conversion LSI 92. The AD conversion LSI 92 converts the input analog video signal into a digital signal and outputs it to the DSP 93. The DSP 93 performs image processing on the input digital signal and displays it on the display 101.

  The AD conversion LSI 92 is connected to the DSP 93 on the printed wiring board 100 via the printed wiring. When image data generated by the AD conversion LSI 92 is transmitted to the DSP 93 via the wiring, a power supply noise is generated at the time of output, and the power supply line (Vcc and ground) on the printed wiring board 100 is connected to the CCD 91 side. Power noise wraps around. As a result, power noise enters the analog video signal output from the CCD 91 to the AD conversion LSI 92. Also, power noise circulates from the output terminal side to the input terminal side through the power supply line and the semiconductor substrate inside the AD conversion LSI 92. In particular, in a digital signal output from the AD conversion LSI 92, a large through current or load drive current flows at the time of bit switching, and noise caused by this flows on the power supply line. The output circuit of an LSI has a relatively large output current. Further, the AD conversion LSI has an amplification circuit such as a PGA (programmable gain control amplifier) that amplifies the input analog signal, and noise propagated to the input side is also amplified together with the video signal. As a result, noise appears on the display screen of the display, leading to deterioration in display image quality.

  In order to reduce noise, there is a measure to connect a large-capacitance pass capacitor to the power supply terminal of the AD conversion LSI. However, the chip size is increased and the system mounting efficiency is lowered, and the effect of improving the noise situation is not sufficient.

  The prior art (Patent Document 1) shown in FIG. 16 has been proposed as a solution to the above-described problem found in the conventional technique of FIG. In FIG. 16, 70 is a CCD, 80 is an AD conversion LSI, 81 is a CDS (correlated double sampling circuit) that samples an analog video signal from the CCD 70, 82 is a PGA that can variably control the amplification gain for the sampling signal, 83 Is an AD conversion circuit (ADC) that converts the amplified analog signal into a digital signal, and 84 is an encoding & code conversion circuit that differentiates the AD converted digital image data and converts it into a gray code. Reference numeral 88 denotes an output buffer for outputting the code-converted signal to the outside of the chip. The substantial difference from FIG. 21 resides in the encoding & code conversion circuit 84 inserted between the AD conversion circuit 83 and the output buffer 88. Gray code is a type of code that displays integers in binary numbers, and is a code that is assembled so that there is always only one bit change position in binary numbers when the original integer changes by one. It is.

  The encoding & code conversion circuit 84 takes the difference between the codes of adjacent pixels related to the same color after AD conversion, and switches the obtained difference output code between the preceding and succeeding codes such as the Gray code. Convert to a code with fewer change bits. As a result, the through current in the output circuit and the drive current of the load are reduced, and the noise energy accompanying the change in output is reduced. A typical example of the code conversion means is a binary-gray code conversion circuit for converting an input binary code into a gray code. Here, in this prior art, it is noted that the difference output code to be reduced in the number of change bits at the time of switching is “difference between codes of adjacent pixels related to the same color after AD conversion”. There is a need to. In particular, pay attention to “adjacent pixels related to the same color”.

In the Bayer arrangement, R (red) and G (green) pixels are arranged on one line as R, G, R, G, R, G..., And G, B are arranged on another line. , G, B, G, B..., G (green) and B (blue) pixels are arranged. Explaining the former arrangement, “difference between codes of adjacent pixels related to the same color” is
ΔR _3-1 = (R data value in the third column) − (R data value in the first column)
ΔR _5-3 = (R data value in the fifth column) − (R data value in the third column)
ΔR _7-5 = (R data value in the seventh column) − (R data value in the fifth column)
... and that
ΔG _4-2 = (G data value in the fourth column) − (G data value in the second column)
ΔG _6-4 = (G data value in the sixth column) − (G data value in the fourth column)
ΔG _8-6 = (G data value in the eighth column) − (G data value in the sixth column)
…That's what it means. This is to extract a level change of the same color along the horizontal direction as differential information. Since a signal after general AD conversion is data in which two types of color data are repeated every other pixel, the above method takes a difference between data of the same color every other pixel.

  FIG. 17 shows the configuration of the encoding & code conversion circuit 84 in the prior art (Patent Document 1). Reference numeral 85 denotes a delay circuit that delays the data output from the AD conversion circuit 83 by a predetermined clock cycle. Reference numeral 86 denotes a subtraction circuit that takes a difference between the data output from the AD conversion circuit 83 and the data delayed by the delay circuit 85 ( A difference circuit 87) is a binary-gray code conversion circuit for converting binary data obtained by the difference into a gray code.

  FIG. 18 shows specific procedures for difference processing and binary-Gray code conversion. The delay amount in the delay circuit 85 is two cycles of the sampling clock in the CDS 81. The reason for two periods is to take a difference between data of the same color every other pixel.

As shown in the column (A) of FIG. 18, it is assumed that the R signal and the G signal are alternately input. Then, it is assumed that the AD conversion value of each signal is changed (decimal number) as in the (B) column. The column (C) represents the binary code that is actually output. In the case of the old technology, this code was output as it is. The number of change bits at the time of switching, which is the number of bits that change when each code switches to the next code by comparing adjacent ones, is as shown in column (D). here,
ΔGR _2-1 = (G data value in the second column minus R data value in the first column)
ΔRG _3-2 = (R data value in the third column−G data value in the second column)
ΔGR _4-3 = (G data value in the fourth column−R data value in the third column)
ΔRG _5-4 = (R data value in the fifth column−G data value in the fourth column)
I think like that.

In the prior art (Patent Document 1), the subtraction circuit 86 inputs a binary code as shown in the column (C) from the AD conversion circuit 83, and the same colors of adjacent pixels, that is, the column (B) in FIG. The difference between every other value is obtained as indicated by the arc arrow. Here, according to what I explained earlier,
ΔR _3-1 = (R data value in the third column) − (R data value in the first column)
ΔG _4-2 = (G data value in the fourth column) − (G data value in the second column)
ΔR _5-3 = (R data value in the fifth column) − (R data value in the third column)
ΔG _6-4 = (G data value in the sixth column) − (G data value in the fourth column)
I think like that. The initial data is left as it is without taking a difference. The value output from the subtracting circuit 86 is as in the (E) column in decimal numbers, and as in the (F) column in binary code.

  The binary-gray code conversion circuit 87 converts the differential binary code in column (F) into a gray code. The result is the (G) column. A downward thick arrow represents the binary-gray code conversion.

  Comparing adjacent codes in the (G) column, the number of change bits at the time of switching is as in the (H) column. When the column (D) and the column (H) are compared, the number of change bits at the time of switching is reduced in the conventional technique (Patent Document 1) compared to the conventional method.

  Incidentally, the total value of the number of change bits (4, 4, 4, 5, 6, 5, 4) at the time of switching in the case of the conventional technology is “32”, on the other hand, the change at the time of switching in the case of the conventional technology. The total value of the number of bits (4, 4, 0, 2, 1, 1, 1) is “13”, and improvement is recognized.

  If the difference between the same colors is taken and converted into a gray code as described above, there is no significant difference between the differences even if the colors are different between the adjacent colors. For example, output of R (red) component image data The number of bits that change when switching from G to (G) component image data output is also small.

  The reason for performing the binary-gray code conversion is as follows. If the binary-Gray code conversion is not performed simply by taking the difference, the following problem remains. In one screen, the rate at which the difference is positive and the rate at which the difference is negative are substantially the same. The binary code is represented by 2's complement. When changing from positive to negative, the code changes greatly from all “0” to all “1”, and when changing from negative to positive, the code changes greatly from all “1” to all “0”. Therefore, if the binary code is converted to the gray code, the code change is small when changing from positive to negative or from negative to positive.

  Here, for reference, the relationship between the binary code represented by 2's complement and the Gray code will be described. For example, in a 3-bit binary code, when the decimal number “0” changes to “−1”, the value changes from “000” to “111”. Similarly, a code having 4 bits, 8 bits, or more bits changes from all “0” to all “1”. In this case, all the bits (three) are switched. On the other hand, in the Gray code, for example, in the case of 3 bits, when the decimal number is changed from “0” to “−1”, the bit changes from “000” to “100”. It is. Accordingly, the through current that flows when the output is switched in the output buffer is significantly less when the gray code is output than when the binary code is output.

In the video signal, since there is little abrupt change between adjacent pixels, even if the code after AD conversion is immediately converted to a gray code, the amount of bit change is small between the same colors. In the prior art, taking the difference without immediately converting the code after AD conversion into gray code,
1185943682562_0
In the case of a CCD output through a filter having a color element array such as the above, even if there is little change between adjacent pixels in a video signal, the code difference between different colors of one pixel is often relatively large. is there. As an exception, if the subject to be photographed is gray with little color change, the code difference between different colors is also reduced.

FIG. 20 shows the configuration of the gray-binary differential decoding circuit 90 on the receiving side in the prior art. 91 is a gray-binary code conversion circuit, 92 is an adding circuit, and 93 is a delay circuit.
JP 2002-300591 A

In the case of the above prior art, it is assumed that there is a correlation between changes in the data difference values of the two colors output from the image sensor under general imaging conditions, and there is little change between the difference values. In the example described above, the change between ΔR _3-1 and ΔG _4-2 , the change between ΔG _4-2 and ΔR _5-3 , ΔR _5-3 and ΔG _6-4 It is assumed that there are few changes between

However, when a natural image or the like having a single color and having a gradation change is captured, the above assumption is not satisfied, and a change between two color difference values becomes large. For example, in the case of the example described above, a change between ΔR _3-1 and ΔG _4-2 , a change between ΔG _4-2 and ΔR _5-3 , ΔR _5-3 and ΔG ₆ Changes between _-4 and so on will become larger.

  In addition, sampling of the same color is every other pixel. Therefore, especially when a gradation component having a frequency characteristic in the vicinity of the Nyquist frequency corresponding to ½ of the sampling frequency is included, the change between the difference values adjacent to each other in the column (D) becomes remarkably large.

In this way, when the change between the difference values becomes large, even if the Gray code conversion is used for the code conversion, the number of bits changing at the time of switching by the Gray code is not reduced, and the noise reduction effect is reduced (see FIG. 19). ). Incidentally, in the case of FIG. 18, the data string in column (B) is
(200, 100, 200, 100, 202, 101, 200, 100, ...)
On the other hand, in the case of FIG. 19, the data string in column (B) is
(200, 100, 207, 100, 212, 101, 209, 100, ...)
Thus, the change of the R signal is large. As for the number of change bits at the time of switching, the total value of (4, 4, 0, 2, 1, 1, 1) in the case of FIG. 18 is “13”, whereas in the case of FIG. The total value of (4, 3, 1, 3, 2, 2, 2) is “17” and increases (an example).

  The present invention was created in view of such circumstances, and even when an image or the like that is a single color and has a gradation change is captured, the number of bits that change at the time of switching after code conversion is reduced, thereby reducing the digital image. An object of the present invention is to provide a semiconductor integrated circuit, an imaging system, and a signal conversion method that can improve image quality by reducing noise when outputting data.

A semiconductor integrated circuit according to the present invention comprises:
An amplifier circuit for amplifying an analog color video signal input from the image sensor;
An AD converter circuit for converting the video signal amplified by the amplifier circuit into a digital signal;
Adjacent color difference data generating means for generating color difference data by taking a difference between adjacent data in a data string having different color information for each pixel after AD conversion by the AD conversion circuit;
Code conversion means for converting the code of the color difference data by the adjacent color difference data generation means into a code with a small number of change bits when switching between the preceding and succeeding codes is provided. This semiconductor integrated circuit is assumed to be configured as an analog front-end device on a chip. The “code conversion means for converting into a code with a small number of change bits when switching between the previous and next codes” is, for example, a binary-Gray code conversion circuit.

  The feature of the configuration of the present invention in comparison with the prior art is the adjacent color difference data generation means. The differentiating means in the case of the conventional technique takes a difference between codes of adjacent pixels related to the same color. On the other hand, the adjacent color difference data generation means of the present invention generates color difference data by taking the difference between adjacent data in a data string having different color information for each pixel after AD conversion. The difference is that “color information is different” with respect to “same color”. In the above configuration, “a data string having different color information for each pixel” assumes that the image sensor in the previous stage is mounted with a plurality of color filters that photoelectrically convert the light image of the subject. In order to facilitate understanding, taking a Bayer array as an example, in the case of the conventional technology, the difference processing target pixel is every other two pixels, whereas in the present invention, the difference processing target pixel is Pixels are adjacent pixels. Considering the arrangement of R1, G1, R2, G2, R3, G3..., In the case of the prior art, R1-R2, R2-R3... And G1-G2, G2-G3. Then, R1-G1, G1-R2, R2-G2, G2-R3, R3-G3. The combination of Ri-Rj and Gi-Gj in the case of the prior art is two kinds of color difference data, but Ri-Gj and Gi-Rj in the case of the present invention are one kind of color difference data. Note that this is merely an example and does not restrict the present invention.

  As described above, the color difference data generated by taking the difference between adjacent data having different color information is subjected to code conversion by the code conversion means, so that the number of change bits at the time of switching between the preceding and succeeding codes is increased. Convert to less code. By doing this, even when an image having a single color but having a gradation change is captured, the number of bits that change at the time of switching after code conversion is smaller than that of the prior art, and the semiconductor integrated circuit including the AD conversion circuit is reduced. The through current in the output circuit and the drive current of the output load are reduced. As a result, noise reduction when outputting digital image data becomes more effective, and it is possible to improve image quality. Further, since the total amount of noise energy is reduced, power consumption can be reduced.

  In the semiconductor integrated circuit having the above-described configuration, the adjacent color difference data generating means obtains a difference between adjacent data in a data string having different color information for each pixel after AD conversion by the AD conversion circuit, and for each pixel clock. A color difference type differentiating unit that generates color difference data having different positive and negative signs, and inverting the positive and negative signs every other data for color difference data having a different positive and negative sign for each pixel clock generated by the color difference type differentiating unit, There is an aspect in which it is constituted by a positive / negative sign inversion means for generating color difference data with positive and negative signs. This is a more detailed description of the configuration of the adjacent color difference data generating means, and is an aspect in the case where the adjacent color difference data generating means is a combination of a color difference type differentiating means and a positive / negative sign inverting means. The “color difference type” emphasizes that it is closely related to “difference between adjacent data in a data string having different color information for each pixel”, which is a feature of the present invention. The positive and negative signs are plus “+” and minus “−”.

  In this case, the color difference type differentiating means inputs the data string after AD conversion from the AD conversion circuit, takes the difference between adjacent data in the data string having different color information for each pixel, and determines whether the difference is positive or negative for each pixel clock. Color difference data having different signs is generated. Thus, the difference in sign of the color difference data for each pixel clock typically appears when the color difference type differentiating means is composed of a delay circuit and a subtraction circuit, as will be described later. If the color difference data has a different sign for each pixel clock, it is difficult to convert the code into a code with a small number of change bits when switching between the preceding and succeeding codes. Therefore, the positive / negative sign inverting means inverts the positive / negative sign every other data to generate color difference data with the positive / negative signs aligned. This is one type of continuous color difference data. If the color difference data has both positive and negative codes, the code is correctly converted to a code with a small number of bits that change when switching between the preceding and succeeding codes. As a result, when the output digital signal is switched, the number of bits that change simultaneously (the number of bits that change simultaneously) decreases, thereby reducing the through current in the output circuit and the drive current of the load, resulting in noise accompanying the change in output. Can be reduced.

  Further, in the semiconductor integrated circuit having the above configuration, the color difference type differentiating means includes a delay circuit that delays input data from the AD converter circuit, and a subtraction that obtains a difference between the data delayed by the delay circuit and the input data. There is a mode in which the delay circuit is configured to perform a delay process of one pixel clock when the data changes in color information every other pixel. With this configuration, the subtraction circuit calculates the difference between the delay data and the current data. However, since the delay circuit is configured as a delay circuit having a delay amount of 1 pixel clock, the difference between adjacent data having different color information is obtained. Thus, it is possible to generate color difference data. However, since the delay amount is one pixel clock, the color difference data has a different sign for each pixel clock. The sign-inversion means to be described next eliminates the disadvantages of this alternating code.

  In the semiconductor integrated circuit having the above-described configuration, the positive / negative sign inverting means may be arbitrary arbitrary temporally forward in the horizontal direction of the effective data with respect to the chrominance data whose positive / negative sign is inverted for each data from the chrominance type differentiating means. There is a mode in which a pixel clock whose phase is fixed with respect to the phase position of the color clock is used and the sign of the color difference data is inverted every other data by the frequency division control of the pixel clock.

  Further, in the semiconductor integrated circuit having the above configuration, the positive / negative sign inverting means is temporally forward in the vertical direction of the effective data with respect to the chrominance data in which the positive / negative sign is inverted for each data from the chrominance type differentiating means. There is an aspect in which a pixel clock whose phase is fixed with respect to an arbitrary phase position is used, and the sign of the color difference data is inverted every other data by dividing the pixel clock by two.

  Whether the reference phase of the pixel clock is fixed to the front of the effective data in the horizontal direction or the front of the vertical direction, the positive / negative sign inversion means generates a positive / negative sign for each data output from the subtraction circuit. The color difference data to be inverted is adjusted to the color difference data having the same sign. If color difference data in which the sign is inverted for each data is sent to the next code conversion means as it is, and this is converted into code, it can be converted into a code with a small number of change bits when switching between previous and next codes. It is difficult. As described above, adjustment to color difference data with positive and negative signs will not cause such inconvenience, and code conversion means can correctly convert to a code with a small number of change bits when switching between previous and next codes. It becomes possible.

  In the semiconductor integrated circuit having the above-described configuration, the adjacent color difference data generating means includes a zero data insertion means for inserting zero data in a preceding data portion of valid data before the color difference type differentiating means. There is. When the color difference type differentiating means is composed of a delay circuit and a subtraction circuit, the leading data of valid data is lost. The zero data insertion means avoids the loss of the head data. As a result, the entire effective data can be handled well, and an inadvertent increase in noise energy is suppressed.

  In the semiconductor integrated circuit having the above configuration, the code conversion means is preferably a binary-gray code conversion circuit that converts an input binary code into a gray code.

  In summary, according to the semiconductor integrated circuit of the present invention, there is provided adjacent color difference data generating means for generating color difference data by taking the difference between adjacent data in a data string having different color information for each pixel after AD conversion. Since the code of the color difference data by the adjacent color difference data generating means is converted by the code converting means into a code (for example, a gray code) having a small number of change bits when switching between the preceding and succeeding codes, the difference between the color difference data adjacent to each other Are not so different, and the number of simultaneously changing bits can be made smaller than that of the prior art in switching the output of image data having a natural gradation. As a result, noise reduction when outputting digital image data becomes more effective, and it is possible to improve image quality. Further, since the total amount of noise energy is reduced, power consumption can be reduced.

  The above is the description of the semiconductor integrated circuit according to the present invention. Hereinafter, the imaging system according to the present invention will be described.

  An imaging system according to the present invention includes any one of the semiconductor integrated circuits as a first semiconductor integrated circuit as a component, and further inputs a code output from the first semiconductor integrated circuit into an original binary code. A color difference data decoding unit for decoding and conversion and a second semiconductor integrated circuit including an image processing circuit for the binary code output from the color difference data decoding unit are provided.

  The color difference data decoding means includes: a code reverse conversion means for inputting the color difference data output from the first semiconductor integrated circuit and performing decoding conversion (decoding processing) into an original binary code; and the code reverse conversion means A positive / negative sign inversion restoring means for inverting and restoring the positive / negative sign every other data with respect to the color difference data having the same positive / negative sign at the output, and generating chrominance data in which the positive / negative sign is inverted for each data, and a positive / negative sign for each data Subtracting and accumulating means for accumulating sequentially while taking the difference between adjacent data of the color difference data that is inverted.

  The code reverse conversion means inputs the color difference data sent from the first semiconductor integrated circuit (this is a data string of a code with a small number of simultaneously changing bits) and converts it into the original binary code of the color difference. Perform decryption conversion. The color difference binary code obtained by this decoding conversion is color difference data with positive and negative signs. If this is subtracted and accumulated as it is, the data string obtained by this processing is a data string in which the sign of each data is reversed with respect to the data string output from the AD conversion circuit in the first semiconductor integrated circuit. End up. In other words, it is not restored correctly. Therefore, before processing by the subtracting and accumulating means, it is guided to the positive / negative sign inversion restoring means. The positive / negative sign reversal restoring means inverts and restores the positive / negative sign every other data with respect to the color difference data having the same positive / negative sign from the code reverse conversion means, and generates color difference data in which the positive / negative sign is inverted for each data. Now you are ready for subtraction accumulation. The color difference data with the positive / negative sign inverted for each data is taken into the subtraction accumulating means, and sequentially accumulated while taking the difference between adjacent data of the color difference data with the positive / negative code inverted for each data. As a result, the data string obtained is a data string having the same form as the data string output from the AD conversion circuit in the first semiconductor integrated circuit, and is correctly restored.

  In the imaging system having the above-described configuration, the positive / negative sign inversion restoring unit temporally applies the same effective data as in the first code conversion in the horizontal direction with respect to the color difference data in which the positive / negative signs are aligned at the output of the code reverse conversion unit. Using a pixel clock whose phase is fixed with reference to the phase position of the front reference, the positive / negative sign of the color difference data is inverted and restored every other data by the frequency division control of the pixel clock. Is configured to generate color difference data that is inverted.

  Further, in the imaging system having the above-described configuration, the positive / negative sign inversion restoring unit temporally operates in the vertical direction of the same effective data as that of the first code conversion with respect to color difference data in which positive / negative signs are aligned at the output of the code reverse conversion unit. Using a pixel clock whose phase is fixed with respect to the front reference phase position as a reference, the positive / negative sign of the chrominance data is inverted and restored every other data by dividing the pixel clock by 2 and positive / negative for each data. There is an aspect in which color difference data whose sign is inverted is generated.

  Whether the reference phase of the pixel clock is fixed in front of the effective data in the horizontal direction or in the front of the vertical direction, the positive / negative sign inversion restoration means has one data for the positive / negative sign of the color difference data in the correct phase relationship. Perform the correct reverse restoration correctly.

  In the imaging system having the above-described configuration, the subtraction accumulation unit includes a subtraction circuit that inputs the output data of the positive / negative sign inversion restoration unit, and a delay circuit that delays a calculation result by the subtraction circuit. The delayed calculation result data is connected as an accumulation input of the subtracting circuit, and the delay circuit is configured to perform a delay process of one pixel clock when the data data changes in color information every other pixel. There is a mode. By doing so, it is possible to correctly restore the obtained data string into a data string having the same form as the data string output from the AD conversion circuit of the first semiconductor integrated circuit.

  In the imaging system having the above configuration, the subtracting and accumulating unit may include a reset unit that performs initial zero data insertion. By doing so, it is possible to eliminate the influence of the 0 data inserted by the 0 data insertion means in the first semiconductor integrated circuit and restore the data string as completely correct.

  In the imaging system having the above-described configuration, an enable code adding circuit for adding an enable code indicating a reference timing at an arbitrary timing is provided at a preceding stage of the code converting means, and an enable code for decoding the enable code is provided at a subsequent stage of the code inverse converting means. There is a mode in which a code decoding circuit is provided and the enable code decoded by the enable code decoding circuit is used as a reference timing for starting the decoding process. By doing so, it becomes possible to start exhibiting the above-mentioned specific functions by the imaging system of the present invention at an arbitrary timing.

  In the imaging system having the above configuration, it is preferable that the code reverse conversion unit is a gray-binary code conversion circuit that converts an input gray code into a binary code.

A signal conversion method according to the present invention is a signal conversion method for converting an analog color video signal input from an image sensor into a digital signal,
AD converting the video signal;
A step of performing difference processing with adjacent data in the same direction while shifting the target pixel in one dimension with respect to data having different color information for each pixel;
Generating color difference data having different one-dimensional positive and negative signs;
A step of inverting the sign of the color difference data every other data with respect to a reference position for color difference data having a different positive / negative sign for each data to obtain color difference data with a positive / negative code aligned;
Converting the color difference data with the positive and negative signs into a code with little change in adjacent data.

  According to the present invention, the adjacent color difference data generating means is inserted between the AD conversion circuit and the code converting means, and the difference between adjacent data in the data string having different color information is obtained for each pixel after AD conversion. Since data is generated, even when an image with a single color but with gradation changes is captured, the number of bits that change at the time of switching after code conversion is small compared to the conventional technology, and the output circuit of a semiconductor integrated circuit Can reduce the through current and the drive current of the output load, more effectively reduce noise when outputting digital image data, and improve the image quality. Further, since the total amount of noise energy is reduced, power consumption can be reduced.

  Embodiments of a semiconductor integrated circuit and an imaging system according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a schematic configuration of an imaging system according to Embodiment 1 of the present invention. This imaging system is composed of an image sensor, an analog front end device, and a DSP.

  In FIG. 1, 10 is an image sensor such as a CCD as an image sensor, 20 is an analog front-end device (AD conversion LSI) which is a first semiconductor integrated circuit, and 30 is a DSP which is a second semiconductor integrated circuit. . As a component of the analog front-end device 20, 21 is a correlated double sampling circuit (CDS) that samples the analog color video signal output from the image sensor 10 and input to the input terminal IN, and 22 amplifies the sampled video signal. A gain controllable amplifier circuit (programmable gain amplifier (PGA)), 23 an AD converter circuit (ADC) that converts the amplified analog signal into a digital signal, and 24 differentiating adjacent digital image data after AD conversion A color difference type encoding & code conversion circuit that inverts the sign of data every other pixel and converts it into a gray code, and 25 is a parallel data output that outputs the code converted signal from the output terminal OUT to the outside of the chip. Circuit. 26 is a CPU interface, 27 is a clock multiplication circuit, 28 is a synchronization signal generation circuit (SSG), and 29 is a timing generator. As a component of the DSP 30, 31 is a color difference data decoding circuit that converts a gray code into a binary code, inverts the sign of color difference data every other pixel, and decodes two types of color data. 32 is a color difference data decoding circuit 31. 2 is an image processing circuit that performs image processing on the binary code output from the computer.

  Of the components of the analog front-end device 20, it may be considered that the circuits other than the color difference type encoding & code conversion circuit 24 are also provided in the prior art. That is, the color difference type encoding & code conversion circuit 24 inserted between the AD conversion circuit 23 and the parallel data output circuit 25 and the color difference data decoding circuit 31 added in association therewith are the features of this embodiment. It is.

  Although not shown, in the LSI chip, a control circuit for controlling the operation of the entire chip and controlling the gain of the programmable gain amplifier 22, a clock signal for giving sampling timing to the CDS 21, an AD conversion circuit 23, and a color difference are provided. A clock generation circuit (or a clock buffer that distributes a clock signal supplied from the outside to a circuit inside the chip) that generates a clock signal necessary for the operation of the type encoding & code conversion circuit 24 is provided. The circuit configuration of the analog front-end device 20 is not limited to the illustrated one.

  FIG. 2 is a block diagram showing a detailed configuration of the color difference type encoding & code conversion circuit 24. As shown in FIG. In FIG. 2, reference numeral 41 denotes an adjacent color difference data generation circuit that generates color difference data by taking a difference between adjacent data in a data string having different color information for each pixel after AD conversion by the AD conversion circuit 23, and 42 is adjacent color difference data. The code conversion circuit 42 converts the code of the color difference data by the generation circuit 41 into a code with a small number of change bits when switching between the preceding and succeeding codes. The color difference type encoding & code conversion circuit 24 includes an adjacent color difference data generation circuit 41 and a code conversion circuit 42.

  51 is a 0 data insertion circuit that inserts 0 data into the data output from the AD conversion circuit 23, and 52 is a difference between adjacent data in a data string having different color information for each pixel after AD conversion by the AD conversion circuit 23. Accordingly, a color difference type differentiating circuit for generating color difference data having a different sign for each pixel clock, and 53 for color difference data having a different sign for each pixel clock generated by the color difference type difference circuit 52. This is a positive / negative sign inverting circuit that inverts the positive / negative sign every data and generates color difference data with the positive / negative signs aligned. The adjacent color difference data generation circuit 41 includes a 0 data insertion circuit 51, a color difference type difference circuit 52, and a positive / negative sign inversion circuit 53.

  54 is a delay circuit that delays the data output from the 0 data insertion circuit 51 by one clock cycle, and 55 is a subtraction circuit that takes the difference between the data output from the 0 data insertion circuit 51 and the data delayed by the delay circuit 54. It is. The color difference type difference circuit 52 includes a delay circuit 54 and a subtraction circuit 55.

  The code conversion circuit 42 is composed of a binary-gray code conversion circuit, and converts the color difference binary data in which the positive and negative signs are aligned by the color difference type differentiating circuit 52 and the positive / negative sign inversion circuit 53 into a gray code.

  FIG. 3 is a block diagram showing a more detailed configuration of the color difference type encoding & code converting circuit 24. The color difference type encoding & code conversion circuit 24 includes an adjacent color difference data generation circuit 41 and a binary-gray code conversion circuit 42 which is an example of a code conversion circuit. The adjacent color difference data generation circuit 41 includes a 0 data insertion circuit 51, a color difference type difference circuit 52, and a positive / negative sign inversion circuit 53. The color difference type difference circuit 52 includes a delay circuit 54 and a subtraction circuit 55. The positive / negative sign inverting circuit 53 includes an amplifier 56 having a gain coefficient of minus 1, a selector 57, and a divide-by-2 circuit 58 that divides the pixel clock by two.

FIG. 3B is an operation explanatory diagram of the color difference type encoding & code converting circuit 24. As a premise, the color filter attached to the image sensor 10 is assumed to be a Bayer array of three primary colors R (red), G (green), and B (blue) as shown in FIG.
1185943682562_1
Then, as shown in FIG. 4B, it is assumed that the horizontal scanning video signal on the even lines and the horizontal scanning video signal on the odd lines are alternately scanned in the vertical direction. In this case, the delay amount in the delay circuit 54 is one clock cycle (one sampling clock cycle in the CDS 21). Also, two types of color data (G data and R data, or B data and G data) that are alternately repeated in one line are generalized as a data and b data.

  Now, referring back to FIG. 3B, the outline of the operation of the color difference type encoding & code converting circuit 24 will be described.

First, in the 0 data insertion circuit 51, 0 data is inserted at the head of a series of data strings (a1, b1, a2, b2, a3, b3, a4, b4...) Input from the AD conversion circuit 23. Thus, 0 data insertion data string D1 = (0, a1, b1, a2, b2, a3, b3, a4, b4...) Is generated. This 0 data insertion data string D1 is subjected to various processes in the delay circuit 54, the subtraction circuit 55, the positive / negative sign inverting circuit 53, and the binary-Gray code conversion circuit 42, and then the binary-Gray code conversion data string D4 = (a1-0). , A1-b1, a2-b1, a2-b2, a3-b2, a3-b3, a4-b3, a4-b4, ...) are generated and output. This binary-gray code conversion data string D4 (except for the leading a1-0) is the (J) column in FIG.
R1-G1, R2-G1, R2-G2, R3-G2, R3-G3, R4-G3, R4-G4 ...
It corresponds to. That means
100, 100, 100, 102, 101, 99, 100 ...
It corresponds to.

  FIG. 5 shows the operation outline of FIG. 3B in detail in time series. 5A is an explanation of the operation by the delay circuit 54 and the subtraction circuit 55, FIG. 5B is an explanation of the operation by the positive / negative sign inversion circuit 53, and FIG. 5C is an explanation of the operation by the binary-Gray code conversion circuit 42. .

First, the operation of the delay circuit 54 and the subtraction circuit 55 will be described with reference to FIG. In this operation, one type of color difference data is generated by taking a difference between adjacent pixel codes in a data string having different color information for each pixel. In the delay circuit 54, the 0 data insertion data string D1 = (0, a1, b1, a2, b2, a3, b3, a4, b4...) Is delayed by one clock cycle and output to the subtraction circuit 55. The subtraction circuit 55 calculates the difference between the 0 data insertion data string D1 = (0, a1, b1, a2, b2, a3, b3, a4, b4...) And its 1 clock cycle delay data string. This is shown in FIG. The left input data string is 0 data insertion data string D1 = (0, a1, b1, a2, b2, a3, b3, a4, b4...). The output data string on the right side is the differentiated data string D2, and in the differentiated data string D2, the lower data string is the current data string and the upper data string is the delayed data string. The difference is (delayed data) − (current data) = (upper data) − (lower data). That is, the differentiated data string D2 is
Delay data string: (0, a1, b1, a2, b2, a3, b3, a4, b4...)
Current data string: (0, a1, b1, a2, b2, a3, b3, a4, b4...)
As
D2: 0-a1, a1-b1, b1-a2, a2-b2, b2-a3, a3-b3, b3-a4, a4-b4 ...
It becomes. In this, the (ab) format and the (ba) format are alternated. Since the subtracted value before one pixel clock is switched to the subtracted value in the next cycle, a color difference data string having a different positive / negative sign for each pixel clock is obtained. Although the sign is different for each pixel clock, it is one kind of color difference data.

  Here, the difference from the prior art will be explained. In the case of the prior art, the difference between the codes of adjacent pixels related to the same color is taken, whereas in the present embodiment, This means that color difference data is generated by taking a difference between adjacent data in a data string having different color information for each pixel. It is necessary to pay attention to the expression “color difference data”. The same applies to the “color difference type” of the color difference type encoding & code converting circuit 24 and the color difference type differentiating circuit 52 of the constituent elements shown in FIGS. In the case of the prior art, pixels subject to difference processing are the same color, not a color difference.

Next, the operation of the positive / negative sign inverting circuit 53 will be described with reference to FIG. The left input data string is a difference data string D2 having a color difference with a different sign for each pixel clock. The difference data string D2 is input to the “H” selection input terminal of the selector 57. Further, an inverted data string D2 ′ = − D2 obtained by inverting the differentiated data string D2 by the amplifier 56 having a gain coefficient of minus 1 is input to the “L” selection input terminal of the selector 57. The selector 57 alternately selects the “L” selection side and the “H” selection side every clock cycle according to the selection control signal from the divide-by-2 circuit 58. As a result, the sign inversion data string D3 output from the positive / negative sign inversion circuit 53 is:
D3: a1-0, a1-b1, a2-b1, a2-b2, a3-b2, a3-b3, a4-b3, a4-b4 ...
It becomes. These are all in the (a−b) format, and are converted into one continuous color difference data string in which positive and negative signs are aligned.

  Next, the operation of the binary-gray code conversion circuit 42 will be described with reference to FIG. The left input data string is a color-inverted sign-inverted data string D3 in which positive and negative signs are aligned. The binary-gray code conversion circuit 42 performs binary-gray code conversion on the code-inverted data string D3, and the code having a small number of bits that change when switching is the number of bits that change when each code is switched to the next code. It is converted into a data string D4.

D4: Gray Code Representation of D3 FIG. 6 is a circuit diagram showing a specific configuration of the binary-gray code conversion circuit 42. The binary-gray code conversion circuit 42 includes a plurality of exclusive OR gates. The number of exclusive OR gates is one less than the number of bits of the code to be converted. Here, as an example, if the number of bits of the code to be converted is 8 bits, seven exclusive OR gates G1 to G7 are used.

  The exclusive OR gate G1 takes an exclusive OR of the first bit d0 and the second bit d1, and outputs the result as the converted first bit d0 ′. The exclusive OR gate G2 takes an exclusive OR of the second bit d1 and the third bit d2, and outputs the result as the converted second bit d1 ′. Similarly, the exclusive OR gate G7 takes an exclusive OR of the seventh bit d6 and the eighth bit d7 and outputs the result as the converted seventh bit d6 ′. The most significant 8th bit d7 is output as it is as the converted 8th bit d7 '.

  FIG. 6 shows an example of converting an 8-bit binary code to a gray code. Besides this, a code conversion circuit having an arbitrary number of bits such as 10 bits and 12 bits can be configured in the same manner.

  Next, a specific example of the operation of the color difference type encoding & code conversion circuit 24 will be described with reference to FIG. 7, FIG. 8, and FIG. FIG. 7 shows the red system single level in which the R signal and the G signal data string alternately input have an R level larger than the G level, as shown in FIG. 18A in the case of the prior art. It is an operation example in the case of the color data. On the other hand, FIG. 8 shows an operation example in the case where the data string is a single red color and has a gradation change. FIG. 9 shows a correspondence table (excerpts of necessary parts) of decimal numbers, binary codes, and gray codes. First, the operation in the case of FIG. 7 will be described, and then the operation in the case of FIG. 8 will be described.

(1) Description of the operation example of FIG. 7 The input data string is the same as the column in FIG.
(200, 100, 200, 100, 202, 101, 200, 100, ...)
It has become. In this data string, R and G are alternately input, and is red system single level color data having an R level larger than the G level. Then, it is assumed that the AD conversion value of each signal is changed (decimal number) as in the (B) column. The column (C) represents the binary code that is actually output. So far, it is the same as the prior art.

As shown in the column (I) of FIG. 7, the delay circuit 54 and the subtraction circuit 55 in the color difference type encoding & code conversion circuit 24 generate color difference data having a different positive / negative code for each pixel clock by the differentiation process ( Difference processing). As a result, as a difference data string D2 having a color difference with a different sign for each pixel clock,
(100, -100, 100, -102, 101, -99, 100, ...)
Is obtained. This is one kind of color difference data, although the positive and negative signs differ for each pixel clock.

Next, as shown in the column (J) of FIG. 7, the positive / negative sign inversion circuit 53 inverts the positive / negative sign for every other data with respect to the difference data string D2 having a different color sign for each pixel clock. Color difference binary data with the same code is generated (data inversion processing). As a result, as a sign-reversed data string D3 of color differences with positive and negative signs aligned,
(100, 100, 100, 102, 101, 99, 100, ...)
Is obtained. This is a single continuous color difference data sequence with positive and negative signs. The column (K) in FIG. 7 shows the code-inverted data string D3 of color differences with the positive and negative signs aligned in binary code. Here, in the binary code in the column (K) of FIG. 7, although the description has been omitted so far, it is shown that 0 data insertion is performed by the 0 data insertion circuit 51.

Next, as shown in the (L) column of FIG. 7, the binary-Gray code conversion circuit 42 performs binary-Gray code conversion on the sign-inverted data string D3 of the color difference with the positive and negative signs aligned. As a result, a data string D4 of a code having a small number of bits that change at the time of switching, which is the number of bits that change when each code switches to the next code, is obtained. This zero data insertion is also effective in FIGS. 7A to 7J, but the description is omitted to avoid complication.
1185943682562_2
To express. this is,
1185943682562_3
1185943682562_4
This corresponds to the result of comparing adjacent codes in the (L) column. The number of change bits at the time of switching in the (M) column in FIG. 7 of this operation example is compared with the number of change bits at the time of switching in the (H) column of FIG. In this operation example, it can be seen that the same effect as the conventional technique is exhibited. Incidentally, the total value of the number of change bits at the time of switching (4, 0, 0, 2, 1, 2, 1) in this operation example is “10”, and the number of change bits at the time of switching in the case of the prior art (4 , 4, 0, 2, 1, 1, 1) is “13”, and a slight improvement is recognized.

(2) Explanation of operation example of FIG. 8 On the other hand, FIG.
(200, 100, 207, 100, 212, 101, 209, 100, ...)
It is an operation example in the case of The image is assumed to have a gradation change while being a single color of red. This is different from the red color single-level color data in the case of FIG.

As shown in the column (I) of FIG. 8, the delay circuit 54 and the subtraction circuit 55 generate color difference data having a different positive / negative sign for each pixel clock by the differentiation process (differentiation process). As a result, as a difference data string D2 having a color difference with a different sign for each pixel clock,
(100, -107, 107, -112, 111, -108, 109, ...)
Is obtained.

Next, as shown in the column (J) of FIG. 8, the positive / negative sign inversion circuit 53 inverts the positive / negative sign for every other data with respect to the difference data string D2 having a different color sign for each pixel clock. Color difference binary data with the same code is generated (data inversion processing). As a result, as a sign-reversed data string D3 of color differences with positive and negative signs aligned,
(100, 107, 107, 112, 111, 108, 100, ...)
Is obtained. The (K) column in FIG. 8 shows the binary code display of the color-inverted data sequence D3 having the same positive and negative signs. Here, the binary code in the column (K) in FIG. 8 indicates that 0 data is inserted.

Looking at the binary code of the sign-inverted data string D3 of the color difference in which the positive and negative signs are aligned in the column (K) of FIG. 8, the number of change bits at the time of switching between adjacent pixels is
(3,4,0,4,5,2,1, ...)
It has changed as follows. This is the transition in the case of column (K) in FIG.
(3,0,0,1,2,2,1, ...)
8 is clearly larger than FIG. This is because, in a natural image, the condition changes when an image having a single color but having a gradation change is captured. In such a case, as already described in the section [Problems to be solved by the invention], when the change between the difference values becomes large, even if the Gray code conversion is used as the code conversion, the switching by the Gray code is performed. The number of time-varying bits is not reduced, and the noise reduction effect is reduced. The point is whether this inconvenience is eliminated in the present embodiment (hereinafter, described).

Next, as shown in the (L) column of FIG. 8, the binary-Gray code conversion circuit 42 performs binary-Gray code conversion on the sign-inverted data string D3 of the color difference with the positive and negative signs aligned. As a result, a data string D4 of a code having a small number of bits that change at the time of switching, which is the number of bits that change when each code switches to the next code, is obtained.
1185943682562_5
To express. this is,
1185943682562_6
1185943682562_7
This corresponds to the result of comparing adjacent codes in the (L) column. The number of change bits at the time of switching in the (M) column in FIG. 8 of this operation example is compared with the number of change bits at the time of switching in the (H) column of FIG. In this operation example, it can be seen that an effect superior to that of the prior art is exhibited (comparable to the case of FIG. 7). Incidentally, the total value of the number of change bits at the time of switching (4, 1, 0, 3, 1, 1, 1) in the case of this operation example is “11”, and the number of change bits at the time of switching in the case of the prior art (4 , 3, 1, 3, 2, 2, 2) is “17”, and a significant improvement is recognized.

  As described above, according to the color difference type encoding & code converting circuit 24 of the present embodiment, after taking the data difference between the two colors, the positive and negative signs are combined, and then converted to the gray code. Even if the colors are different, the difference between the color difference signals is not so large, so in image data with natural gradation, the number of bits that change at the time of switching from one code to the next is less than in the prior art. Can be eliminated.

  In the above, the color difference type encoding & code conversion circuit 24 in the analog front-end device 20 of FIG. 1 has been described. Hereinafter, the color difference data decoding circuit 31 in the DSP 30 of FIG. 1 will be described. The DSP 30 receives the image data output from the analog front end device 20 and performs decoding processing and other data processing. The color difference data decoding circuit 31 is provided for the decoding process, but it is necessary to perform a reverse process to the process performed by the color difference type encoding & code conversion circuit 24 and restore the data correctly.

  FIG. 10 is a block diagram showing a detailed configuration of the color difference data decoding circuit 31 in the first embodiment. In FIG. 10, reference numeral 61 denotes a code reverse conversion circuit (gray-binary code conversion circuit) that receives gray code converted image data from the analog front end device 20 and reversely converts it into the original binary code, and 62 denotes one pixel. A positive / negative sign inversion restoration circuit for inverting the sign of the color difference data every other, and 63 is a subtraction / accumulation circuit for performing a subtraction / accumulation process for decoding the original two types of color data from the color difference data with the positive / negative sign inverted every other pixel. . The color difference data decoding circuit 31 includes a code reverse conversion circuit (gray-binary code conversion circuit) 61, a positive / negative sign inversion restoration circuit 62, and a subtraction accumulation circuit 63.

  Reference numeral 75 denotes a subtraction circuit for inputting the output data of the positive / negative sign inversion restoration circuit 62 and a delay circuit for delaying the calculation result by the 76 subtraction circuit 75. The operation result data delayed by the delay circuit 76 is connected as the cumulative input of the subtraction circuit 75, and the delay circuit 76 performs delay processing of one pixel clock when the data data changes in color information every other pixel. It is configured.

  FIG. 11 is a block diagram showing a more detailed configuration of the color difference data decoding circuit 31. The positive / negative sign inversion restoration circuit 62 includes an amplifier 71 having a gain coefficient of minus 1, a selector 72, and a divide-by-2 circuit 73. The subtraction / accumulation circuit 63 includes a reset circuit 74, a subtraction circuit 75, and a delay circuit 76. The gray-binary code conversion circuit 61 converts the gray code shown on the right side in FIG. 9 into the binary code shown on the left side.

  FIG. 11B is an operation explanatory diagram of the color difference data decoding circuit 31. Here, an outline of the operation will be described.

  First, in the gray-binary code conversion circuit 61, the data string D4 of the code having a small number of change bits at the time of switching input from the parallel data output circuit 25 of the analog front-end device 20 is converted into the data string D0 of the original binary code. To do. In this data string D0, the 0 data inserted by the 0 data insertion circuit 51 is removed.

  FIG. 12 is a circuit diagram showing a specific configuration of the gray-binary code conversion circuit 61. The gray-binary code conversion circuit 61 includes a plurality of exclusive OR gates. The number of exclusive OR gates is one less than the number of bits of the code to be converted. Here, as an example, if the number of bits of the code to be converted is 8 bits, seven exclusive OR gates G11 to G17 are used.

The most significant 8th bit d7 'is output as it is as the converted 8th bit d7 and also input to the exclusive OR gate G17. The exclusive OR gate G17 takes an exclusive OR of the seventh bit d6 'and the eighth bit d7' and outputs the result as the converted seventh bit d6. The exclusive OR gate G16 takes an exclusive OR of the sixth bit d5 'and the seventh bit d6 which is the output of the exclusive OR gate G17, and outputs the result as the converted seventh bit d6. Similarly, the exclusive OR gate G12 takes an exclusive OR of the second bit d1 'and the third bit d2 which is the output of the exclusive OR gate G13, and outputs it as the converted second bit d1. To do. The exclusive OR gate G11 takes an exclusive OR of the first bit d0 'and the second bit d1 which is the output of the exclusive OR gate G12, and outputs it as the converted first bit d0.
Thus, the original binary code is restored.

  FIG. 12 shows an example of converting an 8-bit gray code into a binary code. Besides this, a gray-binary code conversion circuit having an arbitrary number of bits such as 10 bits or 12 bits can be configured in the same manner. it can.

  FIG. 13 shows the operation outline of FIG. 11B in detail in time series. FIG. 13A illustrates the operation by the gray-binary code conversion circuit 61, FIG. 13B illustrates the operation by the positive / negative sign inversion restoration circuit 62, and FIG. 13C illustrates the operation by the subtraction accumulation circuit 63.

First, the operation of the gray-binary code conversion circuit 61 will be described with reference to FIG. The gray-binary code conversion circuit 61 converts the code data string D4 having a small number of change bits at the time of switching, which is input from the parallel data output circuit 25, into a code-inverted data string D3 having a color difference with positive and negative signs. The sign-inverted data string D3 is
D3: a1-0, a1-b1, a2-b1, a2-b2, a3-b2, a3-b3, a4-b3, a4-b4 ...
It becomes. .

Next, the operation of the positive / negative sign inversion restoration circuit 62 will be described with reference to FIG. The positive / negative sign inversion restoration circuit 62 converts the color-inverted sign-inverted data string D3 having the same positive / negative sign into a difference data string D2 having a different positive / negative sign for each pixel clock. The sign-inverted data string D3 having the color difference with the positive and negative signs aligned is input to the “H” selection input terminal of the selector 72. Further, an inverted data string D3 ′ = − D3 obtained by inverting the sign-inverted data string D3 of color differences with the same positive / negative sign inverted by the amplifier 71 having a gain coefficient of minus 1 is input to the “L” selection input terminal of the selector 72. The selector 72 alternately selects the “L” selection side and the “H” selection side for each clock cycle by the selection control signal from the divide-by-2 circuit 73. As a result, the data string D2 output from the positive / negative sign inversion restoration circuit 62 is:
D2: 0-a1, a1-b1, b1-a2, a2-b2, b2-a3, a3-b3, b3-a4, a4-b4 ...
It becomes. This is a color difference data string having a different sign for every pixel clock.

Next, the operation of the subtraction accumulation circuit 63 will be described with reference to FIG. In the subtraction accumulating circuit 63, the subtraction circuit 75 inverts the difference data string D2 having a color difference with a different sign for each pixel clock. that is,
It becomes. When this is delayed by one pixel clock in the delay circuit 76,
D2 ″: a1-0, b1-a1, a2-b1, b2-a2, a3-b2, b3-a3, a4-b3, b4-a4.
In the subtraction circuit 75, an operation of D2 ″ −D2 is performed, and as a data string D0,
D0: a1, b1, a2, b2, a3, b3, a4, b4 ...
Is obtained. This is the original data string D0 in a state in which 0 data of 0 data insertion is removed. The reset circuit 74 is necessary for the processing start timing, and as a result, removes the 0 data previously inserted. In the data string D0, two types of color data are alternately repeated.

  Note that the position where the output data is extracted from the subtraction accumulation circuit 63 used in the decoding process may be on the output side of the delay circuit 76.

(Embodiment 2)
FIG. 14 is a block diagram showing a detailed configuration of the color difference type encoding & code conversion circuit 24 in the semiconductor integrated circuit according to the second embodiment of the present invention, and FIG. 15 shows a detailed configuration of the color difference data decoding circuit 31 in the second embodiment. FIG. In FIG. 14, the same reference numerals as in FIG. 3 of the first embodiment indicate the same components. In FIG. 15, the same reference numerals as those in FIG. 11 of the first embodiment indicate the same components. In addition, the configuration unique to this embodiment is as follows.

  In FIG. 14, 43 is a one-shot trigger circuit that generates a reset signal by a data enable signal, 44 is an enable code addition circuit that is inserted between the selector 57 and the binary-gray code conversion circuit 42 and controlled by the data enable signal. It is. The one-shot trigger circuit 46 generates a reset signal from the data enable signal and supplies the generated reset signal to the divide-by-2 circuit 58. The enable code adding circuit 44 adds an enable code at the input timing of the data enable signal and sends it to the binary-gray code conversion circuit 42.

  In FIG. 15, reference numeral 64 denotes an enable code decoding circuit connected to the subsequent stage of the gray-binary code conversion circuit 61. The enable code decoded by the gray-binary code conversion circuit 61 is converted into a binary code and decoded. The code is supplied to the divide-by-2 circuit 73 and the reset circuit 74.

  According to the present embodiment, since the enable code is used, the above-described specific function can be started to be exhibited at an arbitrary timing by using the decoded enable code as the reference timing for starting the decoding process.

  Other configurations and operations are the same as those in the first embodiment, and thus description thereof is omitted.

  The technique of the present invention is useful as a technique for improving image quality by suppressing the wraparound of power supply noise when digital output data is transmitted in an imaging system, a semiconductor integrated circuit for the imaging system, and the like.

1 is a block diagram showing a schematic configuration of an imaging system according to Embodiment 1 of the present invention. 1 is a block diagram showing a detailed configuration of a color difference type encoding & code converting circuit according to Embodiment 1 of the present invention. The block diagram and operation | movement outline | summary figure which show the further detailed structure of the color difference type encoding & code conversion circuit in Embodiment 1 of this invention Explanatory drawing of Bayer arrangement in Embodiment 1 of the present invention Detailed operation explanatory diagram of the color difference type encoding & code conversion circuit in the first embodiment of the present invention 1 is a circuit diagram showing a specific configuration of a binary-gray code conversion circuit according to a first embodiment of the present invention. Explanatory drawing of the concrete operation | movement by the color difference type encoding & code conversion circuit in Embodiment 1 of this invention (the 1) Explanatory drawing of the concrete operation | movement by the color difference type encoding & code conversion circuit in Embodiment 1 of this invention (the 2) The figure which shows the conversion table of the decimal number, binary code, and Gray code in Embodiment 1 of this invention 1 is a block diagram showing a detailed configuration of a color difference data decoding circuit according to Embodiment 1 of the present invention. 1 is a block diagram showing a more detailed configuration of a color difference data decoding circuit according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a specific configuration of a gray-binary code conversion circuit according to a first embodiment of the present invention. Detailed operation explanatory diagram of the color difference data decoding circuit according to the first embodiment of the present invention. The block diagram which shows the detailed structure of the color difference type encoding & code conversion circuit in Embodiment 2 of this invention The block diagram which shows the detailed structure of the color difference data decoding circuit in Embodiment 2 of this invention. A block diagram showing a schematic configuration of an AD conversion LSI used in an imaging system in the prior art Block diagram showing the configuration of an encoding & code conversion circuit in the prior art Explanatory drawing of concrete operation | movement by the encoding & code conversion circuit in a prior art (the 1) Explanatory drawing of the concrete operation | movement by the encoding & code conversion circuit in a prior art (the 2) The block diagram which shows the structure of the code reverse conversion circuit in a prior art The figure explaining the problem of the conventional imaging system (electronic still camera and video camera) solved by conventional technology

Explanation of symbols

10 Image sensor (image sensor)
20 Analog front-end device (AD conversion LSI; first semiconductor integrated circuit)
21 Correlated Double Sampling Circuit (CDS)
22 Amplifier circuit (programmable gain amplifier)
23 AD converter circuit (ADC)
24 Color difference type encoding & code conversion circuit 25 Parallel data output circuit 30 Digital signal processor (DSP; second semiconductor integrated circuit)
31 Color Difference Data Decoding Circuit 32 Image Processing Circuit 41 Adjacent Color Difference Data Generation Circuit 42 Code Conversion Circuit (Binary-Gray Code Conversion Circuit)
43 One-shot trigger circuit 44 Enable code addition circuit 51 0 Data insertion circuit 52 Color difference type difference circuit 53 Positive / negative sign inversion circuit 54 Delay circuit 55 Subtraction circuit 56 Amplifier with gain coefficient minus 1 57 Selector 58 Divider circuit 61 Code reverse conversion Circuit (Gray-binary code conversion circuit)
62 Positive / negative sign inversion restoration circuit 63 Subtraction accumulation circuit 64 Enable code decoding circuit 71 Amplifier with gain coefficient minus 1 72 Selector 73 Divide-by-2 circuit 74 Reset circuit 75 Subtraction circuit 76 Delay circuit

Claims (16)

An amplifier circuit for amplifying an analog color video signal input from the image sensor;
An AD converter circuit for converting the video signal amplified by the amplifier circuit into a digital signal;
Adjacent color difference data generating means for generating color difference data by taking a difference between adjacent data in a data string having different color information for each pixel after AD conversion by the AD conversion circuit;
A semiconductor integrated circuit comprising: code conversion means for converting a color difference data code generated by the adjacent color difference data generation means into a code having a small number of change bits when switching between the preceding and succeeding codes. The adjacent color difference data generating means includes
A color difference type differentiating unit that calculates a difference between adjacent data in a data string having different color information for each pixel after AD conversion by the AD conversion circuit, and generates color difference data having a different sign for each pixel clock;
Positive / negative sign inverting means for inverting color signs for every other data with respect to color difference data having a different positive / negative sign for each pixel clock generated by the color difference type differentiating means, and generating color difference data with uniform positive / negative signs. The semiconductor integrated circuit according to claim 1, which is configured.   The color difference type differentiating means includes a delay circuit that delays input data from the AD converter circuit, and a subtractor circuit that calculates a difference between the data delayed by the delay circuit and the input data, and the delay circuit 2. The semiconductor integrated circuit according to claim 1, wherein a delay process of one pixel clock is performed for data in which color information changes every other pixel.   The positive / negative sign inversion means fixes the phase of the chrominance data whose sign is inverted for each data from the chrominance type differentiating means with reference to an arbitrary phase position temporally forward in the horizontal direction of the effective data. 4. The semiconductor integrated circuit according to claim 2, wherein the pixel clock is configured to invert the sign of the color difference data every other data by dividing the pixel clock by two.   The positive / negative sign inversion means fixes the phase with respect to color difference data in which the positive / negative sign is inverted for each data from the color difference type differentiating means with respect to an arbitrary phase position temporally forward in the vertical direction of the effective data. 4. The semiconductor integrated circuit according to claim 2, wherein the pixel clock is configured to invert the sign of the color difference data every other data by dividing the pixel clock by two.   6. The adjacent color difference data generation means includes a zero data insertion means for inserting zero data in a preceding data portion of valid data before the color difference type differentiation means. A semiconductor integrated circuit according to 1.   7. The semiconductor integrated circuit according to claim 1, wherein the code conversion means is a binary-gray code conversion circuit that converts an input binary code into a gray code.   The semiconductor integrated circuit according to claim 1 is included in a component as a first semiconductor integrated circuit, and a code output from the first semiconductor integrated circuit is further input to input the original An imaging system comprising: color difference data decoding means for decoding and converting to a binary code; and a second semiconductor integrated circuit comprising an image processing circuit for the binary code output from the color difference data decoding means.   The color difference data decoding means receives the color difference data output from the first semiconductor integrated circuit and decodes and converts it into an original binary code (decoding process); and the output of the code inverse conversion means Positive / negative sign inversion restoration means for inverting and restoring the positive / negative sign every other data with respect to the color difference data having the same positive / negative sign, and generating chrominance data in which the positive / negative sign is inverted for each data, and the positive / negative code is inverted for each data The imaging system according to claim 8, further comprising subtracting and accumulating means for sequentially accumulating the difference between adjacent data of the color difference data to be obtained.   The positive / negative sign inversion restoring means sets the reference phase position temporally forward in the horizontal direction of the same effective data as that of the first code conversion for color difference data having positive / negative signs aligned at the output of the code reverse conversion means. By using a pixel clock whose phase is fixed as a reference, and by dividing the pixel clock by two, the sign of the chrominance data is inverted and restored every other data, and the chrominance data in which the sign of each data is inverted is generated. The imaging system according to claim 9, wherein the imaging system is configured to.   The positive / negative sign inversion restoration means sets a reference phase position temporally forward in the vertical direction of the same effective data as in the first code conversion for color difference data having positive and negative signs aligned at the output of the code reverse conversion means. By using a pixel clock whose phase is fixed as a reference, and by dividing the pixel clock by two, the sign of the chrominance data is inverted and restored every other data, and the chrominance data in which the sign of each data is inverted is generated. The imaging system according to claim 9, wherein the imaging system is configured to.   The subtracting and accumulating means is composed of a subtracting circuit for inputting the output data of the positive / negative sign inversion restoring means and a delay circuit for delaying the operation result by the subtracting circuit, and the operation result data delayed by the delay circuit is the 12. The delay circuit is connected as a cumulative input of a subtraction circuit, and the delay circuit is configured to perform a delay process of one pixel clock when the data data changes in color information every other pixel. The imaging system according to any one of the above.   The imaging system according to claim 9, wherein the subtracting and accumulating unit includes a reset unit that inserts initial zero data.   An enable code adding circuit for adding an enable code indicating a reference timing at an arbitrary timing is provided at a preceding stage of the code converting means, and an enable code decoding circuit for decoding the enable code is provided at a subsequent stage of the code inverse converting means. The imaging system according to any one of claims 8 to 13, wherein the enable code decoded by the code decoding circuit is used as a reference timing for starting the decoding process.   15. The imaging system according to claim 9, wherein the code reverse conversion unit is a gray-binary code conversion circuit that converts an input gray code into a binary code. A signal conversion method for converting an analog color video signal input from an image sensor into a digital signal,
AD converting the video signal;
A step of performing difference processing with adjacent data in the same direction while shifting the target pixel in one dimension with respect to data having different color information for each pixel;
Generating color difference data having different one-dimensional positive and negative signs;
A step of inverting the sign of the color difference data every other data with respect to a reference position for color difference data having a different positive / negative sign for each data to obtain color difference data with a positive / negative code aligned;
Converting the color difference data with the positive and negative signs into a code with little change in adjacent data.

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