JP2005175545A - Semiconductor integrated circuit, imaging system and signal conversion method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for multiplexing a signal read from an imaging device and AD-converted and applying differential coding and code conversion to the signal, and to provide an imaging system and a signal converting method enabling efficient noise reduction, in an imaging apparatus for improving a signal reading speed of the imaging device to minimally several times by reading signals in parallel from the imaging device having a plurality of signal output terminals. <P>SOLUTION: An LSI 20 for AD conversion consists of gain variable programmable gain amplifiers (PGA) 22a, 22b for amplifying a sampled signal; AD conversion circuits (ADC) 23a, 23b for converting the amplified analog signal into a digital signal; a multiplexing circuit 24 for multiplexing the AD-converted digital image data; a coding and code conversion circuit 25 for applying differential coding to the multiplexed signal and further converting it into a gray code; and an output buffer 26 for outputting the code-converted signal to the outside of a chip from an output terminal OUT. The above problem is solved by the LSI 20. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a noise reduction technique in an imaging system using an imaging device such as a charge coupled device (CCD) or a CMOS, and a technique to reduce noise caused by transmission of digital image data using a code conversion method. In particular, the present invention relates to applying such a noise reduction technique to an image sensor that can simultaneously obtain a plurality of output signals in parallel.

  The cause of noise appearing on the display screen in the imaging system is disclosed as described in Patent Document 1. That is, as shown in FIG. 17, the power supply noise generated when the AD conversion LSI 20 outputs image data to transmit the AD converted image data to the DSP 30 is caused by the power supply lines (Vcc line and ground) on the printed circuit board. Line) to enter the video signal input to the AD conversion LSI, or from the output circuit side to the input terminal side through the power line or semiconductor substrate inside the AD conversion LSI. It is described that it is the cause.

  Originally, an LSI output circuit needs to drive a larger load than the inside of a chip such as an external printed wiring, so the output element is also larger in size (10 times) than the elements constituting the internal circuit such as an AD converter circuit. The above is generally used and is designed so that a relatively large amount of current flows. It is considered that a large through current flows when the output signal is switched and noise is applied to the power supply. Noise generated in the output circuit propagates through the substrate to internal circuits other than the input circuit. However, the AD conversion LSI has an amplifier circuit such as a PGA (programmable gain amplifier) that amplifies the input analog signal. The noise propagated to the input side is also amplified together with the video signal, leading to a decrease in display image quality.

Therefore, as shown in FIG. 18, after the digital image data subjected to AD conversion is differentially encoded before it is output, it is converted into a gray code or subjected to predetermined code conversion such as adding a fixed value, and then from the LSI. Output it. More specifically, after the analog color video signal output from the image sensor is AD-converted by the AD converter circuit, the difference between adjacent pixel codes related to the same color after conversion is obtained, and the differentiated output code is obtained. The code is switched between the preceding and succeeding codes and converted into a code with a small number of bits. By performing such code conversion, the number of bits that change when the output digital signal switches is reduced, thereby reducing the through current in the output circuit and reducing the noise accompanying the change in output. .
JP 2002-300591 A

  However, when the conventional noise reduction technology as described above is applied to a system including an image sensor that can obtain a plurality of outputs in parallel, a plurality of differentiating circuits and code conversion circuits after the AD conversion circuit are required, which is economical. There was a problem that it was not right.

  In addition, when differential encoding and code conversion are performed for each signal, there is a problem that the noise reduction effect becomes weak because of the large number of output terminals.

  The present invention has been made to solve such problems, and apparently improves the signal reading speed of the image sensor several times by reading signals in parallel from the image sensor having a plurality of signal output terminals. In addition to providing a semiconductor integrated circuit that multiplexes signals that have been read out from an image sensor and subjected to AD conversion, and then differential encoding and code conversion, an imaging system and signal that enable effective noise reduction An object is to provide a conversion method.

  In order to solve the above problems, a semiconductor integrated circuit according to claim 1 of the present invention includes a plurality of amplifier circuits for amplifying a plurality of analog color video signals output from an image sensor, and the amplified signals as digital signals. A plurality of AD conversion circuits for conversion, a multiplexing means for multiplexing a plurality of digital signals after AD conversion, and a differentiation means for taking a difference between codes of adjacent pixels related to the same color of the multiplexed signal; Code conversion means for code-converting the output of the differentiating means.

  The code conversion means is preferably a binary-gray code conversion circuit that converts an input binary code into a gray code, or a circuit that adds or subtracts a fixed value to the input code.

  The differentiating means is composed of a delay circuit for delaying the output code of the multiplexing means, and a subtracting means for taking the difference between the code delayed by the delay circuit and the input code. The delay time may be configured to be variable according to the color arrangement of the video signal.

  Furthermore, the imaging system according to claim 4 is provided with a color filter and capable of simultaneously obtaining a plurality of output signals, and a plurality of analog color video signals output from the imaging element. An amplification circuit, a plurality of AD conversion circuits for converting the amplified signals into digital signals, a multiplexing means for multiplexing the plurality of digital signals after AD conversion, and adjacent pixels related to the same color of the multiplexed signals A semiconductor integrated circuit comprising a differentiating means for taking a difference between the codes and a first code converting means for code-converting the output of the differentiating means, and a second for converting a code output from the semiconductor integrated circuit. It has a code conversion means and an image processing circuit, and an image processing semiconductor integrated circuit.

  In the imaging system, the first code conversion means is a binary-gray code conversion circuit that converts binary code into gray code, and the second code conversion means is a gray-binary code conversion circuit that converts gray code into binary code. Is desirable.

  The first code conversion means of the imaging system may be configured as a circuit for adding or subtracting a fixed value to the input code, and the second code conversion means may be configured as a circuit for subtracting or adding a fixed value from the input code.

  Further, the differentiating means of the imaging system comprises a delay circuit that delays the output code of the multiplexing means, and a subtracting means that takes the difference between the code delayed by the delay circuit and the input code. The delay time may be variable according to the color arrangement of the video signal.

  Furthermore, in the signal conversion method according to claim 9, after the video signal is AD converted by the AD conversion circuit, a plurality of digital signals are multiplexed, and a difference between codes of adjacent pixels related to the same color after multiplexing is calculated. Therefore, the difference output code is converted into a code with a small number of bits that can be switched between the preceding and succeeding codes.

  According to the present invention, as described above, the present invention provides a difference by multiplexing n signals output from n AD converter circuits (ADC) by multiplexing means to be combined into one signal. The circuit and the code conversion circuit can be saved, and the output terminal of the LSI is reduced to 1 / n, so that there is an effect that it is economical and the amount of noise can be reduced.

  Also, since the difference between adjacent pixels of the same color can be obtained by multiplexing with the multiplexing means, the change in the output data as a result of the differential encoding is reduced compared to the case of differential encoding in parallel, Compared with the case of differential encoding in parallel, the noise suppression effect is high.

BEST MODE FOR CARRYING OUT THE INVENTION

  Examples of the present invention will be described below.

  Preferred embodiments of the present invention will be described below with reference to the drawings. 2 shows the configuration of the color filter of the image sensor used in the imaging system to which the present invention is applied, and FIG. 3 shows the state of the readout signal.

  In this embodiment, as shown in FIG. 2, Gr and R or B and Gb are alternately arranged for each horizontal line, and the two output terminals are read from OUT13 in the order of Gr1 → Gr3 → Gr5. Then, the data is read from OUT24 in the order of R2 → R4 → R6.

  FIG. 1 shows a schematic configuration example of an AD conversion LSI used in an imaging system to which the present invention is applied.

  The AD conversion LSI 20 according to the first embodiment includes correlated double sampling circuits (CDS) 21a and 21b that sample an analog video signal output from the CMOS 10 and input to an input terminal, and a variable gain that amplifies the sampled signal. Programmable gain amplifiers (PGA) 22a and 22b, AD conversion circuits (ADC) 23a and 23b that convert the amplified analog signals into digital signals, a multiplexing circuit 24 that multiplexes the AD converted digital image data, It comprises an encoding and code conversion circuit 25 that differentially encodes a multiplexed signal and converts it into a Gray code, and an output buffer 26 that outputs the code-converted signal to the outside of the chip from an output terminal OUT.

  The circuit provided in the AD conversion LSI 20 of the first embodiment is not limited to that shown in FIG. 1 and is not shown, but the amplifier (PGA) is included in the LSI chip. A control circuit for generating a signal for controlling the gain of 22a and 22b and controlling the operation of the entire chip; a clock signal for giving sampling timing to the CDS 21a and 21b; and AD conversion circuits 23a and 23b and a multiplexing circuit 24; A clock generation circuit that generates a clock signal necessary for the operation of the encoding and code conversion circuit 25 or a clock buffer that distributes an externally supplied clock signal to circuits inside the chip is provided.

  In the first embodiment, by providing the encoding and code conversion circuit 25, the through current in the output buffer 26 can be reduced and the noise can be reduced as will be described later. In this case, it is desirable to connect a pass capacitor to the power supply terminal of the chip. However, by applying the present invention, a pass capacitor having a small capacitance value can be used, so that the mounting area can be reduced.

  FIG. 9 shows a schematic configuration of the encoding and code conversion circuit 25. As shown in FIG. 9, the encoding and code conversion circuit 25 includes a delay circuit 41 that delays the data output from the multiplexing circuit 24 by a predetermined clock period, and the data output from the multiplexing circuit 24 and the delay circuit. A differential encoding circuit 42 that takes a difference from the data delayed at 41 and a code conversion circuit 43 that converts binary data that has been differentially encoded into a gray code.

  The differential encoding circuit 42 is configured to truncate carry bits generated when the difference is taken. By truncating the carry bit, the number of bits of data before taking the difference becomes the same as the number of bits of data after taking the difference, and data handling becomes easy. In Table 1, taking the case of 2 bits as an example, the calculation result c (= ab) when the difference between the data (subtracted value a) and the data (subtracted value b) is taken and the carry is truncated, and the calculation A result d (= c + b) obtained by calculating the subtracted value a from the result c and the subtracted value b is shown. In the present embodiment, the generated carry bits are also discarded in addition performed at the time of differential decoding described later. Thereby, the bit number of the data before taking the difference and the bit number of the data after taking the difference become the same.

表１においては、第１列目のコード（ａ）と第４列目のコード（ｄ）とは一致している。このことより、差分符号化の際および差分復号化の際にそれぞれキャリーの切捨てを行なっても元のコードを正確に復元できることが分かる。なお、表１には２ビットのコードの例を示したが３ビット以上のコードにおいても同様にキャリーを切り捨てても再現性がある。

In Table 1, the code (a) in the first column matches the code (d) in the fourth column. From this, it can be seen that the original code can be accurately restored even if the carry is cut off at the time of differential encoding and differential decoding. Table 1 shows an example of a 2-bit code, but a 3-bit or more code is also reproducible even if the carry is cut off.

  For example, as shown in FIG. 7, the code conversion circuit 43 includes exclusive OR gates G <b> 1 to G <b> 7 that is one less than the number of bits of the code to be converted, and adjacent bits Di, Di + 1 ( An exclusive OR of i = 0 to 6) is output as the converted bit Di ′. The most significant bit D7 before conversion is output as it is as the most significant bit D7 'after conversion. FIG. 8 shows an example of a circuit for converting an 8-bit binary code into a Gray code as an example, and a code conversion circuit having an arbitrary number of bits such as 10 bits and 12 bits can be configured by a similar mechanism.

  Next, a specific procedure of the differential encoding process by the differential encoding circuit 42 and the binary gray code conversion by the code conversion circuit 43 will be described with reference to FIG. In this case, the delay amount in the delay circuit 41 of FIG. 9 is a delay of two clock cycles, that is, two clock cycles in the output of the multiplexing circuit 24. As shown in the column (A) of FIG. 11, the signal multiplexed by the multiplexing circuit 24 is converted into an R (red) signal and G (G (R) → R → Gr → R → Gr → R). Green) signals are alternately input.

  At this time, it is assumed that the value obtained by AD-converting each signal changes as a decimal number as shown in the column (B) of FIG. When this is expressed by the binary code that is actually output, it becomes as shown in FIG. This code is output as it is from a conventional AD conversion LSI that does not have the encoding & code conversion circuit 25. As is clear when adjacent codes in the column (C) of FIG. 12 are compared, the number of bits to be switched when each code changes to the next code is as shown in the column (D) of FIG.

  When the binary code as shown in FIG. 12C is input to the code conversion circuit 25 of the present embodiment, the value output from the differential encoding circuit 42 is expressed in decimal numbers as shown in FIG. In addition, the binary code is as shown in FIG. Here, the difference is the difference between the same colors of adjacent pixels, that is, every other value as indicated by an arrow in the column (B) of FIG. Then, when the differential binary code in FIG. 12F is converted into a gray code, the result is as shown in FIG.

  As is clear when adjacent codes in the column (G) in FIG. 12 are compared, the number of switching bits when each code changes to the next code is as shown in FIG. Comparing the (D) column and the (H) column in FIG. 12, it can be seen that the number of switching bits is significantly reduced in this embodiment compared to the conventional method.

  In the video signal, since there is little abrupt change between adjacent pixels, even if the code after AD conversion is immediately converted to a gray code, the amount of bit change is small between the same colors. In the present embodiment, the difference between the multiplexed code and the gray code is not immediately converted into the gray code, but the difference between adjacent pixels in the video signal is small. This is because the code difference between different colors of one pixel in the CMOS output through the filter of the color element array as described above is often relatively large (except in the case where the subject to be photographed is gray with little color change). The code difference between different colors is also reduced).

  However, if the difference is simply taken, it is expected that the difference will be positive and negative on one screen at almost the same rate, but in the binary code represented by 2's complement, the difference is positive. When changing from negative to negative, the code changes greatly from all “0” to all “1”, and when changing from negative to positive, the code greatly changes from all “1” to all “0”. Therefore, in this embodiment, the binary code is converted to the Gray code so that the code does not change greatly when changing from positive to negative or from negative to positive.

  Table 2 shows the relationship between the binary code represented by 2's complement and the Gray code, taking the case where the code is 3 bits as an example.

表２から分かるように、３ビットのバイナリコードでは１０進数の「０」から「−１」に変化するときに「０００」から「１１１」に変化する。４ビットや８ビット、あるいはそれ以上のビット数のコードでも同様にオール「０」からオール「１」に変化する。この場合、切り替わるビットは全ビット（３個）である。一方、グレイコードでは、例えば３ビットの場合には１０進数の「０」から「−１」に変化するときに「０００」から「１００」に変化するので、この場合、切り替わるビットはたった１ビットである。従って、出力バッファで出力が切り替わる際に流れる貫通電流もバイナリコードを出力する場合よりもグレイコードを出力する場合の方が大幅に少なくなる。

As can be seen from Table 2, the 3-bit binary code changes from “000” to “111” when the decimal number changes from “0” to “−1”. Similarly, a code having 4 bits, 8 bits, or more bits changes from all “0” to all “1”. In this case, all the bits (three) are switched. On the other hand, in the Gray code, for example, in the case of 3 bits, when the decimal number is changed from “0” to “−1”, the bit changes from “000” to “100”. It is. Therefore, the through current that flows when the output is switched in the output buffer is significantly less when the gray code is output than when the binary code is output.

  FIG. 13 shows, as an example, a result (A) of examining the code switching bit number after AD conversion according to the conventional method when a human palm is photographed by a CCD, and a gray scale after differential encoding by applying this embodiment. The result (B) of examining the number of switching bits when code conversion is performed is shown in a graph.

  From the figure, in the conventional method (A), the maximum number of code switching bits is “8” and the most frequently appearing bit number is “4”. The maximum number of switching bits is “6” and the most frequently appearing bit number is “2”. It can be seen that the number of switching bits is smaller in this embodiment than in the conventional method. If the number of bits to be switched is small, the through current flowing in the output buffer when outputting such a code can be reduced, and the power supply noise and the noise transmitted through the substrate can also be reduced.

  In the differential encoding and gray code conversion method shown in FIG. 9, four colors of Cy (cyan), Ye (yellow), Mg (magenta), and G (green) are used as shown in FIG. The present invention can also be applied to the case where an arrayed complementary color filter is used, or the case where a filter in which three primary colors R (red), G (green), and B (blue) are arranged in a horizontal row is used. Of these, even when a complementary color filter is used, the delay amount in the delay circuit 41 may be two clock cycles as in the above-described embodiment, provided that two types of color elements are alternately arranged in the same row.

  On the other hand, although not shown, when a three primary color filter in which three color elements are sequentially arranged in a horizontal row is used in the three primary color filter, the delay amount in the delay circuit 41 may be three clock cycles. Since the delay amount in the delay circuit 41 differs depending on the filter used in this way, the delay circuit 41 in the embodiment of FIG. 2 is configured with a variable delay circuit, and the delay amount (delay clock) is corresponding to this variable delay circuit. It is also possible to provide a register for designating the (cycle) and change the delay amount in the delay circuit 41 by rewriting the set value of this register.

(Example 2)
Next, a second embodiment of the present invention will be described. In the second embodiment, instead of converting into a gray code after differential encoding as in the first embodiment, a fixed value expressed by a binary code after differential encoding is added (subtraction is also possible). It is a thing. The code on the right side of Table 2 shows a code (hereinafter referred to as an offset binary code) when “5 (decimal code“ 101 ”)” is added as a fixed value after differential encoding.

  From Table 2, when “5” is added as a fixed value after differential encoding, the binary code changes from “101” to “100” when the decimal number changes from “0” to “−1”. In this case, it can be seen that the bit to be switched is only one bit. However, in this system, when the decimal number “2” is changed to “3”, it changes from “111” to “000”. In this case, the number of bits to be switched is three. However, depending on the input video signal, that is, the subject to be photographed, the amount of change in signal between adjacent pixels may fall within the range of “−1” to “+2” (video with a small brightness difference). In such a case, even if the second embodiment is applied, the number of bits that change when the output is switched can be reduced, and noise accompanying the change in output can be reduced.

  Table 2 shows the case where the code is 3 bits, but if the number of bits increases, the number of bits that change when the output data is switched is suppressed to 1 or less by appropriately selecting a fixed value to be added. The range of offset binary codes that can be made can be widened. Therefore, even if it is converted to the offset binary code after the differential encoding, the number of bits that change when the output digital signal is switched can be considerably reduced, but not as much as in the first embodiment. The through current in the output circuit can be reduced, and the noise accompanying the change in output can be reduced.

  FIG. 14 shows a schematic configuration of a DSP (digital signal processor) 30 which receives image data output from the AD conversion LSI and performs data processing. The DSP 30 of the second embodiment includes a gray-binary differential decoding circuit 31 that receives gray code-converted image data output from the AD conversion LSI 20, reversely converts the image data into the original binary code, and further performs differential decoding. An image processing circuit 32 that performs image processing such as color correction and image composition on the decoded image data, and the decoded image data is compressed and stored in the external memory 50 or read from the memory 50. It is composed of a compression / decompression circuit 33 that decompresses image data. As the memory 50, in addition to a volatile semiconductor memory such as a RAM, a nonvolatile memory such as a smart media or a compact flash (registered trademark) is used.

  Instead of compressing image data before image processing by the image processing circuit 32, the image data after image processing is compressed by the compression / decompression circuit 33 and stored in the external memory 50. It is also possible. In the second embodiment, the image data image-processed by the DSP 30 is output to the external DA converter circuit 60 and converted into an analog signal, which is supplied to the display 80 through the filter 70 for display. . The DSP 30 in FIG. 14 is represented by functional blocks. In actual hardware, for example, an arithmetic unit such as a multiplier or an adder, a register for holding data, and these are operated in a predetermined order according to the processing content. It consists of a control circuit.

  FIG. 15 shows the configuration of the gray-binary differential decoding circuit 31 provided in the DSP 30. For example, when the data is 3 bits, the gray-binary differential decoding circuit 31 converts a gray code as shown in the third column of Table 2 into a binary code as shown in the second column. A binary conversion circuit 311, a delay circuit 312 that delays the code signal by a predetermined clock period corresponding to the delay in the delay circuit 41 shown in FIG. 9, and a code converted by the gray-binary conversion circuit 311 An adder circuit 313 that generates differentially decoded data by adding the codes delayed by the delay circuit 312. Note that the adder circuit 313 is configured to discard the carry generated during the addition. As described above with reference to Table 1, the original code can be accurately restored even if the carry is cut off during differential decoding.

  FIG. 16 shows a specific configuration example of the gray-binary conversion circuit 311. As shown in the figure, the gray-binary conversion circuit 311 is composed of exclusive OR gates G11 to G17, which is one less than the number of bits of the code to be converted, and each input bit except the most significant bit. Di 'is converted into a binary code by taking an exclusive OR of Di' and the converted bit (output of the exclusive OR gate) Di + 1 on the one higher-order bit side. The most significant bit D7 'is output as it is as the most significant bit D7 after conversion. FIG. 16 shows an example of a circuit for converting an 8-bit gray code into a binary code corresponding to FIG. 10, and a code conversion circuit having an arbitrary number of bits, such as 10 bits and 12 bits, by a similar mechanism. Can be configured.

FIGS. 15 and 16 show examples of conversion circuits in the case where the sent code is a gray code, and the sent code is an offset binary code as shown in the fourth column of Table 2. In some cases, a circuit that performs a process of subtracting (or adding) a fixed value from the input code.
(Example 3)
Next, a third embodiment of the present invention will be described.

  FIG. 5 shows the configuration of the color filter of the image sensor used in the imaging system of the present embodiment and the state of the readout signal. In this embodiment, four signals are read from the CMOS 210 in parallel.

  As shown in FIG. 5, Gr and R or B and Gb are alternately arranged for each horizontal line. Out of the four output terminals, Gr1 → Gr5 → Gr9 from OUT15 and Gr3 → Gr7 → Gr11 from OUT37. Are read from OUT26 in the order of R2 → R6 → R10, and from OUT48 in the order of R4 → R8 → R12.

  As shown in FIG. 4, the AD conversion LSI 120 according to the third embodiment includes correlated double sampling circuits (CDS) 121a, 121b, 121c, which sample four analog video signals output from the CMOS 110 and input to the input terminals. , 121d, variable gain programmable gain amplifiers (PGA) 122a, 122b, 122c, and 122d that amplify the sampled signal, and AD conversion circuits (ADC) 123a, 123b that convert the amplified analog signal into a digital signal , 123c, and 123d, a multiplexing circuit 124 that multiplexes the AD-converted digital image data, an encoding & code conversion circuit 125 that differentially encodes the multiplexed signal and converts it into a Gray code, Transformed signal And an output buffer 126 to be output to the outside of the chip from an output terminal OUT. The operation after multiplexing by the multiplexing circuit 124 is the same as in the first embodiment.

  By multiplexing the four signals output from the AD conversion circuits (ADC) 123a, 123b, 123c, and 123d by the multiplexing circuit 24 and combining them into one signal, the difference circuit and the code conversion circuit are divided into four parts. 1 and the output terminal of the LSI is reduced to a quarter, so that there are advantages that it is economical and the amount of noise generated can be reduced.

  Furthermore, the first purpose of multiplexing by the multiplexing circuit 124 is to obtain a difference between pixels having the strongest correlation. In other words, considering the case where no multiplexing is performed, since the data to be continuously output in each of the four outputs is the same color but spatially adjacent to the same color pixel, the value when the difference is taken is the adjacent same color pixel. It will be bigger than before. However, since the difference between adjacent pixels of the same color can be obtained by multiplexing as in the first embodiment, the change in the output data is less than that in the case of differential encoding in parallel as a result of the differential encoding. Become.

  The circuits provided in the AD conversion LSI 120 of the third embodiment are not all shown in FIG. 4 and are not shown, but the amplifiers (PGA) 122a and 122b are not shown in this LSI chip. , 122c and 122d, a control circuit that generates a signal for controlling the gain of the entire chip, controls the operation of the entire chip, a clock signal that gives sampling timing to the CDS 121a, 121b, 121c, and 121d, and an AD conversion circuit 123a, 123b, 123c, and 123d, and further, a clock generation circuit that generates clock signals necessary for the operation of the multiplexing circuit 124 and the encoding & code conversion circuit 125, or a clock signal supplied from the outside is distributed to circuits inside the chip. A clock buffer or the like is provided.

  Further, in the third embodiment, by providing the encoding and code conversion circuit 125, the through current in the output buffer 126 can be reduced and noise can be reduced as will be described later. In this case, it is desirable to connect a pass capacitor to the power supply terminal of the chip. However, by applying the present invention, a pass capacitor having a small capacitance value can be used, so that the mounting area can be reduced.

  The configuration and principle of the encoding and code conversion circuit 125 are the same as the method of converting a binary code into a gray code as described in the first and second embodiments or the method of adding and subtracting a constant value. Is omitted.

  Instead of using the LSI 120 to multiplex 4: 1 by the multiplexing circuit 124, two LSIs 20 as shown in FIG. 1 are used and two outputs of the same color among the four output signals are multiplexed into the multiplexing circuit 24. An embodiment that multiplexes 2: 1 by is also conceivable. In this case, the delay amount in the delay circuit 41 is one clock cycle.

  Further, when the outputs of the eight image sensors are multiplexed into one as shown in FIGS. 7 and 8, the configuration can be made in the same manner as described above.

It is a block diagram which shows the example of schematic structure of the LSI for AD conversion used for the system which outputs two signals in parallel from an image pick-up element. It is a block diagram which shows arrangement | positioning of a filter and grouping of reading in the image pick-up element which outputs two signals in parallel. It is a timing diagram of a read signal in a system in which two signals are output in parallel from an image sensor. It is a block diagram which shows the example of schematic structure of the LSI for AD conversion used for the system which outputs four signals in parallel from an image pick-up element. It is a block diagram which shows arrangement | positioning of a filter and grouping of reading in the image pick-up element from which four signals are output in parallel. It is a timing diagram of a read signal in a system in which four signals are output in parallel from the image sensor. It is a block diagram which shows arrangement | positioning of a filter and grouping of reading in the image pick-up element which outputs eight signals in parallel. It is a timing diagram of a read signal in a system in which eight signals are output in parallel from the image sensor. It is a block diagram which shows schematic structure of an encoding & code conversion circuit. It is a block diagram which shows schematic structure of a binary-gray conversion circuit. It is an arrangement | positioning figure which shows the structural example of the filter used for an electronic camera. It is code conversion explanatory drawing which shows the specific example of the differential encoding in the AD converter circuit of an Example, and binary-gray conversion. It is a graph which shows the frequency of the switching bit number of the image data after AD conversion in the conventional imaging system, and the frequency of the switching bit number of the image data after AD conversion in the system to which the present invention is applied. It is a block diagram which shows the structural example of DSP which processes the image data after AD conversion. It is a block diagram which shows the structural example of the gray binary differential decoding circuit provided in DSP. It is a block diagram which shows the specific structural example of a gray-binary conversion circuit. It is a block diagram which shows schematic structure of a general imaging system. It is a block diagram which shows the example of schematic structure of the LSI for AD conversion used for the imaging system to which difference encoding and code conversion are applied.

Explanation of symbols

10 CCD / CMOS
20 AD conversion LSI
21a Correlated double sampling circuit (CDS)
21b Correlated double sampling circuit (CDS)
22a Programmable gain amplifier (PGA)
22b Programmable gain amplifier (PGA)
23a AD conversion circuit (ADC)
23b AD conversion circuit (ADC)
24 Multiplexer 25 Encoder & Code Converter 26 Output Buffer 30 DSP (Digital Signal Processor)
31 Gray binary differential decoding circuit 32 Image processing circuit 33 Compression / decompression circuit 41 Delay circuit 42 Differential encoding circuit 43 Code conversion circuit 50 Memory 60 DA converter 70 Filter 80 Display 100 Printed wiring board 110 CCD / CMOS
120 AD conversion LSI
121a Correlated Double Sampling Circuit (CDS)
121b Correlated Double Sampling Circuit (CDS)
121c Correlated Double Sampling Circuit (CDS)
121d Correlated Double Sampling Circuit (CDS)
122a Programmable gain amplifier (PGA)
122b Programmable gain amplifier (PGA)
122c Programmable gain amplifier (PGA)
122d Programmable gain amplifier (PGA)
123a AD conversion circuit (ADC)
123b AD converter circuit (ADC)
123c AD conversion circuit (ADC)
123d AD conversion circuit (ADC)
124 Multiplexing circuit 125 Encoding & code conversion circuit 126 Output buffer 220 AD conversion LSI
221 Correlated Double Sampling Circuit (CDS)
222 Programmable Gain Amplifier (PGA)
223 AD converter circuit (ADC)
224 Coding & code conversion circuit 225 Output buffer

Claims (9)

  Multiplexing circuits for amplifying multiple analog color video signals output from the image sensor, multiple AD conversion circuits for converting the amplified signals into digital signals, and multiplexing multiple digital signals after AD conversion A semiconductor integrated circuit comprising: multiplexing means; difference means for obtaining a difference between adjacent pixel codes relating to the same color of the multiplexed signal; and code conversion means for code-converting the output of the difference means.   2. The semiconductor integrated circuit according to claim 1, wherein the code conversion means is a binary-gray code conversion circuit for converting an input binary code into a gray code.   2. The semiconductor integrated circuit according to claim 1, wherein said code converting means is a circuit for adding or subtracting a fixed value to an input code.   4. The semiconductor integrated circuit according to claim 1, wherein the differentiating unit takes a difference between a delay circuit that delays an output code of the multiplexing unit, and a code delayed by the delay circuit and an input code. A semiconductor integrated circuit comprising: a subtracting unit; and the delay circuit is configured to have a variable delay time in accordance with a color arrangement of an input video signal.   An image sensor having a color filter and capable of simultaneously obtaining a plurality of output signals, a plurality of amplifier circuits for amplifying a plurality of analog color video signals output from the image sensor, and the amplified signals as digital signals A plurality of AD conversion circuits for conversion, a multiplexing unit that multiplexes a plurality of digital signals after AD conversion, and a difference unit that calculates a difference between codes of adjacent pixels related to the same color of the multiplexed signal; A semiconductor integrated circuit having a first code converting means for code-converting the output of the differentiating means, a second code converting means for converting a code output from the semiconductor integrated circuit, and an image processing circuit, for image processing An imaging system comprising a semiconductor integrated circuit.   6. The imaging system according to claim 5, wherein the first code conversion means is a binary-Gray code conversion circuit that converts binary code into Gray code, and the second code conversion means is Gray--that converts Gray code into binary code. An imaging system characterized by being a binary code conversion circuit.   6. The imaging system according to claim 5, wherein the first code conversion unit includes a circuit that adds or subtracts a fixed value to the input code, and the second code conversion unit includes a circuit that subtracts or adds a fixed value from the input code. An imaging system characterized by comprising:   8. The imaging system according to claim 5, wherein the differentiating means includes a delay circuit that delays an output code of the multiplexing means, and a subtraction that takes a difference between a code delayed by the delay circuit and an input code. And the delay circuit is configured such that the delay time is variable according to the color arrangement of the input video signal.   A signal conversion method for converting an analog color video signal output from an imaging device capable of outputting a plurality of signals into a digital signal, wherein the video signal is AD converted by an AD conversion circuit, and then the plurality of digital signals are multiplexed. The signal conversion is characterized in that the difference between adjacent pixel codes related to the same color after multiplexing is taken and the difference output code is converted into a code with a small number of bits that is switched between the preceding and following codes. Method.

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