JP2009038389A - Semiconductor chip adhesive - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor chip adhesive which doesn't require cleaning-off of residual flux after soldering and retains electric insulation even at a high temperature and in a humid atmosphere and allows soldering with high bonding strength and reliability. <P>SOLUTION: A resin (A) which has at least one phenol-based hydroxyl group and contains ≤5% free phenol and a resin (B) acting as a curing agent for the resin (A) are mixed as essential components in the semiconductor chip adhesive. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a solder joint for connecting a conductor terminal of a semiconductor mounting substrate and a solder bump of a semiconductor chip, and at the same time to a semiconductor chip adhesive for bonding the semiconductor mounting substrate and the semiconductor chip.

In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and further high-density mounting of electronic components have progressed. Semiconductor packages used in these electronic devices have been In addition, the size and number of pins are increasing.

With the miniaturization of semiconductor packages, the conventional package using a lead frame has a limit on miniaturization. Therefore, recently, it is assumed that a chip is mounted on a circuit board, and BGA (Ball Grid) is used. Array) and a new area mounting type packaging method such as CSP (Chip Scale Package) have been proposed. In these semiconductor packages,
As an electrical connection method of various insulating materials such as plastics and ceramics called semiconductor mounting substrates, which have the functions of a semiconductor chip electrode and a lead frame of a conventional semiconductor package, and terminals of the substrate composed of conductor wiring , Wire bonding method, TAB (Tape Automated Bonding) method, and FC (Flip Chip) method are known.
BGA and CSP structures using the FC connection method, which are advantageous for miniaturization of semiconductor packages, have been actively proposed.

Solder bonding using bumps formed of solder balls is employed for mounting BGA and CSP on a printed wiring board. For this soldering, a flux is used, and a solder paste may be used in combination. The reason why the solder balls are used in particular is that the amount of solder supply can be easily controlled and a large amount of solder can be supplied, so that the bump can be made high. Also, solder bonding is often used for the electrical connection method between the electrodes of the semiconductor chip and the terminals of the semiconductor mounting substrate in the manufacturing process of the BGA or CSP.

In general, for solder bonding, dirt on the surface of the electrode against the solder surface such as oxide on the metal surface is removed, and re-oxidation of the metal surface during solder bonding is prevented to reduce the surface tension of the solder. The soldering flux is used to make the molten solder wet easily on the metal surface. As this flux, a flux obtained by adding an activator for removing an oxide film to a thermoplastic resin flux such as rosin is used.

However, if this flux remains after bonding, problems such as deterioration of electrical insulation and corrosion of printed wiring, such as melting of the thermoplastic resin at high temperature and high humidity, and release of active ions in the activator, etc. . Therefore, at present, the residual flux after soldering is cleaned and removed to solve the above problems, but there are disadvantages such as environmental problems of the cleaning agent and cost increase due to the cleaning process.
JP-A-8-32214

In addition, the downsizing of semiconductor packages and the increase in the number of pins promote the miniaturization of bumps, and there is a concern that the bonding strength and the reliability may be reduced. Therefore, in order to obtain the reliability of the bump connection portion, it is also actively studied to seal and reinforce the bump connection portion by filling the gap between the chip and the substrate with an insulating resin called underfill. However, this requires a process of filling and curing an underfill with a high technical difficulty, and thus has a problem that the manufacturing process is complicated and the manufacturing cost is increased.

In addition, the downsizing of semiconductor packages and the increase in the number of pins promote the miniaturization of bumps, and there is a concern that the bonding strength and the reliability may be reduced. Therefore, in order to obtain the reliability of the bump connection portion, it is also actively studied to seal and reinforce the bump connection portion by filling the gap between the chip and the substrate with an insulating resin called underfill. However, this requires a process of filling and curing an underfill with a high technical difficulty, and thus has a problem that the manufacturing process is complicated and the manufacturing cost is increased.

In view of such a current problem of solder bonding at the time of mounting a semiconductor package, the present invention does not require cleaning and removal of residual flux after solder bonding, and maintains electrical insulation even in a high temperature and high humidity atmosphere. An object of the present invention is to provide a semiconductor chip adhesive that enables solder bonding with high strength and reliability.

That is, the present invention relates to a resin (A) having at least one phenolic hydroxyl group and free phenol content of 5% or less, and a resin (
B) as an essential component, and an adhesive for a semiconductor chip with solder bumps applied onto a semiconductor mounting substrate or a bonding surface of a semiconductor chip, comprising: a conductor terminal of the semiconductor mounting substrate; a solder bump of the semiconductor chip; And then soldering and bonding with a semiconductor chip adhesive, followed by curing by heating and soldering and bonding the semiconductor mounting substrate and the semiconductor chip. And a semiconductor chip adhesive.

The semiconductor chip adhesive of the present invention is preferably a phenol novolak resin, an alkylphenol novolak resin, or a biphenol novolak resin which has at least one phenolic hydroxyl group and is a resin (A) having 5% or less free phenol. A naphthol novolak resin, a resorcinol novolak resin, or a polyvinylphenol resin is an essential component, and the weight loss upon curing of the resulting semiconductor chip adhesive is 3% or less.

The semiconductor chip adhesive of the present invention does not require cleaning and removal of residual flux after solder bonding, maintains electrical insulation even in high temperature and high humidity atmosphere, and enables solder bonding with high bonding strength and reliability. So, simplifying the process in the sealed system such as mounting the semiconductor package on the printed wiring board, three-dimensional connection between layers, and suppressing the manufacturing cost,
Also, it is extremely useful for improving the reliability of solder joints.

The semiconductor chip adhesive of the present invention comprises a resin (A) having at least one phenolic hydroxyl group and containing 5% or less free phenol, and a resin (B) that acts as a curing agent. The phenolic hydroxyl group of the resin (A) having a phenolic hydroxyl group used in the present invention is due to its reducing action,
It removes dirt such as solder and oxides on the metal surface and acts as a solder joint flux. This phenolic hydroxyl group is not limited at all, but in order to enhance the action as a solder joint flux, the resin (A) having a phenolic hydroxyl group has an electron at the ortho- and para-positions relative to the phenolic hydroxyl group. Those having an attractive group and an electron donating group at the meta position are preferred.

Furthermore, since a good cured product can be obtained by the resin (B) that acts as the curing agent, there is no need for cleaning and removal after solder bonding, electrical insulation is maintained even in a high temperature and high humidity atmosphere, Enables highly reliable solder joints.

As the resin (A) having a phenolic hydroxyl group and 5% or less of free phenol used in the present invention, a phenol novolak resin, an alkylphenol novolak resin, a biphenol novolak resin, a naphthol novolak resin, a resorcinol novolak resin, a polyvinyl phenol resin Of these, at least one of them is used, and more preferably a weight average molecular weight of 20000 or less. If the molecular weight is too large, the fluidity of the semiconductor chip adhesive at the time of solder bonding is lowered, which hinders solder bonding. However, there is no problem if the melt viscosity at the time of soldering can be controlled to 50 Pa · s or less by using other compounding agents. For this purpose, a resin (B) acting as a curing agent having a low melt viscosity or a plasticizer having no volatile content may be added.

Since the solder bonding adhesive is sandwiched between layers during solder bonding and is in a sealed state, if the molecular weight is too small, swelling may occur during solder bonding due to volatilization of low molecular components or the like. In particular, the amount of free phenol is preferably 5% or less. Since free phenol has a boiling point near 180 ° C., if it exceeds 5% in the resin (A) having a phenolic hydroxyl group, the cohesive strength of the solder bonding adhesive at the temperature during solder bonding is free. Unable to withstand volatilization of phenol, causing swelling. Therefore, as a solder bonding adhesive, it is important to suppress the weight loss during curing including volatilization of the above-mentioned free phenol and low molecular vaporization component to 3% or less. However, it is also possible to suppress swelling under pressure and temperature rise conditions during solder joint molding.

As for the compounding quantity of resin (A) which has a phenolic hydroxyl group, 20 to 80 weight% of the whole semiconductor chip adhesive agent is preferable. If it is less than 20% by weight, the action of removing dirt such as solder and oxides on the metal surface is lowered, and solder bonding cannot be performed.
On the other hand, if it is more than 80% by weight, a sufficient cured product cannot be obtained, and the bonding strength and reliability are lowered. The semiconductor chip adhesive of the present invention, which has a composition that balances melt viscosity, oxide removability and curability, can greatly improve the bonding strength and reliability compared to conventional solder bonding using flux. it can.

As resin (B) which acts as a hardening | curing agent of resin (A) which has a phenolic hydroxyl group used for this invention, an epoxy resin, an isocyanate resin, etc. are used. Specifically, all are based on phenol-based ones such as bisphenol, phenol novolac, alkylphenol novolac, biphenol, naphthol and resorcinol, and skeletons such as aliphatic, cycloaliphatic and unsaturated aliphatic And modified epoxy compounds and isocyanate compounds. Moreover, in order to accelerate | stimulate hardening of the semiconductor chip adhesive of this invention, you may use a well-known curing catalyst.

The amount of the resin (B) acting as a curing agent is preferably 0.5 to 2.0 times equivalent of the hydroxyl group of the resin (A) having a phenolic hydroxyl group. When the resin (B) is less than 0.5 times equivalent, insulation reliability and electrical characteristics may be deteriorated due to the remaining phenolic hydroxyl group. Moreover, when more than 2.0 times equivalent, it may become impossible to express sufficient flux effect | action for solder joining.

The semiconductor chip adhesive of the present invention can be used as a varnish of a semiconductor chip adhesive by dissolving and mixing the above components in an organic solvent such as alcohols, ethers and ketones. The semiconductor chip adhesive varnish is applied to a semiconductor chip bonding surface with solder bumps on a semiconductor mounting substrate or the bonding surface on the semiconductor chip by a method such as screen printing or spin coating and dried, and then mounted on a semiconductor. The conductor terminals of the substrate and the solder bumps of the semiconductor chip are aligned, and are bonded, pressed, heated and soldered via a semiconductor chip adhesive. The semiconductor chip can be conductor-connected and bonded.

Hereinafter, the present invention will be described more specifically with reference to examples, but the present invention is not limited thereto.

First, a resin (A) having at least one phenolic hydroxyl group and free phenol of 5% or less and a resin (B) that acts as a curing agent thereof are blended to obtain a semiconductor chip adhesive varnish. The solder ball shear strength test, the temperature cycle test, and the insulation resistance test were performed for adjustment and evaluation of the characteristics. The evaluation results of the examples and comparative examples are collectively shown in Table 1.

Example 1.
High ortho type phenol novolac resin (R-65, OH manufactured by Sumitomo Durez Co., Ltd.)
100 g of group equivalent 105, free phenol 2%) and 160 g of bisphenol F type epoxy resin (Nippon Kayaku Co., Ltd. RE-404S, epoxy group equivalent 165) are dissolved in 60 g of cyclohexanone, and 2-phenyl is used as a curing catalyst. -4,5-dihydroxymethylimidazole 0.2g was added, and the semiconductor chip adhesive varnish was produced.

Example 2
In place of 100 g of the high-ortho type phenol novolac resin used in Example 1,
Random type phenol novolac resin (PR-51470, manufactured by Sumitomo Durez Co., Ltd.)
A semiconductor chip adhesive varnish was produced in the same manner as in Example 1 except that 100 g of OH group equivalent 105, free phenol 0.5%) was used.

Example 3 FIG.
In place of 100 g of the high-ortho type phenol novolac resin used in Example 1,
A semiconductor chip adhesive varnish was prepared in the same manner as in Example 1 except that 100 g of polyvinylphenol resin (Maruka Rinka-M, OH group equivalent 120, free phenol 0.5%, manufactured by Maruzen Petrochemical Co., Ltd.) was used. .

Comparative Example 1
In place of 100 g of the high-ortho type phenol novolac resin used in Example 1,
Phenol novolac resin (OH group equivalent 105, free phenol; 12%) 1
A semiconductor chip adhesive varnish was produced in the same manner as in Example 1 except that 00 g was used.

1. Solder ball shear strength test An evaluation circuit including a land diameter of 400 μm and a land pitch of 1 mm is formed using a 125 μm thick copper plate (EFTEC64T manufactured by Furukawa Electric Co., Ltd.), and the lead frame is formed of an epoxy resin semiconductor encapsulant. (EME-737 manufactured by Sumitomo Bakelite Co., Ltd.
2) After mold-sealing, polishing from one side to expose the evaluation circuit,
A 20 mm square evaluation package was produced. For polishing finish, JIS-R62
Water-resistant abrasive paper No. 1000 specified in No. 52 was used. This was washed with isopropyl alcohol and then dried at 80 ° C. for 30 minutes to obtain a solder joint evaluation package. For comparison, an evaluation package was also prepared in which a land other than the solder bonding land was coated with a solder resist.

The semiconductor chip adhesive varnishes obtained in Examples 1 to 3 and Comparative Example 1 were respectively applied to the entire surface of the evaluation circuit exposed surface of the evaluation package, dried at 80 ° C. for 10 minutes, and a thickness of 20 μm. The semiconductor chip adhesive film was formed. Semiconductor chip adhesives of Examples 1 to 3 and Comparative Example 1, and commercially available solder flux MS as Comparative Example 2
60 solder balls (Sn—Pb eutectic solder, manufactured by Senju Metal Mining Co., Ltd.) with a diameter of 60 μm are mounted on the land of the evaluation package circuit to which P511 (manufactured by Kyushu Matsushita Electric Co., Ltd.) is applied. The solder balls were bonded to the evaluation package through a reflow furnace set at a peak temperature of 240 ° C. Thereafter, Examples 1 to 3 and Comparative Example 1 were heat-treated at 150 ° C. for 60 minutes to cure the semiconductor chip adhesive.

Next, the solder ball shear strength of the obtained evaluation package with solder balls (
Measured by Daisy Universal Bond Tester PC2400T). The average value of 60 was obtained for each, and the results are summarized in Table 1.

2. Temperature cycle test The semiconductor chip adhesives of Examples 1 to 3 and Comparative Example 1 were applied to the entire surface of a semiconductor chip test board (FB500-PCB Co., Ltd., Tenryu Technics).
The film was dried for 0 minutes to form a semiconductor chip adhesive film having a thickness of 100 μm. A semiconductor chip test die (FBT500) having a bump diameter of 190 μm and a bump height of 140 μm is mounted on this semiconductor chip test board, passed through a reflow furnace set at a peak temperature of 240 ° C., and then compared with Examples 1-3. For Example 1, the semiconductor chip adhesive was cured by heat treatment at 150 ° C. for 60 minutes, and 10 semiconductor chip mounting test boards for evaluation were produced.

After confirming the continuity of the obtained semiconductor chip mounting test board for evaluation, it was 1 at −50 ° C.
A temperature cycle (TC) test was performed with one cycle of 0 minutes and 125 minutes at 10 minutes. The results of the number of disconnection failures after 1000 cycles of the TC test are summarized in Table 1.
Furthermore, as a comparative example, the above-mentioned commercially available flux was applied to a semiconductor chip test board, a semiconductor chip test die was mounted, and the sample was passed through a reflow furnace set at a peak temperature of 240 ° C. A sample filled with a fill was designated as Comparative Example 4. Comparative Examples 3 and 4 were used after being soldered and washed with isopropyl alcohol.

3. Insulation Resistance Test A printed wiring board for insulation reliability testing having a comb-shaped pattern with a conductor spacing of 150 μm plated with solder is used, and the semiconductors obtained in Examples 1 to 3 and Comparative Example 1 are used for this printed wiring board. Each chip adhesive varnish was applied and dried at 80 ° C. for 10 minutes to form a semiconductor chip adhesive layer having a thickness of 20 μm. As another comparative example of Comparative Example 1, a test printed wiring board coated with a commercially available flux was also prepared. After passing through a reflow furnace set at a peak temperature of 240 ° C., Examples 1 to 3 and Comparative Example 1 were heat-treated at 150 ° C. for 60 minutes to cure the semiconductor chip adhesive to obtain a test printed wiring board. .

After measuring the insulation resistance of this printed wiring board, in an atmosphere of 85 ° C / 85%,
A DC voltage of 50 V was applied, and the insulation resistance after 1000 hours was measured. The applied voltage at the time of measurement was 100 V for 1 minute, and the insulation resistance was summarized in Table 1. As a comparative example using a commercially available flux, Comparative Example 5 was obtained without washing the flux.

As can be seen from the evaluation results shown in Table 1, when using the semiconductor chip adhesive of the present invention, compared to the case of using the conventional flux, in the solder ball shear strength,
The value was twice as high, and in the TC test, almost no disconnection failure occurred. The insulation resistance test shows almost no decrease, and the effect of the semiconductor chip adhesive of the present invention is obvious.

Claims (5)

A semiconductor comprising as essential components a resin (A) having at least one phenolic hydroxyl group and containing 5% or less free phenol, and a resin (B) acting as a curing agent thereof Chip adhesive. The resin (A) having a phenolic hydroxyl group and having a free phenol content of 5% or less is selected from the group consisting of a phenol novolak resin, an alkylphenol novolak resin, a biphenol novolac resin, a naphthol novolak resin, a resorcinol novolak resin, and a polyvinyl phenol resin. 2. The semiconductor chip adhesive according to claim 1, wherein the adhesive is at least one selected. 3. The semiconductor chip adhesive according to claim 1, wherein the weight loss upon curing is 3% or less. A semiconductor chip adhesive applied on a semiconductor mounting substrate or a semiconductor chip with solder bumps, the conductor terminals of the semiconductor mounting substrate being aligned with the solder bumps of the semiconductor chip, and the semiconductor chip adhesive Through close contact,
4. The semiconductor mounting substrate and the semiconductor chip are soldered and bonded together after pressurizing and heating and soldering, and further curing by heating. Semiconductor chip adhesive. A semiconductor chip adhesive according to any one of claims 1 to 3 is applied to an adhesive surface on a semiconductor mounting substrate or a semiconductor chip with solder bumps, and the semiconductor chip adhesive is interposed through the semiconductor chip adhesive. The conductor terminals of the substrate and the solder bumps of the semiconductor chip are aligned, pressed, heated and soldered, and then cured by heating to solder and bond the semiconductor mounting substrate and the semiconductor chip. A solder bonding method characterized by the above.