JP2009038265A - Semiconductor device substrate - Google Patents

Semiconductor device substrate Download PDF

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Publication number
JP2009038265A
JP2009038265A JP2007202427A JP2007202427A JP2009038265A JP 2009038265 A JP2009038265 A JP 2009038265A JP 2007202427 A JP2007202427 A JP 2007202427A JP 2007202427 A JP2007202427 A JP 2007202427A JP 2009038265 A JP2009038265 A JP 2009038265A
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JP
Japan
Prior art keywords
substrate
semiconductor device
wire bonding
bonding pad
resin
Prior art date
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Application number
JP2007202427A
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Japanese (ja)
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JP2009038265A5 (en
Inventor
Tsuneki Ishii
恒樹 石井
Kenichi Ito
健一 伊東
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Panasonic Corp
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Panasonic Corp
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Priority to JP2007202427A priority Critical patent/JP2009038265A/en
Publication of JP2009038265A publication Critical patent/JP2009038265A/en
Publication of JP2009038265A5 publication Critical patent/JP2009038265A5/ja
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent peeling between a wire bonding pad and a sealing resin at the time of secondary packaging. <P>SOLUTION: A circuit pattern containing a wire bonding pad 6 and a through via 8 on a substrate body 4 is formed like a pinched-in gourd. Then, a region required for wire bonding is obtained, minimizing a region covered with gold plating. When sealing with resin is performed, resin goes into a bottomed via 7 formed near a region with a narrow width of the wire bonding pad 6, and anchor effect is demonstrated. After that, the wire bonding pad 6 and the sealing resin are firmly adhered. As a result, peeling between the wire bonding pad 6 and the sealing resin can be prevented at the time of secondary packaging. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、１または複数の半導体素子が実装され、樹脂封止されて半導体装置となる半導体装置用基板に関するものである。   The present invention relates to a semiconductor device substrate on which one or a plurality of semiconductor elements are mounted and resin-sealed to form a semiconductor device.

携帯電話を中心とする移動体通信分野において、通信用半導体装置の小型、薄型化と合わせて高機能化の要求が強まっている。小型化、薄型化のためにビルドアップ基板を代表例とする高性能の樹脂基板が採用されるようになり、マザーボードとの信号の入出力を行う外部接続用端子数も増加する傾向にある。   In the mobile communication field centering on mobile phones, there is an increasing demand for higher functionality as communication semiconductor devices become smaller and thinner. In order to reduce the size and thickness, a high-performance resin substrate, typically a build-up substrate, has been adopted, and the number of external connection terminals for inputting / outputting signals to / from a motherboard tends to increase.

一般的に半導体素子を実装する樹脂基板には、前記素子を載せるダイパッドと呼ばれる専用の回路パターンと、前記半導体素子と基板表面を金属細線で結線するためのワイヤーボンディングパッドと呼ばれる回路パターンが形成されている。前記の回路パターンは銅のエッチングにより形成され、金属細線を回路パターンに接続するために金メッキで被覆されている場合が多い。基板裏面には外部接続用の端子電極が銅のエッチングで形成され、表面保護と接続抵抗を下げるために表面には金メッキが形成されている。   In general, on a resin substrate on which a semiconductor element is mounted, a dedicated circuit pattern called a die pad for mounting the element and a circuit pattern called a wire bonding pad for connecting the semiconductor element and the substrate surface with a thin metal wire are formed. ing. The circuit pattern is formed by etching copper, and is often covered with gold plating to connect a fine metal wire to the circuit pattern. A terminal electrode for external connection is formed by copper etching on the back surface of the substrate, and gold plating is formed on the surface in order to reduce surface protection and connection resistance.

金メッキは金線、アルミ線などの金属細線との接続性が良好で、ワイヤーボンドで接続する際の基板温度や金属細線と金メッキの接続加重などの接続条件範囲が広く、さらに接続後の信頼性も高いため広く用いられている。   Gold plating has good connection with fine metal wires such as gold wire and aluminum wire, and has a wide range of connection conditions such as substrate temperature when connecting with wire bond and connection weight between fine metal wire and gold plating, and reliability after connection Is also widely used.

入出力端子数が多い通信用半導体装置では、基板表面側のワイヤーボンディングパッド数もそれに伴って多く、限られた面積の中でワイヤーを打つための最小限の面積のパッドが多数配置されたような基板が多い。通常、ワイヤーボンドで半導体素子と基板を結線した後、エポキシ樹脂のような封止樹脂で被覆される。   In a communication semiconductor device with a large number of input / output terminals, the number of wire bonding pads on the substrate surface side is also increased accordingly, and it seems that a large number of pads with a minimum area for placing wires in a limited area are arranged. There are many substrates. Usually, after connecting a semiconductor element and a board | substrate with a wire bond, it coat | covers with sealing resin like an epoxy resin.

以下、図３を用いて従来の半導体装置用基板について説明する。
図３は従来の半導体装置用基板の構成を示す図であり、図３（ａ）は従来の半導体装置用基板の構成を示す平面図、図３（ｂ）は図３（ａ）のＢ−Ｂ線に沿って切断した断面図である。 Hereinafter, a conventional substrate for a semiconductor device will be described with reference to FIG.
FIG. 3 is a diagram showing a configuration of a conventional substrate for a semiconductor device, FIG. 3A is a plan view showing the configuration of a conventional substrate for a semiconductor device, and FIG. It is sectional drawing cut | disconnected along B line.

図３に示す従来の半導体装置用基板１は、４．０ｍｍ□、厚み０．２ｍｍの大きさで、基板中央に半導体素子を実装する約３．０ｍｍ□のダイパッド５が形成され、その周囲に沿って半導体素子２および半導体素子３からワイヤーリード１１を接続するための長方形のワイヤーボンディングパッド６が３２箇所形成されている。前記ワイヤーボンディングパッド６内にはレーザー加工で基板本体４に貫通ビア８が形成され、それと接続して裏面側に外部接続用の端子である裏面電極１０が３２箇所形成されている。また、前記ダイパッド５、ワイヤーボンディングパッド６および外部接続用の端子である裏面電極１０の表面には金メッキが形成されている。
特開２００２−３２９８０７号公報 特開２００５−１３６３２９号公報 A conventional semiconductor device substrate 1 shown in FIG. 3 has a size of 4.0 mm □ and a thickness of 0.2 mm, and a die pad 5 of about 3.0 mm □ on which a semiconductor element is mounted is formed in the center of the substrate. 32 rectangular wire bonding pads 6 for connecting the wire leads 11 from the semiconductor element 2 and the semiconductor element 3 are formed. In the wire bonding pad 6, through vias 8 are formed in the substrate body 4 by laser processing, and 32 back surface electrodes 10 serving as external connection terminals are formed on the back surface side. Further, gold plating is formed on the surfaces of the die pad 5, the wire bonding pad 6, and the back electrode 10 which is a terminal for external connection.
JP 2002-329807 A JP 2005-136329 A

樹脂基板はパターンの寸法精度が良く、細線化、薄型化が容易という特徴を持つが、有機基材のため吸湿するという欠点も併せ持っている。そのため、樹脂基板は回路パターン表面処理に金メッキが使われることが多いが、金メッキは表面が安定で不活性なため樹脂との接着性が弱いことが知られている。   Resin substrates have the characteristics that pattern dimensional accuracy is good and thinning and thinning are easy, but they also have the disadvantage of absorbing moisture due to organic substrates. For this reason, gold plating is often used for the surface treatment of the circuit pattern of the resin substrate. However, it is known that the gold plating has a weak adhesion to the resin because the surface is stable and inactive.

最近では基板および封止樹脂の薄型化による飽和吸湿量到達時間の短縮化と、環境対策で二次実装の際に無鉛はんだを使うためリフローピーク温度が上昇している理由により、二次実装の際に樹脂基板、特にワイヤーボンディングパッドと封止樹脂間で界面剥離が起こりやすいという問題が生じてきた。   Recently, due to the shortening of the saturated moisture absorption time due to the thinner substrate and sealing resin and the use of lead-free solder for secondary mounting as an environmental measure, the reflow peak temperature has risen. At this time, there has been a problem that interfacial peeling is likely to occur between the resin substrate, particularly the wire bonding pad and the sealing resin.

本発明は、上記問題点を解決するために、二次実装の際に、ワイヤーボンディングパッドと封止樹脂間での剥離を抑制することを目的とする。   In order to solve the above-described problems, an object of the present invention is to suppress peeling between a wire bonding pad and a sealing resin during secondary mounting.

上記目的を達成するために、本発明の請求項１記載の半導体装置用基板は、１または複数の半導体素子を搭載し樹脂封止されてなる半導体装置に用いる半導体装置用基板であって、前記半導体装置用基板の本体となる基板本体と、前記半導体素子が搭載される前記基板本体の第１の主面上に形成された領域である金メッキされているダイパッドと、前記半導体装置の外部端子となる前記第１の主面と対向する前記基板本体の第２の主面に形成される裏面電極と、前記基板本体を貫通し前記裏面電極と接続する貫通ビアと、前記半導体素子と金属細線を介して電気的に接続する領域であって金メッキされて前記第１の主面に形成されるワイヤーボンディングパッドと、前記貫通ビアおよび前記ワイヤーボンディングパッドを含みくびれを備えて金メッキされている回路パターンと、前記くびれの近傍の前記第１の主面に前記回路パターン毎に少なくとも１個以上形成される有底ビアとを有することを特徴とする。   In order to achieve the above object, a semiconductor device substrate according to claim 1 of the present invention is a semiconductor device substrate used for a semiconductor device in which one or a plurality of semiconductor elements are mounted and resin-sealed. A substrate main body serving as a main body of a substrate for a semiconductor device; a gold-plated die pad that is a region formed on a first main surface of the substrate main body on which the semiconductor element is mounted; and an external terminal of the semiconductor device; A back electrode formed on the second main surface of the substrate main body facing the first main surface, a through via penetrating the substrate main body and connecting to the back electrode, the semiconductor element and the fine metal wire A wire bonding pad formed on the first main surface by gold plating, and a constriction including the through via and the wire bonding pad. A circuit pattern is plated, and having a bottomed via formed at least one or more the circuit pattern each in the first main surface in the vicinity of said constriction.

請求項２記載の半導体装置用基板は、請求項１記載の半導体装置用基板において、前記回路パターンの前記くびれが前記貫通ビアと前記ワイヤーボンディングパッドとの間に形成されることを特徴とする。   According to a second aspect of the present invention, in the semiconductor device substrate according to the first aspect, the constriction of the circuit pattern is formed between the through via and the wire bonding pad.

請求項３記載の半導体装置用基板は、請求項１または請求項２のいずれかに記載の半導体装置用基板において、前記ワイヤーボンディングパッドが前記貫通ビアよりも前記ダイパッドを基準にして前記基板本体外側に形成されることを特徴とする。   The substrate for a semiconductor device according to claim 3 is the substrate for a semiconductor device according to claim 1 or 2, wherein the wire bonding pad is outside the substrate body with respect to the die pad rather than the through via. It is formed in this.

請求項４記載の半導体装置用基板は、請求項１または請求項２または請求項３のいずれかに記載の半導体装置用基板において、前記回路パターンの前記貫通ビアとの接続領域周辺部の外形を、直線成分を持たせて形成することを特徴とする。   The semiconductor device substrate according to claim 4 is the semiconductor device substrate according to claim 1, wherein the outer shape of the periphery of the connection region of the circuit pattern with the through via is defined. , And having a linear component.

請求項５記載の半導体装置用基板は、請求項１または請求項２または請求項３または請求項４のいずれかに記載の半導体装置用基板において、前記ダイパッドの外形寸法が、搭載される前記半導体素子の搭載領域の外形寸法よりも小さいことを特徴とする。   The semiconductor device substrate according to claim 5 is the semiconductor device substrate according to claim 1, claim 2, claim 3, or claim 4, wherein an outer dimension of the die pad is mounted on the semiconductor device. It is characterized by being smaller than the outer dimensions of the element mounting area.

以上により、二次実装の際に、ワイヤーボンディングパッドと封止樹脂間での剥離を抑制することができる。   As described above, peeling between the wire bonding pad and the sealing resin can be suppressed during the secondary mounting.

以上のように本発明によれば、基板のワイヤーボンディングパッドおよび貫通ビアを含む回路パターンをくびれを持ったひょうたん形にして、金メッキで被覆された領域を最小としながらもワイヤーボンドに必要な領域を確保し、樹脂封止された際に前記パッドの幅の狭くなった領域近傍に形成された有底ビアに樹脂が入りアンカー（投錨）効果を発揮し、前記パッドと前記封止樹脂とを強固に固着し、二次実装の際のワイヤーボンディングパッドと封止樹脂間での剥離を抑制することができる。   As described above, according to the present invention, the circuit pattern including the wire bonding pad of the substrate and the through via is formed into a gourd shape having a constriction, and the area necessary for wire bonding is reduced while minimizing the area covered with gold plating. When the resin is sealed and the resin is sealed, the resin enters the bottomed via formed in the vicinity of the narrowed area of the pad to exert an anchoring effect, and the pad and the sealing resin are firmly bonded. It is possible to suppress the peeling between the wire bonding pad and the sealing resin during the secondary mounting.

以下、本発明の実施の形態を示す半導体装置用基板およびその製造方法について、図１，図２を参照しながら説明する。なお、本発明は、以下に記載の実施の形態に限定されない。また、以下において、同じ要素には同じ符号を付しており、説明を省略している場合がある。また、半導体素子の電極端子数と、半導体装置用基板の端子数と、ワイヤーリードの本数とは、各々、図面の記載の理解を得やすくするために実際の個数より少なく記載しており、図面等に記載の本数に限定されない。   Hereinafter, a substrate for a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to FIGS. The present invention is not limited to the embodiments described below. Moreover, in the following, the same code | symbol is attached | subjected to the same element and description may be abbreviate | omitted. In addition, the number of electrode terminals of the semiconductor element, the number of terminals of the substrate for the semiconductor device, and the number of wire leads are each less than the actual number in order to facilitate understanding of the description of the drawings. It is not limited to the number described in the above.

図１は本発明の半導体装置用基板の構成を示す図であり、図１（ａ）は半導体装置用基板の平面図であり、図１（ｂ）は図１（ａ）に示すＡ−Ａ線に沿って切断した断面図である。図２は本発明の半導体装置用基板に半導体素子を搭載した半導体装置の構成を示す図であり、図２（ａ）は半導体装置の平面図であり、図２（ｂ）は図２（ａ）に示すＡ−Ａ線に沿って切断した断面図である。   FIG. 1 is a diagram showing a configuration of a substrate for a semiconductor device according to the present invention, FIG. 1 (a) is a plan view of the substrate for a semiconductor device, and FIG. 1 (b) is an AA shown in FIG. It is sectional drawing cut | disconnected along the line. FIG. 2 is a diagram showing a configuration of a semiconductor device in which a semiconductor element is mounted on a semiconductor device substrate of the present invention, FIG. 2 (a) is a plan view of the semiconductor device, and FIG. 2 (b) is a diagram of FIG. It is sectional drawing cut | disconnected along the AA line shown to).

まず、図１，図２を用いて半導体装置用基板１の構成を示す。
半導体装置用基板１は、半導体素子２，３を実装するための基板であり、図１に示すように、基板本体４と半導体素子設置部であるダイパッド５と、複数のくびれを持ったひょうたん型のワイヤーボンディングパッド６と、各ワイヤーボンディングパッド６のくびれた狭い部分外側の基板領域に形成された少なくとも１個以上の有底ビア７とを備えている。 First, the configuration of the semiconductor device substrate 1 will be described with reference to FIGS.
A semiconductor device substrate 1 is a substrate on which semiconductor elements 2 and 3 are mounted. As shown in FIG. 1, a substrate body 4, a die pad 5 as a semiconductor element installation portion, and a gourd type having a plurality of constrictions. Wire bonding pads 6 and at least one or more bottomed vias 7 formed in the substrate region outside the narrow portion of each wire bonding pad 6.

基板本体４は、絶縁性部材からなり、例えば、ガラス繊維及びケブラー（登録商標）等の有機化合物からなる繊維に、エポキシ樹脂、フェノール樹脂またはポリイミド樹脂等を含浸して硬化させた基板や、ＢＴレジンからなる基板等の種々の樹脂基板を用いることができる。なお、本実施の形態では、基板本体４として、ＢＴレジンからなる基板を用いる場合を例として説明する。また、基板本体４は、半導体素子２，３を実装するための実装面４ａを有している。   The substrate body 4 is made of an insulating member, for example, a substrate obtained by impregnating an epoxy resin, a phenol resin, a polyimide resin, or the like into a fiber made of an organic compound such as glass fiber and Kevlar (registered trademark), or BT. Various resin substrates such as a resin substrate can be used. In the present embodiment, a case where a substrate made of BT resin is used as the substrate body 4 will be described as an example. The substrate body 4 has a mounting surface 4 a for mounting the semiconductor elements 2 and 3.

半導体素子設置部であるダイパッド５は、実装面４ａの中央部分に設けられており、ここでは、図１（ａ）に示すように、互いに隔離されて２つ設けられる場合を例に説明する。   The die pad 5 which is a semiconductor element installation part is provided in the center part of the mounting surface 4a. Here, as shown in FIG. 1A, a case where two are provided separately from each other will be described as an example.

ダイパッド５は、銅箔等により形成されており、半導体素子２，３と電気的に接続されている。すなわち、半導体素子２，３は後述のように、ダイパッド５の上に接地して設置される。また、搭載される半導体素子よりも外形寸法が小さく形成されても良い。   The die pad 5 is formed of a copper foil or the like and is electrically connected to the semiconductor elements 2 and 3. That is, the semiconductor elements 2 and 3 are grounded on the die pad 5 as will be described later. Further, the outer dimension may be smaller than that of the mounted semiconductor element.

各貫通ビア８は、基板本体４の厚み方向に対して貫通して設けられており、互いに等間隔に設けられている。
第２の回路パターンはワイヤーボンディングパッド６と貫通ビア８とで構成されており、各々、貫通ビア８から実装面４ａの周辺部分へ向かって延びて設けられており、ダイパッド５に対して放射状に配置されている。このようにワイヤーボンディングパッド６は、各々、貫通ビア８よりも外側に配置されていても良く、その場合には、熱などに起因して、ダイパッド５に設置した半導体素子２，３がダイパッド５から剥離してしまった場合であっても、その剥離は貫通ビア８で止まり、ワイヤーボンディングには影響を及ぼさない。 The through vias 8 are provided so as to penetrate in the thickness direction of the substrate body 4 and are provided at equal intervals.
The second circuit pattern is composed of the wire bonding pad 6 and the through via 8, each extending from the through via 8 toward the peripheral portion of the mounting surface 4 a and radially with respect to the die pad 5. Has been placed. As described above, the wire bonding pads 6 may be arranged outside the through vias 8, and in this case, the semiconductor elements 2 and 3 installed on the die pad 5 are connected to the die pad 5 due to heat or the like. Even if it is peeled off, the peeling stops at the through via 8 and does not affect the wire bonding.

ワイヤーボンディングパッド６ｃは、各々、半導体素子２，３を接地するための端子部であり、導体配線部９を介して、ダイパッド５と電気的に接続されている。すなわち、ワイヤーボンディングパッド６ｃは、各々、導体配線部９及びダイパッド５を介して、ダイパッド５に設置される半導体素子２，３に電気的に接続されて、半導体素子２，３を接地するように設置する。   Each of the wire bonding pads 6 c is a terminal portion for grounding the semiconductor elements 2 and 3, and is electrically connected to the die pad 5 through the conductor wiring portion 9. That is, the wire bonding pads 6c are electrically connected to the semiconductor elements 2 and 3 installed on the die pad 5 through the conductor wiring portion 9 and the die pad 5, respectively, so that the semiconductor elements 2 and 3 are grounded. Install.

ワイヤーボンディングパッド６ａ，６ｂは、各々半導体素子２，３に対して起動電力を供給、若しくは、電気信号の入出力するための端子部であり、ワイヤーリード１１を介して、半導体素子２，３の電極端子１２と電気的に接続される。   The wire bonding pads 6a and 6b are terminal portions for supplying starting power to the semiconductor elements 2 and 3 or inputting / outputting electric signals, respectively. It is electrically connected to the electrode terminal 12.

外部接続用の第３の回路パターンである裏面電極１０は、外部電圧の印加、若しくは、電気信号が入出力される端子部であり、実装面４ａに対する裏面に設けられており、各貫通ビア８に接続されている。すなわち、裏面電極１０は、各々、貫通ビア８、ワイヤーボンディングパッド６ａ，６ｂ，及びワイヤーリード１１を介して、ダイパッド５に設置される半導体素子２，３の電極端子１２に電気的に接続されて、半導体素子２，３に対する起動電力の印加、若しくは、電気信号の入出力に使用される。   The back surface electrode 10 which is a third circuit pattern for external connection is a terminal portion to which an external voltage is applied or an electric signal is input / output, and is provided on the back surface with respect to the mounting surface 4a. It is connected to the. That is, the back electrode 10 is electrically connected to the electrode terminals 12 of the semiconductor elements 2 and 3 installed on the die pad 5 through the through vias 8, the wire bonding pads 6 a and 6 b, and the wire leads 11, respectively. In addition, it is used for applying start-up power to the semiconductor elements 2 and 3 or for inputting and outputting electrical signals.

次に、半導体装置用基板１の製造方法を示す。
まず、ＢＴレジンからなる基板本体４の表面に、例えば銅箔を貼り付け、フォトリゾグラフィプロセスとエッチングプロセスとを用いて所定のパターン形状に加工する。 Next, a method for manufacturing the semiconductor device substrate 1 will be described.
First, for example, a copper foil is attached to the surface of the substrate body 4 made of BT resin, and processed into a predetermined pattern shape using a photolithographic process and an etching process.

具体的には、まず、例えば、厚みが０．２ｍｍのＢＴレジンからなる基板本体４の両面に、厚みが約１８μｍの銅箔を貼り付け、基板本体４に貫通ビア８を形成するための穴あけ加工を行う。次に、両面銅貼りされた樹脂基板４の表面に、無電解銅メッキおよび電解銅メッキにより銅メッキ層（図示せず）を形成する。このとき、銅メッキ層は、貫通ビア８の内面にも設けられる。そして、フォトリソグラフィプロセスとエッチングプロセスとを行うことにより、図１に示すように、ダイパッド５、ワイヤーボンディングパッド６、貫通ビア８、裏面電極１０、及び導体配線部９を設けることができる。４角の貫通ビア８を受けるためのワイヤーボンディングパッド６のパターン形状は、半導体素子実装時のダイボンダーの基板認識のために、図１に示すように、直線成分を持たすことが好ましい。   Specifically, first, for example, a copper foil having a thickness of about 18 μm is pasted on both surfaces of a substrate body 4 made of a BT resin having a thickness of 0.2 mm, and holes for forming through vias 8 in the substrate body 4 are formed. Processing. Next, a copper plating layer (not shown) is formed by electroless copper plating and electrolytic copper plating on the surface of the resin substrate 4 bonded with copper on both sides. At this time, the copper plating layer is also provided on the inner surface of the through via 8. Then, by performing a photolithography process and an etching process, the die pad 5, the wire bonding pad 6, the through via 8, the back electrode 10, and the conductor wiring portion 9 can be provided as shown in FIG. The pattern shape of the wire bonding pad 6 for receiving the four through vias 8 preferably has a linear component as shown in FIG. 1 for the substrate recognition of the die bonder when the semiconductor element is mounted.

次に、有底ビア８は、ワイヤーボンディングパッド６のくびれた部分に、レーザー加工または、ドリル加工を施すことで設けることができる。
半導体装置用基板４が奏する効果を以下にまとめる。 Next, the bottomed via 8 can be provided by performing laser processing or drilling on the constricted portion of the wire bonding pad 6.
The effects produced by the semiconductor device substrate 4 are summarized below.

上述のように、ワイヤーボンディングパッド６および貫通ビア８を含む回路パターンがくびれを持ったひょうたん型のため、半導体素子を封止するための封止樹脂との接着力の弱い金メッキ面積が減少し、且つ、樹脂封止された際にワイヤーボンディングパッド６の幅の狭くなった領域（くびれ部分）に形成された有底ビアに樹脂が入り込みアンカー（投錨）効果を発揮するため、ワイヤーボンディングパッド６と封止樹脂とを強固に固着し、二次実装の際のワイヤーボンディングパッド６と樹脂の剥離を防止することができる。   As described above, because the circuit pattern including the wire bonding pad 6 and the through via 8 is a gourd type having a constriction, the gold plating area having a weak adhesive force with a sealing resin for sealing a semiconductor element is reduced. In addition, when the resin is sealed, the resin enters the bottomed via formed in the narrowed region (necked portion) of the wire bonding pad 6 to exert an anchor (throwing) effect. It is possible to firmly fix the sealing resin and prevent the wire bonding pad 6 and the resin from being peeled off during the secondary mounting.

また、貫通ビア８から半導体装置用基板１に対して外向きに放射状にワイヤーボンディングパッド６が形成することにより、ダイパッド５に設置された半導体素子２，３がダイパッド５から剥離し、その剥離が導体配線部９を伝って進行したとしても、その剥離は貫通ビア８で止まり、ワイヤーボンディングパッド６にまで進行することを防止できる。   Further, the wire bonding pads 6 are formed radially outward from the through vias 8 with respect to the semiconductor device substrate 1, whereby the semiconductor elements 2 and 3 installed on the die pad 5 are peeled off from the die pad 5, and the peeling is performed. Even if it progresses along the conductor wiring part 9, the peeling stops at the through via 8, and it can be prevented that it progresses to the wire bonding pad 6.

また、半導体素子２，３を設置するダイパッド５の外形寸法を、半導体素子の外形寸法より小さく形成することにより、ダイパッド５表面を覆う、封止樹脂との接着力の弱い金メッキが、直接封止樹脂と接しないために、半導体素子２，３がダイパッド５から剥離してしまっても、唯一金メッキと封止樹脂が接している導体配線部９での剥離を拡大させることなく、周辺にあるワイヤーボンディングパッド６に至る剥離の進行を防止できる。   Further, by forming the outer dimensions of the die pad 5 on which the semiconductor elements 2 and 3 are installed smaller than the outer dimensions of the semiconductor element, the gold plating covering the surface of the die pad 5 and having a weak adhesive force with the sealing resin is directly sealed. Even if the semiconductor elements 2 and 3 are peeled off from the die pad 5 because they are not in contact with the resin, the wires in the periphery are not enlarged only at the conductor wiring portion 9 where the gold plating and the sealing resin are in contact. The progress of peeling to the bonding pad 6 can be prevented.

さらに、本発明は、樹脂基板に簡単な追加工を施すだけで実現されており、樹脂封止された際に基板と封止樹脂を強固に固着することで品質を向上しながら、製造コスト上昇を抑えることを可能とするものである。   Furthermore, the present invention is realized by simply performing a simple additional process on the resin substrate. When the resin is sealed, the substrate and the sealing resin are firmly fixed to improve the quality while increasing the manufacturing cost. It is possible to suppress this.

ここで、貫通ビア８とワイヤーボンディングパッド６との位置関係やダイパッド５の外形寸法等はそれぞれ組み合わせて実施しても良い。   Here, the positional relationship between the through via 8 and the wire bonding pad 6, the outer dimensions of the die pad 5, and the like may be combined.

本発明は、二次実装の際のワイヤーボンディングパッドと封止樹脂間での剥離を抑制することができ、１または複数の半導体素子が実装され、樹脂封止されて半導体装置となる半導体装置用基板等に有用である。   INDUSTRIAL APPLICABILITY The present invention can suppress peeling between a wire bonding pad and a sealing resin during secondary mounting, and for a semiconductor device in which one or a plurality of semiconductor elements are mounted and resin-sealed to form a semiconductor device. Useful for substrates.

本発明の半導体装置用基板の構成を示す図The figure which shows the structure of the board | substrate for semiconductor devices of this invention. 本発明の半導体装置用基板に半導体素子を搭載した半導体装置の構成を示す図The figure which shows the structure of the semiconductor device which mounted the semiconductor element in the board | substrate for semiconductor devices of this invention. 従来の半導体装置の構成を示す図The figure which shows the structure of the conventional semiconductor device

符号の説明Explanation of symbols

１ 半導体装置用基板
２ 半導体素子
３ 半導体素子
４ 基板本体
４ａ 実装面
５ ダイパッド
６ ワイヤーボンディングパッド
６ａ ワイヤーボンディングパッド
６ｂ ワイヤーボンディングパッド
６ｃ ワイヤーボンディングパッド
７ 有底ビア
８ 貫通ビア
９ 接地用導体配線
１０ 裏面電極
１１ ワイヤーリード
１２ 電極端子 DESCRIPTION OF SYMBOLS 1 Semiconductor device substrate 2 Semiconductor element 3 Semiconductor element 4 Substrate body 4a Mounting surface 5 Die pad 6 Wire bonding pad 6a Wire bonding pad 6b Wire bonding pad 6c Wire bonding pad 7 Bottomed via 8 Through via 9 Grounding conductor wiring 10 Back electrode 11 Wire lead 12 Electrode terminal

Claims (5)

１または複数の半導体素子を搭載し樹脂封止されてなる半導体装置に用いる半導体装置用基板であって、
前記半導体装置用基板の本体となる基板本体と、
前記半導体素子が搭載される前記基板本体の第１の主面上に形成された領域である金メッキされているダイパッドと、
前記半導体装置の外部端子となる前記第１の主面と対向する前記基板本体の第２の主面に形成される裏面電極と、
前記基板本体を貫通し前記裏面電極と接続する貫通ビアと、
前記半導体素子と金属細線を介して電気的に接続する領域であって金メッキされて前記第１の主面に形成されるワイヤーボンディングパッドと、
前記貫通ビアおよび前記ワイヤーボンディングパッドを含みくびれを備えて金メッキされている回路パターンと、
前記くびれの近傍の前記第１の主面に前記回路パターン毎に少なくとも１個以上形成される有底ビアと
を有することを特徴とする半導体装置用基板。 A substrate for a semiconductor device used in a semiconductor device in which one or a plurality of semiconductor elements are mounted and sealed with resin,
A substrate body serving as a body of the semiconductor device substrate;
A gold-plated die pad that is a region formed on the first main surface of the substrate body on which the semiconductor element is mounted;
A back electrode formed on a second main surface of the substrate body facing the first main surface to be an external terminal of the semiconductor device;
A through via passing through the substrate body and connected to the back electrode;
A wire bonding pad formed on the first main surface by gold plating in a region electrically connected to the semiconductor element through a fine metal wire;
A circuit pattern that is gold-plated with a constriction including the through via and the wire bonding pad;
A substrate for a semiconductor device, comprising: at least one bottomed via formed in the first main surface in the vicinity of the constriction for each circuit pattern. 前記回路パターンの前記くびれが前記貫通ビアと前記ワイヤーボンディングパッドとの間に形成されることを特徴とする請求項１記載の半導体装置用基板。   2. The semiconductor device substrate according to claim 1, wherein the constriction of the circuit pattern is formed between the through via and the wire bonding pad. 前記ワイヤーボンディングパッドが前記貫通ビアよりも前記ダイパッドを基準にして前記基板本体外側に形成されることを特徴とする請求項１または請求項２のいずれかに記載の半導体装置用基板。   3. The semiconductor device substrate according to claim 1, wherein the wire bonding pad is formed outside the substrate body with reference to the die pad rather than the through via. 前記回路パターンの前記貫通ビアとの接続領域周辺部の外形を、直線成分を持たせて形成することを特徴とする請求項１または請求項２または請求項３のいずれかに記載の半導体装置用基板。   4. The semiconductor device according to claim 1, wherein the outer shape of the periphery of the connection region of the circuit pattern with the through via is formed with a linear component. 5. substrate. 前記ダイパッドの外形寸法が、搭載される前記半導体素子の搭載領域の外形寸法よりも小さいことを特徴とする請求項１または請求項２または請求項３または請求項４のいずれかに記載の半導体装置用基板。   5. The semiconductor device according to claim 1, wherein an outer dimension of the die pad is smaller than an outer dimension of a mounting region of the semiconductor element to be mounted. Substrate.
JP2007202427A 2007-08-03 2007-08-03 Semiconductor device substrate Withdrawn JP2009038265A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016167556A (en) * 2015-03-10 2016-09-15 富士ゼロックス株式会社 Substrate, substrate device, optical device, image formation apparatus, wire bonding method, and manufacturing method for substrate device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016167556A (en) * 2015-03-10 2016-09-15 富士ゼロックス株式会社 Substrate, substrate device, optical device, image formation apparatus, wire bonding method, and manufacturing method for substrate device

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