JP2009027122A - Method of manufacturing thin film transistor, thin film transistor and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress dispersion in the length L of a TFT (a distance between a source and a drain of the TFT). <P>SOLUTION: A method includes a step of successively forming a gate electrode 2, a gate insulating film 3 and an amorphous silicon film 4 on an insulating substrate 1 and a step of forming a channel protection film only on an area which is a channel area of the amorphous silicon film 4. In the step of forming the channel protection film, the channel protection film is formed so that the channel protection film has a lamination structure composed of a plurality of layers 5a, 5b having respectively different etching rates and the lowermost layer 5a of the lamination structure becomes a film composition having selectivity for resetting the etching dispersion of the other layer 5b excluding the lowermost layer 5a. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a thin film transistor, a thin film transistor, and a display device having the thin film transistor.

  In recent years, a display device that displays an image using an organic EL (Electro Luminescence) phenomenon has attracted attention as one of flat panel displays. This display device, that is, an organic EL display has excellent features such as a wide viewing angle and low power consumption because it utilizes the light emission phenomenon of the organic light emitting element itself. Furthermore, since it exhibits high responsiveness to high-definition high-speed video signals, development for practical use is being promoted particularly in the video field.

  Among the driving methods for organic EL displays, the active matrix method using thin film transistors (TFTs) as driving elements is superior to conventional passive matrix methods in terms of response time and resolution. It is considered to be a driving method particularly suitable for an organic EL display having the above. This active matrix type organic EL display has an organic light emitting element (organic EL element) having at least an organic light emitting material and a driving panel provided with a TFT for driving the organic light emitting element. It has a configuration in which the sealing panel is bonded via an adhesive layer so as to sandwich the organic EL element. In addition, the active matrix organic EL display includes at least a switching transistor that controls the brightness of a pixel and a drive transistor that controls light emission of the organic EL element, as TFTs constituting the organic EL display.

  In such an organic EL display, in general, the display gradation as a display is controlled by controlling the gate voltage of the driving transistor and thereby controlling the amount of current flowing to the organic EL element. For this reason, if there is a large variation in the current flowing through the driving transistor for each pixel, the light emission luminance of the organic EL display will be different for each pixel. In other words, since the light emission of the organic EL element depends on the amount of current flowing through the drive transistor, it is very important to suppress the current variation of the drive transistor in the organic EL display in order to perform a good image display output.

  One of the factors that cause the TFT current variation is, for example, the L length variation of the TFT. Here, the “L length” of a TFT refers to the size (distance) between the source and drain of the TFT. In other words, when a TFT is formed, the finished dimension between the source and drain of the channel etching stopper becomes L length as it is, and if this finished in-plane variation is large, the on-current variation in TFT characteristics will be caused. .

  By the way, it is known that the presence or absence of the L length variation of the TFT depends on the formation accuracy of the channel protective film functioning as an etching stopper when forming the source / drain. That is, the channel protective film is usually formed by forming a resist pattern on a film formed of an insulating material and performing an etching process using the resist pattern as a mask. When variations occur, the distance between the source and the drain when a TFT is configured corresponding to the variation also occurs.

With regard to this point, for example, in forming a resist pattern for an etching stopper to be a mask, it is conceivable that exposure and development are performed in a self-aligning manner by gate electrode backside exposure, thereby reducing variation. However, such a technique does not interpolate the etching rate variation in the etching process, and as a result, there remains a problem that the etching variation causes the L length variation of the TFT.
In order to reduce the variation in the etching shift amount when forming the channel protective film, selective dry etching treatment for the channel protective film formed on the silicon film is performed using anisotropic dry etching. It is also envisaged that a method of performing However, even in the case of the anisotropic etching at the corner, the resist pattern serving as a mask is damaged by the anisotropic ion collision during the etching process on the channel protective film, and this causes the resist pattern itself to vary in anisotropic dry etching. There is a risk of reverse shifting to reflect. Therefore, it is considered that even anisotropic etching cannot be avoided as a result of the problem of variation in the finished dimension between the source and drain, as in the case of isotropic etching.
Further, for example, it is difficult to ensure that the selectivity with respect to silicon is almost infinite as in etching with hydrogen fluoride water, and the [stopper etch rate / silicon damage rate] is 2 to 10 at most. When all the film thickness of the channel protective film serving as a stopper is dry etched all at once, it is necessary to perform overetching suitable for the variation time that occurs when etching all film thicknesses, resulting in the time required for overetching. There is a problem that the length of the film becomes longer and the thickness of the silicon must be increased accordingly. Furthermore, when patterning the channel protective film on the channel region is performed using hydrogen fluoride water up to the top of the silicon, the hydrogen fluoride water that has entered from the pinholes existing on the silicon film also etches the gate insulating film. As a result, the interlayer insulating property of the gate insulating film may be deteriorated.

Further, in Patent Document 1 below, an insulating film serving as an etching stopper is made of a different laminated structure, and the taper shape is prevented from being overhanged by the hydrogen fluoride water etching process, thereby causing a transistor leakage failure. It is disclosed that it does not cause. However, in the method of performing wet etching processing that is isotropic etching in both layers to the silicon surface, the stopper insulating film itself in the middle of the etching in the middle of the wet etching processing, regardless of the laminated structure of the etching stopper, Furthermore, it plays the role of a mask for etching the remaining portion of the stopper insulating film. Therefore, there is a problem that dimensional variation caused by isotropic etching variation cannot be avoided.
Patent Document 2 listed below discloses that the channel protective film has a laminated structure, and the gate insulating film damage is suppressed and the etching damage to silicon is reduced due to pinhole penetration from a hydrofluoric acid chemical solution by dry etching. Has been. However, when etching the upper layer of the laminated structure, the resist is removed, and when the lower layer of the laminated structure is etched, the upper layer itself is used as a mask. Therefore, the upper layer etching completed dimension is transferred as it is to become L length, and as a result, there is a problem that the upper layer etching variation is directly L length variation.
Further, in Patent Document 3 below, the channel protective film has a laminated structure, and the upper layer has a slower film quality than the lower layer with respect to the etching rate in the post-process (n + layer etching process) after the channel protective film is formed. Accordingly, it is disclosed that the variation in transistor characteristics is reduced by reducing the variation in the remaining film thickness of the channel protective film itself. However, the variation in transistor characteristics here is not related to the L length variation due to the etching of the channel protective film itself, and thus the problem caused by the L length variation still cannot be solved.

Japanese Patent No. 2915397 JP-A-9-298303 JP-A-6-188422

  In view of the above-described problems in the prior art, the present invention can suppress the L-length variation of the TFT without increasing the thickness of the silicon film more than necessary, thereby forming a TFT with less characteristic variation. It is an object to provide a thin film transistor manufacturing method, a thin film transistor, and a display device having the thin film transistor.

  The present invention provides a method of manufacturing a thin film transistor devised to achieve the above object, a step of sequentially forming a gate electrode, a gate insulating film and an amorphous silicon film on an insulating substrate, and the amorphous silicon film. Forming a channel protective film only on a region to be a channel region of the semiconductor layer, forming an n + silicon film and a metal layer in order on the channel protective film and the amorphous silicon film, and forming the amorphous silicon film and the The n + silicon film is patterned to selectively leave only the region corresponding to the source / drain electrode, and the channel protective film is used as an etching stopper to selectively select the region corresponding to the channel region in the n + silicon film and the metal layer. Forming a source region and a drain region from the n + silicon film by removing; and Forming a source electrode and a drain electrode from the metal layer, and in the step of forming the channel protective film, the channel protective film has a laminated structure including a plurality of layers having different etching rates, and the laminated structure The channel protective film is formed so that the lowermost layer in FIG. 4 has a film configuration having selectivity for resetting etching variations of other layers except the lowermost layer.

  According to the thin film transistor manufacturing method of the above procedure, the channel protective film has a laminated structure with different etching rates, and the lowermost layer has a selectivity for resetting the etching variation of other layers. As an etching process for the protective film, for example, etching of other layers is performed by an etching method with a small resist dimension shift, and etching of the lowermost layer is performed by an anisotropic dry etching method having a small isotropic etching component. Is feasible. Therefore, it is possible to form the L length of the TFT in which the variation in the finish from the resist mask dimension is suppressed without making the amorphous silicon film unnecessarily thick, and as a result, the characteristic variation is smaller than the conventional one. Fewer transistors can be formed. In addition, when etching the layer immediately above the amorphous silicon film, it is possible to perform dry etching without using hydrogen fluoride water as a chemical etchant. However, the gate insulating film is not etched, and the interlayer insulating property of the gate insulating film is not lowered.

  According to the present invention, it is possible to suppress the L-length variation of the TFT without increasing the thickness of the amorphous silicon film more than necessary, thereby forming a TFT with less characteristic variation. Therefore, when a display device is configured using the TFT, since there is little characteristic variation of the TFT, it is possible to suppress the occurrence of variations in light emission luminance and the like for each pixel, resulting in a good image. It is possible to configure a display device that performs display output.

  Hereinafter, a thin film transistor manufacturing method, a thin film transistor, and a display device according to the present invention will be described with reference to the drawings.

First, a display device will be described using an organic EL display that emits light from an organic EL element using a TFT as a drive element. here,
FIG. 1 is an explanatory diagram showing a configuration example of an organic EL display having TFTs.
In the organic EL display shown in the figure, a TFT 10 as a drive element is formed on an insulating substrate 1, and an insulating planarizing film 31 is uniformly formed on the TFT 10, and a reflective electrode 32A, A plurality of organic EL elements 32 including an organic light emitting layer 32B and a transparent electrode 32C are formed, an interelectrode insulating film 33 is formed so as to isolate the organic EL elements 32, and an insulating planarizing layer is formed thereon again. 34 is formed, and a transparent substrate 35 is arranged so as to sandwich them. In the organic EL display having such a configuration, when a predetermined voltage is applied between the reflective electrode 32A and the transparent electrode 32C, the organic light emitting layer 32B emits light, thereby emitting emitted light L2 and L3 upward in the drawing. Is done.
Here, a so-called top emission type has been described, but other examples include a so-called bottom emission type and a dual emission type. It doesn't matter.

FIG. 2 is an explanatory diagram illustrating an example of a pixel circuit configuration of the organic EL display. Here, an active matrix type organic EL display using an organic EL element as a light emitting element is taken as an example.
As shown in FIG. 2A, a display area 40a and a peripheral area 40b are set on the substrate 40 of the organic EL display. The display area 40a is configured as a pixel array section in which a plurality of scanning lines 41 and a plurality of signal lines 42 are wired vertically and horizontally, and one pixel a is provided corresponding to each intersection. Each pixel a is provided with an organic EL element. In the peripheral area 40b, a scanning line driving circuit 43 that scans and drives the scanning lines 41 and a signal line driving circuit 44 that supplies a video signal (that is, an input signal) corresponding to the luminance information to the signal line 42 are arranged. Yes.
In the display area 40a, organic EL elements corresponding to the R, G, and B color components are mixed in order to perform full-color image display, and these are arranged in a matrix in accordance with a predetermined rule. It shall be. Although it is conceivable that the number of installed organic EL elements and the formation area thereof are the same for each color component, for example, they may be made different according to the energy component for each color component.
As shown in FIG. 2B, the pixel circuit provided in each pixel a includes, for example, an organic EL element 32, a drive transistor Tr, a write transistor (sampling transistor) WS, and a storage capacitor Cs. . Then, the video signal written from the signal line 42 via the write transistor WS is held in the holding capacitor Cs by driving by the scanning line driving circuit 43, and a current corresponding to the held signal amount is supplied to the organic EL element 32. Then, the organic EL element 32 emits light with a luminance corresponding to the current value.
Note that the configuration of the pixel circuit as described above is merely an example, and a capacitor element may be provided in the pixel circuit as necessary, or a plurality of transistors may be provided to configure the pixel circuit. In addition, a necessary drive circuit is added to the peripheral region 40b according to the change of the pixel circuit.

  In such an organic EL display, the display gradation as a display is controlled by controlling the gate voltage of the drive transistor Tr and thereby controlling the amount of current flowing to the organic EL element 32. For this reason, if the variation in the current flowing through the drive transistor Tr for each pixel is large, as a result, the light emission luminance of the organic EL display is different for each pixel. In other words, since the light emission of the organic EL element 32 depends on the amount of current flowing through the drive transistor Tr, it is very important to suppress the current variation of the drive transistor Tr in an organic EL display in order to achieve good image display output. It is.

The display devices typified by the organic EL display described above include various electronic devices shown in FIGS. 3 to 7, such as digital cameras, notebook personal computers, portable terminal devices such as mobile phones, video cameras, and the like. It is used as a display device for electronic devices in all fields that display video signals input to devices or video signals generated in electronic devices as images or videos. Hereinafter, specific examples of electronic devices in which the display device is used will be described.
Note that the display device includes a module having a sealed configuration. For example, a display module formed by being attached to a facing portion such as transparent glass on the pixel array portion corresponds to this. The transparent facing portion may be provided with a color filter, a protective film, and the like, and further the above-described light shielding film. Further, the display module may be provided with a circuit unit for inputting / outputting a signal to the pixel array unit from the outside, an FPC (flexible printed circuit), and the like.

  FIG. 3 is a perspective view illustrating a television which is a specific example of the electronic apparatus. The television shown in the figure includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like, and is manufactured by using a display device as the video display screen unit 101.

  4A and 4B are perspective views illustrating a digital camera which is a specific example of the electronic device, in which FIG. 4A is a perspective view seen from the front side, and FIG. 4B is a perspective view seen from the back side. The digital camera of the illustrated example includes a light emitting unit 111 for flash, a display unit 112, a menu switch 113, a shutter button 114, and the like, and is manufactured by using a display device as the display unit 112.

  FIG. 5 is a perspective view illustrating a notebook personal computer which is a specific example of the electronic apparatus. The notebook personal computer of the illustrated example includes a keyboard 122 that is operated when characters and the like are input, a display unit 123 that displays an image, and the like. The display unit 123 is used as the display unit 123. .

  FIG. 6 is a perspective view showing a video camera which is a specific example of the electronic apparatus. The video camera of the illustrated example includes a main body 131, a lens 132 for photographing an object on a side facing forward, a start / stop switch 133 at the time of photographing, a display unit 134, and the like, and a display device is used as the display unit 134. It is produced by.

  7A and 7B are diagrams illustrating a mobile terminal device, for example, a mobile phone, which is a specific example of an electronic device, in which FIG. 7A is a front view in an open state, FIG. 7B is a side view thereof, and FIG. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. The mobile phone according to this application example includes an upper housing 141, a lower housing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub display 145, a picture light 146, a camera 147, and the like. Alternatively, it is manufactured by using a display device as the sub display 145.

Next, the TFT 10 used as a drive element in the organic EL display configured as described above will be described in more detail.
FIG. 8 and FIG. 9 are explanatory diagrams showing an outline of the TFT manufacturing procedure.

In manufacturing the TFT 10, first, as shown in FIG. 8A, a molybdenum (Mo) film is uniformly formed with a thickness of about 100 nm on the insulating substrate 1 made of a glass material, a plastic material, or the like by, for example, sputtering. A gate electrode 2 is formed by forming a film and etching it by photolithography to pattern it into a predetermined shape. The metal material for forming the gate electrode 2 may be chromium (Cr) or titanium (Ti) in addition to Mo, as long as it is a metal having a high melting point that is hardly changed by heat generated when the amorphous silicon film 4 is crystallized later. ) Etc. can be considered.
After the gate electrode 2 is formed, silicon oxide (SiO ₂ ) having a thickness of about 160 nm is then uniformly formed on the insulating substrate 1 including the gate electrode 2 by, for example, plasma CVD. A gate insulating film 3 is formed. Note that an insulating material made of at least one or more of the gate insulating film 3 is not limited to being composed of SiO _2, such as SiO _2, silicon nitride (SiN) or silicon oxynitride (SiON) You may do it.
Further, an amorphous (noncrystalline) silicon film 4 is uniformly formed with a thickness of about 30 nm on the gate insulating film 3 by, for example, a plasma CVD method.

After the amorphous silicon film 4 is formed, dehydrogenation annealing is performed as a pretreatment for annealing in a nitrogen atmosphere furnace at, for example, 430 ° C., and then the amorphous silicon film 4 is irradiated with excimer laser light (λ = 308 nm) to be crystallized. Perform annealing. The laser beam used for this laser annealing process does not necessarily need to be an excimer laser or a pulse wave, and may be a continuous wave using a solid-state laser.
In the laser annealing process, a silicon nitride film, a silicon oxide film, or the like is previously formed as an antireflection film on the amorphous silicon film 4 by using, for example, a CVD method, whereby silicon can be efficiently crystallized. It is also possible to do so. In that case, the antireflection film on the amorphous silicon film 4 may be used as it is under the etching stopper of the channel protective film without being removed after the laser annealing treatment.
Further, the wavelength used for the laser annealing treatment does not necessarily need to use a wavelength in a silicon absorption region such as excimer laser light (c308 nm). For example, a wavelength of λ = 800 nm may be formed on a silicon oxide film or silicon nitride film on silicon. Are formed as a buffer layer (impurity diffusion prevention layer) for preventing impurity diffusion, and a Mo film or the like is formed as a light-to-heat conversion layer through the buffer layer to be used for annealing treatment. It becomes possible. Also in this case, the light-heat conversion layer is not removed after the laser annealing treatment, but is used as it is in the lower layer of the etching stopper of the channel protective film, or the light-heat conversion layer is removed, but the buffer layer It is conceivable to leave the film without removing it and use it as an etching stopper lower layer as it is.
Note that the above-described dehydrogenation annealing and laser annealing treatment are not necessarily required when crystallization is not necessary or when a necessary crystallinity is obtained in the film formation stage (in the CVD chamber). In this case, for example, when the gate insulating film 3 and the silicon film 4 are formed by the plasma CVD method, it is conceivable that etching stopper films 5a and 5b described later are continuously formed.

  After the modification of the amorphous silicon film 4 by the annealing process, subsequently, an etching stopper lower layer film (hereinafter simply referred to as “lower layer film”) for forming a channel protective film on the modified amorphous silicon film 4. 5a and an etching stopper upper layer film (hereinafter simply referred to as “upper layer film”) 5b are formed. Specifically, for example, a silicon oxide film as the lower layer film 5a is about 20 nm thick, and a silicon nitride film is used as the upper layer film 5b with a thickness of about 300 nm using plasma CVD so that they are stacked. Form a film. As long as the lower layer film 5a and the upper layer film 5b can function as an etching stopper, a silicon oxynitride film, a silicon oxide film, a silicon nitride film, It is conceivable to use a laminated structure of a silicon oxynitride film and another type of film.

  However, it is assumed that the lower layer film 5a and the upper layer film 5b have different etching rates. More specifically, it is assumed that each etching rate and each film thickness are set so as to satisfy the conditions described later.

  Once such a laminated structure composed of the lower layer film 5a and the upper layer film 5b is formed, a resist mask 9 is then formed at a position corresponding to the position where the channel protective film is formed using a photolithography method.

  Thereafter, in order to form a channel protective film only on the region to be the channel region of the amorphous silicon film 4, as shown in FIGS. 8B and 8C, the stacked structure composed of the lower layer film 5a and the upper layer film 5b is applied. Etching is performed. However, the etching process at this time includes a plurality of etching steps, more specifically, a first etching step for the upper film 5b (see FIG. 8B) and a second etching step for the lower film 5a (see FIG. 8 (C)).

The first etching step (hereinafter, simply referred to as “first etching”) is performed using an etching technique with a small resist dimension shift. Etching methods with a small resist dimension shift include, for example, etching with hydrogen fluoride water (wet etching), dry etching in a mode in which isotropic etching with little resist damage is dominant (PE mode dry etching), and reactive species by plasma. Etching (CDE; Chemical Dry Etching) or the like is used.
In the first etching, selectivity with the lower layer film 5a (a value of a ratio of an etching rate of a material to be removed to an etching rate of a mask material) should be sufficiently provided. For example, by controlling parameters such as power, gap between electrodes, pressure, and material gas mixing ratio at the time of CVD film formation, a difference in density between the lower layer film 5a and the upper layer film 5b can be obtained, thereby providing sufficient selectivity. Securement is possible. Alternatively, chemical dry etching is performed by adding nitrogen to a fluorocarbon-based gas without being restricted by the denseness of the film by using the lower film 5a as a silicon oxide film and the upper film 5b as a silicon nitride film. As a result, a selectivity of about 8 with respect to the silicon oxide film can be obtained.

It is assumed that the second etching step (hereinafter simply referred to as “second etching”) is performed using an etching technique having a small isotropic etching component. As an etching technique having a small amount of isotropic etching components, anisotropic dry etching is exemplified. More specifically, hydrogen is added to the fluorocarbon-based gas or hydrogen is added to the SF6 gas in the anisotropic dry etch mode and the RIE mode that enables selective etching with respect to silicon. What is performed on various gas plasma conditions is mentioned.
When the first etch is performed by dry etching (mode in which isotropic etching is dominant), the second etch also has anisotropy in the etching mode continuously with the same dry etching apparatus without breaking the vacuum. It is possible to switch to the dominant mode.

By the way, in performing the etching process in a plurality of etching steps including the first etch and the second etch as described above, the lower layer film 5a and the upper layer film 5b to be processed by the etching process, the first etch and Each etching rate by the second etching is set so as to satisfy the relationship described below.
That is, the film thickness of the upper film 5b is Bt (nm), the film thickness of the lower film 5a is At (nm), the film thickness of the portion to be the channel region of the amorphous silicon film 4 is Sit (nm), Etching rate and variation for upper layer film 5b are Bs1 (nm / min) ± Bu1 (%), etching rate and variation for lower layer film 5a in first etching are As1 (nm / min) ± Au1 (%), second etching The etching rate and variation with respect to the upper layer film 5b at Bs2 (nm / min) ± Bu2 (%), and the etching rate and variation with respect to the lower layer film 5a at the second etching are Sis2 (nm / min) ± Siu2 (%). The etching rate and variation for the amorphous silicon film 4 in 2 etches are As2 (nm / min) ± Au2 (% ), Bs1> As1, As2> Sis2, At> [2 × Bs1 × Bu1 × Bt × As1 × (100 + Au1)] / [Bs1 × Bs1 × (100−Bu1) (100 + Bu1)], and Sit > [At × Sis2 × (100 + Siu2)] / [As2 × (100−Au2)] The lower layer film 5a, the upper layer film 5b, and the amorphous silicon film 4 are formed, and the first etch and Conditions for performing the second etch (method, parameters, etc.) are set.

  By satisfying such a relationship, in the first etch, as shown in FIG. 8B, the shift damage of the formation dimension of the resist mask 9 (etching damage that changes the formation dimension) is suppressed. At the stage where the lower layer film 5a does not disappear by etching, the etching for the upper layer film 5b is completed. Moreover, even if variations in the formation dimension of the upper layer film 5b after the etching occur as a result of the etching on the upper layer film 5b, the formation dimension shift damage of the resist mask 9 is suppressed, so that the resist mask 9 is used as a mask. By performing the second etching on the lower layer film 5a, the etching variation of the upper layer film 5b can be absorbed and reset.

Next, in the second etching to be performed, as shown in FIG. 8C, the lower layer film 5a on the amorphous silicon film 4 is subjected to anisotropic selective dry etching, whereby the lower layer film 5a after the etching is subjected to the first etching. The formation dimensions of the resist mask 9 not subjected to shift damage are transferred as they are. Therefore, the etched lower layer film 5a can realize a dimensional finish in which the occurrence of variations is suppressed, and can absorb and reset the etching variations of the upper layer film 5b.
In addition, since the second etching needs to be performed by the thickness of the lower layer film 5a, a film thickness margin required depending on the degree of the etching selection ratio with respect to silicon can be reduced.
Furthermore, in the second etching, when etching the lower layer film 5a immediately above the amorphous silicon film 4, the hydrogen fluoride water that is a chemical etchant is not used but dry etching is performed. However, the gate insulating film 3 is also etched, and as a result, the interlayer insulating property of the gate insulating film 3 does not deteriorate.

Here, for example, the etching rate and variation in the first etch are 80 (nm / min) ± 10 (%) for the upper film 5b and 10 (nm / min) ± 10 (% for the lower film 5a. The etching rate and variation in the second etch are 40 (nm / min) ± 10 (%) for the lower layer film 5a and 5 (nm / min) ± 10 (%) for the amorphous silicon film 4 Assuming that the thickness of the upper layer film 5b is 300 nm, if the lower layer film 5a is 8.3 nm or more and the amorphous silicon film 4 is 1.3 nm or more, these films are not completely lost. Thus, a channel protective film with little variation is formed in which the mask dimensions of the resist mask 9 are transferred almost as they are.
Here, the amorphous silicon film 4 may be 1.3 nm or more, but this film thickness corresponds to the minimum film thickness at which the amorphous silicon film 4 does not disappear completely. Therefore, in reality, it is desirable to form a film by adding a minimum film thickness (for example, 10 nm) required in the contact layer region, and specifically, a film thickness of about 30 nm can be considered.

After the channel protective film having the laminated structure composed of the lower layer film 5a and the upper layer film 5b is formed in this way, the n + amorphous silicon film 6 is formed on the channel protective film and the amorphous silicon film 4 as shown in FIG. Is formed to a thickness of about 50 nm, and the amorphous silicon film 4 and the n + amorphous silicon film 6 are patterned to form an island pattern, and only the region corresponding to the source / drain electrode (that is, the region corresponding to the gate electrode 2) is formed. Leave selectively. Further, a metal layer 7 having a three-layer structure made of titanium having a thickness of about 50 nm / aluminum having a thickness of about 250 nm / titanium having a thickness of about 50 nm is formed. Then, an etching process is performed using the channel protective film as an etching stopper, and regions corresponding to the channel regions in the n + amorphous silicon film 6 and the metal layer 7 are selectively removed. As a result, a source region and a drain region are formed from the n + amorphous silicon film 6, and a source electrode and a drain electrode are formed from the metal layer 7.
Thereafter, a passivation film 8 made of a silicon nitride film having a thickness of about 300 nm is formed, and only the contact hole portion is patterned.

  The TFT 10 is manufactured through such a procedure (each process).

  In the manufacturing method of the TFT 10 having the above procedure and the TFT 10 obtained through the manufacturing method, the channel protective film has a laminated structure composed of the lower layer film 5a and the upper layer film 5b having different etching rates, and the lowermost layer in the laminated structure. The lower film 5a corresponding to is a film structure having selectivity for resetting the etching variation of the upper film 5b, which is another layer in the laminated structure. Then, as an etching process for forming the channel protective film, the first etch for the upper layer film 5b is performed using an etching method with a small resist dimension shift to suppress the erosion of the resist mask 9, and the second etch for the lower layer film 5a. Etching is performed by using an anisotropic dry etching method having a small isotropic etching component. Therefore, it is possible to form the L length of the TFT 10 in which the finish variation from the resist mask dimension is suppressed without making the amorphous silicon film 4 thicker than necessary, and as a result, there is less characteristic variation than the conventional one. The TFT 10 can be formed. In addition, when etching the layer immediately above the amorphous silicon film 4, hydrogen fluoride water which is a chemical etchant is not used but dry etching is performed. In this case, the interlayer insulating property of the gate insulating film 3 is not lowered.

That is, the channel protective film serving as a channel etching stopper has a laminated structure with different etching rates, the upper film 5b is etched with less resist erosion, and the lower film 5a has selectivity for resetting the etching variation of the upper film 5b. Further, the etching of the lower layer film 5a is selectively removed by anisotropic dry etching to suppress the L length variation of the TFT 10, and as a result, it is possible to form the TFT 10 with less characteristic variation. It is.
This is particularly effective when applied to a device such as an organic EL display in which the amount of current flowing through a transistor defines the luminance. This is because in such devices, it is essential to reduce current variation. In particular, when aiming at a large screen display, an etching stopper type transistor using a channel protective film is effective. However, in that case, it is not sufficient to increase the uniformity in the vertical direction (thickness direction) with respect to the channel protective film. If the uniformity in the channel direction (plane direction) is not ensured, for example, 10% or less. It is difficult to realize the current variation. On the other hand, if the TFT 10 is configured as described in the present embodiment, the uniformity in the channel direction (L length variation) can be significantly improved compared to the conventional case, and the luminance uniformity can be achieved with a large organic EL. It is very effective to secure.

  As described above, according to the TFT 10 and the manufacturing method thereof described in the present embodiment, the L-length variation of the TFT 10 can be suppressed without increasing the thickness of the amorphous silicon film 4 more than necessary, and thereby the characteristics. A TFT 10 with little variation can be formed. Therefore, when an organic EL display is configured using the TFT 10, since there is little characteristic variation of the TFT 10, it is possible to suppress the occurrence of variations such as emission luminance for each pixel, and as a result, good It becomes feasible to configure an organic EL display that performs image display output.

In the present embodiment, the preferred specific examples of the present invention have been described. However, the present invention is not limited to the contents, and can be appropriately changed without departing from the gist thereof.
For example, in the present embodiment, the case where the laminated structure constituting the channel protective film is a two-layer structure including the lower layer film 5a and the upper layer film 5b has been described as an example. If the lowermost layer is a film configuration having selectivity for resetting the etching variation, the same effects as those of the present embodiment can be obtained.
In addition, the material, film thickness, film formation method, film formation conditions, and the like of each constituent element exemplified in this embodiment are not particularly limited, and can be appropriately changed as necessary. .
In addition to the organic EL display described in this embodiment, the present invention can also be applied to a liquid crystal display device including a liquid crystal element as a display element, for example. The same effect as the case can be obtained.

It is explanatory drawing which shows the structural example of the organic electroluminescent display provided with TFT. It is explanatory drawing which shows an example of the pixel circuit structure of an organic EL display. It is a perspective view which shows the television which is a specific example of an electronic device. It is a perspective view which shows the digital camera which is a specific example of an electronic device. It is a perspective view which shows the notebook type personal computer which is a specific example of an electronic device. It is a perspective view which shows the video camera which is a specific example of an electronic device. It is a figure which shows the portable terminal device which is a specific example of an electronic device, for example, a mobile telephone. It is explanatory drawing (the 1) which shows the outline | summary of the manufacturing procedure of TFT to which this invention was applied. It is explanatory drawing (the 2) which shows the outline | summary of the manufacturing procedure of TFT to which this invention was applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Gate electrode, 3 ... Gate insulating film, 4 ... Amorphous silicon film, 5a ... Etching stopper lower layer film, 5b ... Etching stopper upper layer film, 6 ... n + amorphous silicon film, 7 ... Metal layer, 8 ... Passivation film, 9 ... resist mask, 10 ... TFT, 32 ... organic EL element

Claims (6)

Forming a gate electrode, a gate insulating film and an amorphous silicon film in order on an insulating substrate;
Forming a channel protective film only on a region to be a channel region of the amorphous silicon film;
An n + silicon film and a metal layer are sequentially formed on the channel protective film and the amorphous silicon film, and the amorphous silicon film and the n + silicon film are patterned to selectively select only a region corresponding to the source / drain electrode. And a source region and a drain region are formed from the n + silicon film by selectively removing regions corresponding to the channel region in the n + silicon film and the metal layer using the channel protective film as an etching stopper. And forming a source electrode and a drain electrode from the metal layer,
In the step of forming the channel protective film, the channel protective film has a laminated structure including a plurality of layers having different etching rates, and the lowermost layer in the laminated structure resets etching variations of other layers except the lowermost layer. A method for manufacturing a thin film transistor, characterized in that the channel protective film is formed so as to have a film structure having selectivity for the purpose. In the step of forming the channel protective film, the formation of the channel protective film having a laminated structure is performed in a plurality of etching steps,
The first etching step for forming the other layer is performed using an etching technique with a small resist dimension shift,
The method for manufacturing a thin film transistor according to claim 1, wherein the second etching step for forming the lowermost layer is performed by using an etching method having a small isotropic etching component. The film thickness of the other layer is Bt, the film thickness of the lowermost layer is At, the film thickness of the portion that becomes the channel region of the amorphous silicon film is Sit, and the film thickness of the other layer in the first etching step is The etching rate and variation are Bs1 ± Bu1, the etching rate and variation for the bottom layer in the first etching step is As1 ± Au1, and the etching rate and variation for the other layer in the second etching step are Bs2 ±. When the etching rate and variation for the lowermost layer in the second etching step is Sis2 ± Siu2, and the etching rate and variation for the amorphous silicon film in the second etching step are As2 ± Au2. , Bs1> As1, As2> Sis2, At> [ 2 × Bs1 × Bu1 × Bt × As1 × (100 + Au1)] / [Bs1 × Bs1 × (100−Bu1) (100 + Bu1)] and Sit> [At × Sis2 × (100 + Siu2)] / [As2 × (100− The method of manufacturing a thin film transistor according to claim 2, wherein the relationship of Au2)] is satisfied. Forming an antireflection film or an impurity diffusion prevention layer on the amorphous silicon film, and a photothermal conversion layer thereon;
The amorphous silicon film is crystallized by irradiating a light beam to the photothermal conversion layer or the antireflection film or impurity diffusion preventing layer to heat the amorphous silicon film. Forming a silicon film,
2. The method of manufacturing a thin film transistor according to claim 1, wherein the thin film transistor is used as it is as a lower layer of the channel protective film without removing the antireflection film or the impurity diffusion preventing layer even after the heat treatment. A gate electrode and a gate insulating film formed on the insulating substrate;
A crystalline silicon film formed on the insulating substrate via the gate electrode and the gate insulating film, and having a channel region in a region corresponding to the gate electrode;
An insulating channel protective film selectively formed in a region corresponding to the channel region on the crystalline silicon film;
An n + silicon film having a source region and a drain region on the channel protective film and the crystalline silicon film with a region corresponding to the channel region interposed therebetween;
A metal film having a source electrode and a drain electrode corresponding to the source region and the drain region, respectively.
The channel protective film has a laminated structure composed of a plurality of layers having different etching rates, and a film structure having selectivity for resetting etching variations of the other layers except the lowermost layer in the lowermost layer in the laminated structure A thin film transistor characterized in that the thin film transistor is formed. A plurality of display elements;
A thin film transistor that performs a predetermined driving operation on each of the plurality of display elements,
The thin film transistor
A gate electrode and a gate insulating film formed on the insulating substrate;
A crystalline silicon film formed on the insulating substrate via the gate electrode and the gate insulating film, and having a channel region in a region corresponding to the gate electrode;
An insulating channel protective film selectively formed in a region corresponding to the channel region on the crystalline silicon film;
An n + silicon film having a source region and a drain region on the channel protective film and the crystalline silicon film with a region corresponding to the channel region interposed therebetween;
A metal film having a source electrode and a drain electrode corresponding to the source region and the drain region, respectively.
The channel protective film has a laminated structure composed of a plurality of layers having different etching rates, and a film structure having selectivity for resetting etching variations of the other layers except the lowermost layer in the lowermost layer in the laminated structure It is formed so that it may become.

Images