JP2009026506A - Organic el display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress occurrence of a large dark spot. <P>SOLUTION: The organic EL display device is equipped with an insulating substrate SUB, a plurality of pixel electrodes PE arranged on one main face of the insulating substrate SUB, an insulating resin layer PI which covers the main face and has a plurality of first apertures installed at the positions corresponding to the plurality of pixel electrodes PE, an inorganic substance layer IL which covers the insulating resin layer PI and has a plurality of second apertures installed on the positions corresponding to the plurality of the first apertures, an organic substance layer ORG which covers the plurality of pixel electrodes PE, and a counter electrode CE which covers the organic substance layer ORG and the insulating resin layer PI. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an organic electroluminescence (EL) display device.

  Many organic EL display devices adopting an active matrix driving method include a partition insulating layer. For example, Patent Document 1 describes a method for manufacturing an organic EL display device using a partition insulating layer.

  The partition insulating layer is an insulating layer provided with an opening corresponding to the pixel electrode, and is interposed between the insulating substrate and the counter electrode. When the light-emitting layer of the organic EL element is formed by vacuum vapor deposition, the partition insulating layer plays a role of preventing the vapor deposition mask from coming into contact with the base of the light-emitting layer, for example, the hole transport layer. Further, when the light emitting layer of the organic EL element is formed by an ink jet method, the partition insulating layer makes it easy to accurately position the ink on the target pixel electrode.

  By the way, in the organic EL element in which a pinhole is generated in the counter electrode, moisture enters from the outside into the organic EL element through the pinhole. The organic EL element deteriorates immediately when moisture enters the organic layer. Therefore, an organic EL element having a pinhole in the counter electrode can be visually recognized as a dark spot.

If the dark spot is sufficiently small, the dark spot will not significantly degrade the image quality. However, some dark spots grow greatly starting from pinholes. Such dark spots can significantly degrade image quality.
Japanese Patent Application Laid-Open No. 2001-291583

  An object of the present invention is to suppress the occurrence of large dark spots.

  According to one aspect of the present invention, an insulating substrate, a plurality of pixel electrodes arranged on one main surface of the insulating substrate, a plurality of first electrodes covering the main surface and corresponding to the plurality of pixel electrodes. An insulating resin layer provided with one opening, an inorganic layer covering the insulating resin layer and provided with a plurality of second openings at positions corresponding to the plurality of first openings, and covering the plurality of pixel electrodes There is provided an organic EL display device comprising the organic layer and a counter electrode that covers the organic layer and the insulating resin layer.

  According to the present invention, generation of a large dark spot can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the component which exhibits the same or similar function, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a plan view schematically showing an organic EL display device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing an example of a display panel that can be used in the organic EL display device shown in FIG. 3 is an enlarged cross-sectional view of a part of the display panel shown in FIG. FIG. 4 is a cross-sectional view schematically showing an example of an organic EL element that can be used in the display panel shown in FIG.

  The display device of FIG. 1 is a top emission organic EL display device that employs an active matrix driving method. This display device includes a display panel DP, a video signal line driver XDR, and a scanning signal line driver YDR.

  As shown in FIGS. 1 to 3, the display panel DP includes an array substrate AS and a sealing substrate CS. The array substrate AS and the sealing substrate CS face each other and form a hollow body. Specifically, the central portion of the sealing substrate CS is separated from the array substrate AS. The peripheral edge of the sealing substrate CS is attached to one main surface of the array substrate AS via a frame-shaped sealing layer (not shown).

  The array substrate AS includes the insulating substrate SUB shown in FIGS. The insulating substrate SUB is, for example, a glass substrate.

  An undercoat layer UC shown in FIG. 3 is formed on the substrate SUB. For example, the undercoat layer UC is formed by laminating a silicon nitride layer and a silicon oxide layer in this order on the substrate SUB.

  On the undercoat layer UC, a semiconductor pattern made of, for example, polysilicon containing impurities is formed. A part of this semiconductor pattern is used as the semiconductor layer SC. Impurity diffusion regions used as a source and a drain are formed in the semiconductor layer SC. Further, another part of the semiconductor pattern is used as a lower electrode of a capacitor C described later. The lower electrodes are arranged corresponding to the pixels PX described later.

  The semiconductor pattern is covered with a gate insulating film GI. The gate insulating film GI can be formed using, for example, TEOS (tetraethyl orthosilicate).

  On the gate insulating film GI, the scanning signal lines SL1 and SL2 shown in FIG. 1 are formed. The scanning signal lines SL1 and SL2 extend in the X direction along the row of the pixels PX, and are alternately arranged in the Y direction along the column of the pixels PX. The scanning signal lines SL1 and SL2 are made of, for example, MoW. The Z direction is a direction perpendicular to the X direction and the Y direction.

  An upper electrode of the capacitor C is further disposed on the gate insulating film GI. The upper electrode is arranged corresponding to the pixel PX and faces the lower electrode of the capacitor C. The upper electrode is made of, for example, MoW, and can be formed in the same process as the scanning signal lines SL1 and SL2.

  The scanning signal lines SL1 and SL2 intersect the semiconductor layer SC. The intersection between the scanning signal line SL1 and the semiconductor layer SC constitutes the switching transistor SWa shown in FIGS. The intersection between the scanning signal line SL2 and the semiconductor layer SC forms the switching transistors SWb and SWc shown in FIG. Further, the lower electrode, the upper electrode, and the insulating film GI interposed therebetween constitute the capacitor C shown in FIG. The upper electrode includes a protrusion protruding from the capacitor C in a direction perpendicular to the Z direction, and the protrusion intersects the semiconductor layer SC. This intersection constitutes the drive transistor DR shown in FIG.

  In this example, the drive transistor DR and the switching transistors SWa to SWc are top-gate p-channel thin film transistors. Further, the part indicated by reference numeral G in FIG. 3 is the gate of the switching transistor SWa.

  The gate insulating film GI, the scanning signal lines SL1 and SL2, and the upper electrode are covered with an interlayer insulating film II. The interlayer insulating film II is made of, for example, silicon oxide deposited by a plasma CVD method.

  On the interlayer insulating film II, the video signal line DL and the power supply line PSL shown in FIG. 1 are formed. The video signal lines DL extend in the Y direction and are arranged in the X direction. For example, the power supply line PSL extends in the Y direction and is arranged in the X direction.

  On the interlayer insulating film II, a source electrode SE and a drain electrode DE shown in FIG. 3 are further formed. The source electrode SE and the drain electrode DE connect the elements in each pixel PX.

  The video signal line DL, the power supply line PSL, the source electrode SE, and the drain electrode DE have, for example, a three-layer structure of Mo / Al / Mo. These can be formed in the same process.

  The video signal line DL, the power supply line PSL, the source electrode SE, and the drain electrode DE are covered with a passivation film PS. A through hole is formed in the passivation film PS at a position corresponding to the drain electrode DE connected to the drain of the switching transistor SWa. The passivation film PS is made of, for example, silicon nitride.

  On the passivation film PS, the pixel electrodes PE are arranged corresponding to the pixels PX. These pixel electrodes PE are light-reflecting back electrodes. In this embodiment, the pixel electrode PE is an anode. Each pixel electrode PE is connected to the drain electrode DE through a through hole provided in the passivation film PS, and this drain electrode is connected to the drain of the switching transistor SWa.

  A partition insulating layer PI, which is an insulating resin layer, is further formed on the passivation film PS. In the partition insulating layer PI, a first opening is provided at a position corresponding to the pixel electrode PE. The first openings are, for example, through holes arranged corresponding to the pixel electrodes PE, or slits arranged corresponding to the columns formed by the pixel electrodes PE. Here, as an example, the first opening is a through-hole arranged corresponding to the pixel electrode PE. The partition insulating layer PI can be formed using, for example, a photolithography technique.

  As shown in FIG. 3, the partition insulating layer PI may cover the peripheral edge of each pixel electrode PE. Alternatively, the partition insulating layer PI may be separated from each pixel electrode PE.

  The partition insulating layer PI is covered with an inorganic layer IL. In this embodiment, the inorganic layer IL is an insulating layer. As the material of this insulating layer, for example, silicon oxynitride and aluminum oxide can be used.

  The inorganic layer IL is provided with a second opening at a position corresponding to the first opening. The second opening has the same shape as the first opening. That is, when the first opening is a through hole arranged corresponding to the pixel electrode PE, the second opening is also a through hole arranged corresponding to the pixel electrode PE. When the first opening is a slit arranged corresponding to the column of pixel electrodes PE, the second opening is also a slit arranged corresponding to the column of pixel electrodes PE. Here, as an example, the first opening is a through-hole arranged corresponding to the pixel electrode PE.

  The inorganic layer IL is obtained, for example, by performing film formation by sputtering and patterning using photolithography. The maximum temperature reached by the partition insulating layer PI during the formation of the inorganic layer IL is, for example, 250 ° C. or lower, and typically 200 ° C. or lower. When the partition insulating layer PI is heated to an excessively high temperature, the deterioration may occur.

  The inorganic layer IL may cover only a part of the surface of the partition insulating layer PI that is not in contact with the base (hereinafter referred to as the upper surface of the partition insulating layer PI). Alternatively, the inorganic layer IL may cover the entire top surface of the partition insulating layer PI. When the latter structure is employed, the effect of suppressing the generation of a large dark spot is greater than when the former structure is employed.

  An organic layer ORG is formed on each pixel electrode PE. Each layer included in the organic material layer ORG may be patterned corresponding to the pixel PX. Alternatively, each layer included in the organic material layer ORG may be connected between the pixels PX.

  The organic layer ORG includes the light emitting layer EML shown in FIG. The organic layer ORG can further include at least one of a hole transport layer HTL and an electron transport layer ETL in addition to the light emitting layer EML.

  The partition insulating layer PI and the organic layer ORG are covered with the counter electrode CE shown in FIGS. The counter electrode CE is a common electrode shared between the pixels PX, and is a visible light transmissive front electrode. In this embodiment, the counter electrode CE is a cathode. The counter electrode CE is, for example, an electrode wiring (not shown) formed on the same layer as the video signal line DL through a contact hole provided in the inorganic layer IL, the partition insulating layer PI, and the passivation film PS. Is electrically connected.

  Each organic EL element OLED includes a pixel electrode PE, an organic layer ORG, and a counter electrode CE. An electron blocking layer may be inserted between the light emitting layer EML and the hole transport layer HTL. A hole blocking layer may be inserted between the light emitting layer EML and the electron transport layer ETL. Further, a hole injection layer HIL shown in FIG. 4 may be inserted between the hole transport layer HTL and the pixel electrode PE which is an anode. An electron injection layer EIL shown in FIG. 4 may be inserted between the electron transport layer ETL and the counter electrode CE as a cathode.

  Each of the pixels PX includes a drive transistor DR, switching transistors SWa to SWc, an organic EL element OLED, and a capacitor C as shown in FIG. As described above, in this example, the drive transistor DR and the switching transistors SWa to SWc are p-channel thin film transistors.

  The drive transistor DR, the switching transistor SWa, and the organic EL element OLED are connected in series in this order between the first power supply terminal ND1 and the second power supply terminal ND2. In this example, the power supply terminal ND1 is a high potential power supply terminal, and the power supply terminal ND2 is a low potential power supply terminal.

  The gate of the switching transistor SWa is connected to the scanning signal line SL1. The switching transistor SWb is connected between the video signal line DL and the drain of the drive transistor DR, and its gate is connected to the scanning signal line SL2. The switching transistor SWc is connected between the drain and gate of the driving transistor DR, and the gate is connected to the scanning signal line SL2.

  The capacitor C is connected between the gate of the driving transistor DR and the constant potential terminal ND1 '. In this example, the constant potential terminal ND1 'is connected to the power supply terminal ND1.

  As shown in FIGS. 1 to 3, the sealing substrate CS faces the array substrate AS. Specifically, the sealing substrate CS faces the substrate SUB with the organic EL element OLED interposed therebetween. The sealing substrate CS is, for example, a glass substrate.

  As described above, the seal layer has a frame shape, and is interposed between the array substrate AS and the peripheral portion of the sealing substrate CS. The seal layer surrounds a pixel group constituted by all the pixels PX. As the material of the sealing layer, for example, frit glass and an adhesive can be used.

  The array substrate AS, the sealing substrate CS, and the seal layer form an airtight hollow body. The internal space of the hollow body is, for example, a vacuum or filled with an inert gas. Typically, a desiccant is placed in the hollow body. For example, the desiccant is supported on the sealing substrate CS. In this aspect, since the organic EL display device is a top emission type, the desiccant is not positioned to face the display area, but is positioned to face the peripheral area.

  The video signal line driver XDR and the scanning signal line driver YDR are mounted on the array substrate AS as shown in FIG. A video signal line DL is connected to the video signal line driver XDR. In this example, a power supply line PSL is further connected to the video signal line driver XDR. The video signal line driver XDR outputs the video signal as a current signal to the video signal line DL and supplies a power supply voltage to the power supply line PSL. Scanning signal lines SL1 and SL2 are connected to the scanning signal line driver YDR. The scanning signal line driver YDR outputs the first and second scanning signals as voltage signals to the scanning signal lines SL1 and SL2, respectively.

  When displaying an image on this organic EL display device, for example, the pixels PX are sequentially selected for each row. In a selection period in which a certain row is selected, a writing operation is performed on the pixel PX in the selected row. In the non-selection period, the display operation is performed on the pixels PX in the non-selected row.

Specifically, in a selection period for selecting a certain row, first, the switching transistor SWa is opened from the scanning signal line driver YDR to the scanning signal line SL1 to which the pixel PX included in the row is connected (non-conducting state). The scanning signal is output as a voltage signal. Subsequently, the scanning signal line driver YDR outputs, as a voltage signal, a scanning signal that closes the switching transistors SWb and SWc (makes them conductive) to the scanning signal line SL2 to which the previous pixel PX is connected. In this state, the video signal line driver YDR outputs the video signal to the video signal line DL as a current signal (write current) I _sig , and the gate-source voltage V _gs of the drive transistor DR is changed to the previous video signal. Set to a size corresponding to I _sig . Thereafter, a scanning signal for opening the switching transistors SWb and SWc is output as a voltage signal from the scanning signal line driver YDR to the scanning signal line SL2 to which the previous pixel PX is connected. Subsequently, a scanning signal for closing the switching transistor SWa is output as a voltage signal from the scanning signal line driver YDR to the scanning signal line SL1 to which the previous pixel PX is connected. This ends the selection period.

In the non-selection period following the selection period, a scanning signal for closing the switching transistor SWa is output as a voltage signal from the scanning signal line driver YDR to the scanning signal line SL1 to which the previous pixel PX is connected. The switching transistor SWa remains closed, and the switching transistors SWb and SWc remain open. In the non-selection period, a drive current I _drv having a magnitude corresponding to the gate-source voltage V _gs of the drive transistor DR flows through the organic EL element OLED. The organic EL element OLED emits light with a luminance corresponding to the magnitude of the drive current I _drv .

  This organic EL display device hardly generates a large dark spot. This will be described below.

  In manufacturing the array substrate AS, foreign matter may adhere to the film formation surface. For example, if the counter electrode CE is formed in a state where foreign matter is attached to the organic layer ORG, there is a possibility that a pinhole is generated in the counter electrode CE at the position of the foreign matter.

  Thus, when a part of the counter electrode CE is missing, moisture enters the organic EL element OLED through the missing part. As a result, the organic EL element OLED deteriorates in the vicinity of the missing portion, and the organic EL element OLED is visually recognized as a dark spot.

  The present inventors paid attention to the fact that there is a large variation in the size of the dark spot, and investigated this in detail. As a result, it was found that there is a marked difference in the growth of dark spots between the case where the counter electrode CE is missing at the position of the partition insulating layer PI and the case where it is missing at other positions. That is, when the counter electrode CE is missing at the position of the partition insulating layer PI, the dark spot grows rapidly starting from this missing part. On the other hand, when the counter electrode CE is missing at other positions, the growth of dark spots is slow. For example, in the former case, the diameter of the dark spot becomes larger at a speed of 5 times or more than in the latter case.

  The reason for such a difference is that the partition insulating layer PI is easy to absorb moisture and is thicker than other components such as the organic layer ORG. That is, if the counter electrode CE is missing at the position of the partition insulating layer PI, a large amount of moisture quickly enters the partition insulating layer PI. Part of the moisture that has entered the partition insulating layer PI deteriorates the organic EL element OLED in the vicinity of the missing portion. The other part of the moisture that has entered the partition insulating layer PI quickly moves to a position away from the missing portion using the partition insulating layer PI as a main path, thereby causing deterioration of the organic EL element OLED. . For this reason, when the counter electrode CE is missing at the position of the partition insulating layer PI, the dark spot grows rapidly starting from this missing part.

  Therefore, in the organic EL display device described above, the partition insulating layer PI is covered with the inorganic layer IL. When this structure is adopted, even if the counter electrode CE is missing at the position of the partition insulating layer PI, the inorganic layer IL prevents moisture from entering the partition insulating layer PI. Therefore, large dark spots are unlikely to occur.

  Next, the second aspect of the present invention will be described. The second mode is the same as the first mode except that a display panel described below is used.

  FIG. 5 is a cross-sectional view schematically showing an example of a display panel that can be used in the organic EL display device according to the second aspect of the present invention. The display panel DP has the same structure as the display panel DP described with reference to FIG. 3 except for the following configuration.

  That is, in the display panel DP of FIG. 5, the inorganic layer IL is made of a conductor. As this conductor, for example, conductive oxides such as ITO (indium tin oxide) and IZO (indium zinc oxide), metals, alloys, and the like can be used.

  In the display panel DP of FIG. 5, the partition insulating layer PI does not cover the pixel electrode PE and is separated from the pixel electrode PE. The inorganic layer IL covers the entire top surface of the partition insulating layer PI and is separated from the pixel electrode PE.

  According to such a structure, it can suppress that a big dark spot arises similarly to the 1st aspect. In addition, the pixel electrodes PE can be prevented from being electrically connected to each other due to the use of a conductor as the material of the inorganic layer IL.

  FIG. 6 is a cross-sectional view schematically showing another example of the display panel that can be used in the organic EL display device according to the second aspect of the present invention. The display panel DP has the same structure as the display panel DP described with reference to FIG. 5 except for the following configuration.

  In the display panel DP of FIG. 6, the partition insulating layer PI covers the peripheral edge of the pixel electrode PE as in the display panel DP described with reference to FIG. The inorganic layer IL covers only a part of the upper surface of the partition insulating layer PI. Specifically, the inorganic layer IL does not cover the area in the vicinity of the pixel electrode PE on the upper surface of the partition insulating layer PI, and covers the other areas.

  When such a configuration is employed, the occurrence of a large dark spot can be suppressed, although not as much as when the configurations of FIGS. 3 and 5 are employed. In addition, as in the case where the configuration of FIG. 5 is adopted, it is possible to prevent the pixel electrodes PE from being electrically connected due to the use of a conductor as the material of the inorganic layer IL.

  In the first and second embodiments, the thickness of the inorganic layer IL is, for example, in the range of 100 nm to 1000 nm, and typically in the range of 300 nm to 500 nm. When the inorganic layer IL is thin, the effect of preventing moisture from entering the partition insulating layer PI is reduced. Further, it is difficult to form and pattern the thick inorganic layer IL.

Various modifications can be made to the organic EL display device according to the first and second aspects.
For example, the above-described technique may be applied to a bottom emission organic EL display device instead of being applied to a top emission organic EL display device. In this case, the desiccant may be positioned so as to face the display area.

  Instead of adopting a configuration in which a current signal is written as a video signal in the organic EL display device, a configuration in which a voltage signal is written as a video signal in the organic EL display device may be employed.

  The counter electrode CE may be covered with a protective layer including an inorganic insulating layer. As a material for the inorganic insulating layer, for example, silicon oxynitride and aluminum oxide can be used.

  The sealing substrate CS and the array substrate AS may be in contact with each other at the position of the partition insulating layer PI. In this case, the counter electrode CE is typically covered with a protective layer.

  Examples of the present invention will be described below.

(Example 1)
In this example, 24 display panels DP described with reference to FIGS. 2 and 3 were manufactured by the method described below. In this example, the diagonal dimension of the display area is 3.5 inches (about 8.9 cm).

  First, rectangular glass substrates having a short side and a long side of 400 mm and 500 mm, respectively, were prepared. One main surface of the glass substrate was partitioned into 24 array regions, and the constituent elements of the array substrate AS excluding the substrate SUB were formed on each array region.

  Specifically, components from the undercoat layer UC to the partition insulating layer PI shown in FIG. 3 were formed on each array region of the glass substrate.

Next, aluminum oxide (Al ₂ O ₃ ) was deposited on the partition insulating layer PI or the like using a parallel plate magnetron sputtering apparatus. This aluminum oxide layer was patterned using photolithography. As a result, an inorganic layer IL was obtained. The aluminum oxide layer was patterned so that the width of the contact portion between the inorganic layer IL and the pixel electrode PE was about 1 μm in the opening of the inorganic layer IL. The thickness of the inorganic layer IL was 400 nm.

Next, an organic layer ORG was formed on the pixel electrode PE and the partition insulating layer PI by vacuum deposition. The organic layer ORG was composed of the hole transport layer HTL and the light emitting layer EML shown in FIG. Specifically, as the hole transport layer HTL, N, N′-diphenyl-N, N′-bis (1-naphthylphenyl) -1,1′-biphenyl-4,4′-diamine (α-NPD) A layer having a thickness of 200 nm was formed. Then, a layer having a thickness of 50 nm made of tris (8-hydroxyquinolate) aluminum (Alq ₃ ) was formed as the light emitting layer EML on the hole transport layer HTL. The light emitting layer EML also serves as an electron transport layer.

  Subsequently, a 2 nm thick layer made of an alloy of magnesium and silver was formed on the organic layer ORG as the electron injection layer HIL shown in FIG. Further, a counter electrode CE made of ITO was formed on the electron injection layer HIL. As described above, the array substrate before cleaving was completed.

  Next, 24 glass substrates were prepared as the sealing substrate CS shown in FIG. An ultraviolet curable resin layer was formed on the surface of the sealing substrate CS to be bonded to the array substrate AS.

  Next, the sealing substrate CS and the array substrate before cleaving were bonded so that the sealing substrate CS faced the array region. Further, the ultraviolet curable resin layer was irradiated with ultraviolet rays to cure them. In this example, no desiccant was used.

  Thereafter, the array substrate was cleaved along the outline of each array region. Thus, 24 display panels DP were obtained.

(Example 2)
FIG. 7 is a cross-sectional view schematically showing a display panel according to Example 2. As shown in FIG. The display panel DP has the same structure as the display panel DP described with reference to FIG. 3 except that the counter electrode CE is covered with the protective layer PL.

  In this example, 24 display panels DP were manufactured by the same method as described in Example 1 except that the protective layer PL was formed on the counter electrode CE. Specifically, in this example, a protective layer PL having a thickness of 100 nm made of silicon oxynitride (SiON) was formed on the counter electrode CE using a parallel plate magnetron sputtering apparatus.

(Example 3)
FIG. 8 is a cross-sectional view schematically showing a display panel according to Example 3. As shown in FIG. This display panel DP has the same structure as the display panel DP shown in FIG. 7 except that the sealing substrate CS is in contact with the protective layer PL. In this example, 24 display panels DP were manufactured by the same method as described in Example 2 except that the sealing substrate CS was in contact with the protective layer PL.

(Example 4)
In this example, 24 display panels DP shown in FIG. 6 were manufactured by the method described below.

  First, by the same method as in Example 1, components from the undercoat layer UC to the partition insulating layer PI were formed on each array region of the glass substrate.

  Next, ITO was deposited on the partition insulating layer PI or the like using a parallel plate magnetron sputtering apparatus. This ITO layer was patterned using photolithography after heat treatment at 200 ° C. for 1 hour. As a result, an inorganic layer IL was obtained. The ITO layer was patterned so that the inorganic layer IL was separated from the pixel electrode PE. The thickness of the inorganic layer IL was 400 nm.

  Next, the organic layer ORG, the electron injection layer HIL, and the counter electrode CE were formed by the same method as described in Example 1. As described above, the array substrate before cleaving was completed.

  Thereafter, the array substrate before cleaving and the sealing substrate CS were bonded and the array substrate was cleaved by the same method as described in Example 1 except that this array substrate before cleaving was used. Thus, 24 display panels DP were obtained.

(Comparative example)
FIG. 9 is a cross-sectional view schematically showing a display panel according to a comparative example. The display panel DP has the same structure as the display panel DP shown in FIGS. 2 and 3 except that the inorganic layer IL is omitted. In this example, 24 display panels DP were manufactured by the same method as described in Example 1 except that the inorganic layer IL was omitted.

Next, these display panels DP were left in a high temperature and high humidity environment having a temperature of 60 ° C. and a relative humidity of 90%, and the occurrence of dark spots was examined visually. The results are summarized in the following table.

  In the above table, the ratio of the display panel DP in which the dark spot is generated is described for each elapsed time after the display panel DP is left in the high temperature and high humidity environment. In the above table, each column of the column labeled “covered state” is described as “all covered” when the inorganic layer IL covers the entire top surface of the partition insulating layer PI, and the inorganic layer IL Is covered as “partially covered” when only a part of the upper surface of the partition insulating layer PI is covered. In the above table, each column of the column “array substrate / sealing substrate” indicates “contact” when the array substrate AS and the sealing substrate CS are in contact with each other at the partition insulating layer PI. ”And“ non-contact ”when there is no contact.

  As shown in this table, when the inorganic layer IL was used, dark spots were less likely to occur than when the inorganic layer IL was omitted. In particular, when the entire upper surface of the partition insulating layer PI was covered with the inorganic layer IL, the effect of suppressing the generation of dark spots was great.

  Further, when the counter substrate CS is brought into contact with the array substrate AS at the position of the partition insulating layer PI, the counter electrode CE is compared with the case where the counter substrate CS is separated from the array substrate AS at the position of the partition insulating layer PI. It is easily damaged. That is, in the former case, compared to the latter case, the counter electrode CE is likely to have a missing portion. Nevertheless, when the entire upper surface of the partition insulating layer PI is covered with the inorganic layer IL, even if the configuration in which the counter substrate CS is in contact with the array substrate AS at the position of the partition insulating layer PI is adopted, The generation could be sufficiently suppressed.

1 is a plan view schematically showing an organic EL display device according to a first embodiment of the present invention. Sectional drawing which shows roughly an example of the display panel which can be used with the organic electroluminescent display apparatus shown in FIG. Sectional drawing which expands and shows a part of display panel shown in FIG. Sectional drawing which shows roughly an example of the organic EL element which can be used with the display panel shown in FIG. Sectional drawing which shows roughly an example of the display panel which can be used with the organic electroluminescence display which concerns on the 2nd aspect of this invention. Sectional drawing which shows schematically the other example of the display panel which can be used with the organic electroluminescence display which concerns on the 2nd aspect of this invention. Sectional drawing which shows the display panel which concerns on Example 2 roughly. Sectional drawing which shows the display panel which concerns on Example 3 roughly. Sectional drawing which shows schematically the display panel which concerns on a comparative example.

Explanation of symbols

  AS ... Array substrate, C ... Capacitor, CE ... Counter electrode, CS ... Sealing substrate, DE ... Drain electrode, DL ... Video signal line, DP ... Display panel, DR ... Drive transistor, EIL ... Electron injection layer, EML ... Light emission Layer, ETL ... electron transport layer, G ... gate, GI ... gate insulating film, HIL ... hole injection layer, HTL ... hole transport layer, II ... interlayer insulating film, IL ... inorganic layer, ND1 ... power supply terminal, ND1 ' ... constant potential terminal, ND2 ... power supply terminal, OLED ... organic EL element, ORG ... organic substance layer, PE ... pixel electrode, PI ... partition insulating layer, PS ... passivation film, PSL ... power supply line, PX ... pixel, SC ... semiconductor layer , SE ... source electrode, SL1 ... scanning signal line, SL2 ... scanning signal line, SUB ... insulating substrate, SWa ... switching transistor, SWb ... switching transistor, SWc ... Tsu quenching transistor, UC ... undercoat layer, XDR ... the video signal line driver, YDR ... scanning signal line driver.

Claims (6)

An insulating substrate;
A plurality of pixel electrodes arranged on one main surface of the insulating substrate;
An insulating resin layer covering the main surface and provided with a plurality of first openings at positions corresponding to the plurality of pixel electrodes;
An inorganic layer that covers the insulating resin layer and is provided with a plurality of second openings at positions corresponding to the plurality of first openings;
An organic layer covering the plurality of pixel electrodes;
An organic EL display device comprising: a counter electrode that covers the organic material layer and the insulating resin layer.   The organic EL display device according to claim 1, wherein the inorganic layer is an insulating layer.   The organic EL display device according to claim 1, wherein the inorganic layer is a conductive layer.   2. The organic EL display device according to claim 1, wherein an entire surface of the insulating resin layer which is not in contact with the base is covered with the inorganic layer.   The organic EL display device according to claim 1, wherein the organic material layer further covers the insulating resin layer, and the inorganic material layer is interposed between the insulating resin layer and the organic material layer.   The organic EL display device according to claim 1, further comprising an inorganic insulating layer covering the counter electrode.

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