JP2009025428A - Image display device, and method for driving image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device capable of displaying properly an image even with variations or the like of an output format of an image data signal, and to provide a method for driving the image display device. <P>SOLUTION: The image display is provided with: a plurality of pixels 4 arranged in a matrix; gate wires and source wires; and gate driver circuits 2, 3 for supplying a gate signal to the gate wire, on the same substrate. Each of the gate driver circuits 2, 3 is provided with a shift register circuit having a plurality of stages for outputting sequentially the gate signal to each of the gate wire, selection periods of the gate signals supplied to the adjacent gate wires are overlapped partially, the selection period of the gate signal supplied to at least one gate wire is made shorter than that of the gate signal supplied to the other gate wire, and a start signal is supplied to the shift register at timing after a head position of the image data signal supplied to the image display. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to an image display device and an image display device driving method.

  In recent years, in an image display device such as a liquid crystal display device, a gate driver circuit is not formed on a substrate on which an active element such as a TFT (Thin Film Transistor) is formed without using a gate driver IC for manufacturing cost and high added value. The structure which forms together is employ | adopted. The shift register circuit incorporated in the gate driver circuit is described in detail in Patent Document 1.

  As a driving method employed in the gate driver circuit, Non-Patent Document 1 discloses a precharge operation driving method in which a gate wiring is activated before an image data signal is written to a pixel. In Non-Patent Document 1, a circuit configuration for performing the precharge operation driving method is described as “double ASG”. The precharge operation driving method is also called an overlap scan driving method (hereinafter referred to as an overlap scan driving method), and a gate pulse for activating a gate wiring is overlapped between adjacent gate wirings. This is a driving method in which the width of is larger than usual.

  Therefore, the overlap scan driving method has an effect of improving insufficient charging of the gate wiring and the pixel. Further, when the overlap scan driving method is applied to the shift register circuit of Patent Document 1, in addition to the above effects, there is an effect of improving the operation speed margin of the shift register circuit.

  On the other hand, the shift register circuit included in the gate driver circuit disclosed in Patent Document 1 requires at least two clock signals CKV and CKVB that do not simultaneously become “H” in order to operate at the timing illustrated in FIG. Met. Here, at least two clock signals that are not simultaneously “H” are “L” at the same time between a certain clock signal and its inverted clock signal, or between a certain clock signal and its inverted clock signal. Two clock signals having a period of zero or more.

  The shift register circuit that drives the nth gate wiring is charged with the gate potential of the transistor that drives the gate wiring by the output pulse of the (n−1) th shift register circuit, and the output pulse is output at the nth clock timing. Is done. The gate potential of the shift register circuit that drives the nth gate wiring is a period from when the output pulse of the (n−1) th shift register circuit becomes “L” until the nth clock timing becomes “H”. Is in a floating state (biased with high resistance).

  However, in the driving method, if the above period (that is, a period in which the clock signal (CKV) and the inverted clock signal (CKVB) are “L” at the same time) becomes long, charging is performed due to leakage current in the shift register circuit or the like. The nth gate potential is lowered, the output drive capability is lowered, and the operation speed of the gate driver circuit is lowered.

  Therefore, in the conventional gate driver circuit design, it is necessary to increase the output transistor size of the shift register circuit on the premise that the operation speed of the gate driver circuit decreases. Alternatively, in order not to increase the output transistor size of the shift register circuit, it has been desired that the interval time between the clock signal and the inverted clock signal should not be longer than the time required for the circuit.

  Furthermore, to improve the operating speed margin of the shift register circuit and reduce power consumption, it is possible to reduce the frequency of the clock signal and reduce the capacitive load per clock signal (mainly the gate overlap capacitance of the transistor). It was necessary to adopt a multi-phase clock signal. Further, as described above, in order not to make the interval time between the clock signal and the inverted clock longer than necessary, it is necessary to employ overlap scan driving.

JP 2004-246358 A Jin Young Choi, 7 others, “A Compact and Cost-efficient TFT-LCD through the Triple-Gate Pixel Structure”, SID2006, P-218L

  In the overlap scan drive, the “H” period of the output pulse to the gate wiring is longer than the normal drive method, but the timing of changing from “H” to “L” is the same as the normal drive method. Therefore, in the overlap scan drive, the shift register circuit must be activated before the timing of writing the output pulse to the gate wiring to the corresponding gate wiring.

  Therefore, in the case of overlap scan driving in which the clock signal is multiphased, before the timing at which the source driver circuit starts to latch the image data signal (in the device having the data enable signal, the data enable signal is enabled), It is necessary to operate the start signal of the shift register circuit and to raise a clock signal for driving the first stage gate driver circuit.

  However, in the configuration of the conventional image display device, when the output format (mainly the number of blanking) of the image data signal is changed, it is necessary to change the setting value of the timing controller in order to generate the control signal accordingly. there were. Further, even when the timing controller recognizes the head position timing of the image in the scanning direction by counting up the number of horizontal synchronization signals of the previous frame in the configuration of the conventional image display device, the output format of the image data signal is temporarily In some cases, it may not be possible to follow the target (for example, several frames).

  SUMMARY An advantage of some aspects of the invention is that it provides an image display apparatus and an image display apparatus driving method capable of appropriately displaying an image even when an output format of an image data signal is changed.

  The solution according to the present invention includes a plurality of pixels arranged in a matrix, a gate wiring and a source wiring connected to each of the pixels, and a gate driver circuit for supplying a gate signal to the connected gate wiring. An image display device provided above, wherein the gate driver circuit includes a shift register circuit having a plurality of stages for sequentially outputting a gate signal to each of the plurality of gate wirings, and a gate signal supplied to an adjacent gate wiring A selection period of the gate signal supplied to at least one gate wiring is made shorter than a selection period of the gate signal supplied to the other gate wiring and is supplied to the image display device. A start signal is supplied to the shift register circuit at a timing after the head position of the image data signal.

  Since the image display device according to the present invention can control the gate driver circuits 2 and 3 using only the synchronization signal in each vertical period (one frame), the output format of the image data signal can be changed. , Can display images properly.

(Embodiment 1)
First, FIG. 25 shows a configuration diagram of an image display device which is a premise of the image display device according to the present embodiment. The image display device shown in FIG. 25 includes a pixel array 1 that displays an image, gate driver circuits 2 and 3 that supply gate signals to gate wirings S1 to Sm provided in the pixel array 1, and each pixel of the pixel array 1. 4 includes a source driver circuit (hereinafter simply referred to as source driver 5) for supplying a pixel data signal. Further, the image display device shown in FIG. 25 includes a power supply circuit 6 that supplies power supply voltages VDD and VSS to the gate driver circuits 2 and 3, and a timing generation circuit 7 that controls the timing of the gate driver circuits 2 and 3 and the source driver 5. And a level shifter circuit 8 for adjusting the voltage level of the control signal supplied to the shift register circuits SRCO and SRCE.

  Further, the gate driver circuit 2 shown in FIG. 25 has the stages SRCO1 to SRCONn + 1 of the shift register circuit that outputs the gate signals SROUTO1 to SROUTOn for the gate wirings G1, G3,. Have. Similarly, the gate driver circuit 3 shown in FIG. 25 has stages of shift register circuits SRCE1 to SRCEn + 1 that output gate signals SROUTE1 to SROUTEn for the gate lines G2, G4,. is doing. In the following description, each stage of the shift register circuit is also simply referred to as a shift register circuit. The power supply voltages VDD and VSS of the shift register circuits SRCO and SRCE are supplied from the power supply circuit 6. The clock signals CKVO, CKVBO, CKVE and CKVBE are supplied from the level shifter circuit 8 to the CK terminals of the shift register circuits SRCO and SRCE. Supplied as

  Further, start signals STVO and STVE are supplied from the level shifter circuit 8 to the IN terminals of the uppermost shift register circuits SRCO1 and SRCE1 of the gate driver circuits 2 and 3, respectively. Then, the output of the previous stage (output from the OUT terminal) is supplied to the IN terminals of the shift register circuits SRCO2... SRCE2. The timing generation circuit 7 is supplied with a vertical synchronization signal, a horizontal synchronization signal, a dot clock signal, a data enable signal, and an image data signal.

  FIG. 26 shows a timing chart in which the overlap scan drive is not performed in the image display apparatus shown in FIG. 25, and FIG. 27 shows a timing chart in which the overlap scan drive is performed. In the timing chart shown in FIG. 26, multi-phase clock signals that can reduce the frequency of the clock signal and reduce the capacity load per clock signal are employed. In the multi-phase clock signal, the interval time between the clock signal and the inverted clock signal becomes longer as the clock signal is multi-phased. Specifically, in the timing chart shown in FIG. 26, the clock signal has four phases, and the interval time between the clock signals CKVO and CKVE and the inverted clock signals CKVBO and CKVBE is about one horizontal period. Although not shown, when the clock signal is divided into eight phases, the interval time between the clock signal and the inverted clock signal is about 3 horizontal periods.

  On the other hand, in the timing chart shown in FIG. 27 in which overlap scan driving is performed, the clock signals CKVO and CKVE and the inverted clock signals CKVBO and CKVBE have “H” periods of about two horizontal periods. Therefore, in the timing chart shown in FIG. 27, the interval time between the clock signals CKVO and CKVE and the inverted clock signals CKVBO and CKVBE is one horizontal period or less.

  In the timing chart shown in FIG. 27, the “H” period of the output pulses to the gate wirings G1 to Gn is longer than that in FIG. 26, but the timing of changing from “H” to “L” is the same as in FIG. Therefore, in the timing chart shown in FIG. 27 in which the overlap scan driving is performed, the start signals STVO and STVE must be set to “H” before the output pulse to the gate lines G1 to Gn is written to the corresponding gate lines G1 to Gn. Don't be.

  That is, in the timing chart shown in FIG. 27, it is necessary to operate the shift register circuits SRCO1 and SRCE1 before the timing when the source driver 5 starts to latch the image data signal (the timing when the data enable signal is enabled).

  Specifically, in the timing chart shown in FIG. 27, the start signal STVO is active from the t-2 period, and the start signal STVE is active from the t-1 period. In the timing chart shown in FIG. 27, since positive logic is employed, the active state is “H”.

  In the timing chart shown in FIG. 27, the clock signal CKVO supplied to the shift register circuit SRCO1 connected to the gate wiring G1 in the first row is active during a period in which the data enable signal is active.

  In order for the timing generation circuit 7 to supply the gate driver circuits 2 and 3 with the start signals STVO and STVE having the timing shown in FIG. There is. First, the first condition is that the blanking numbers (front porch and back porch) before and after the vertical synchronization signal are known and do not vary in the output format of the image data signal. As a next condition, the timing generation circuit 7 that generates the start signals STVO and STVE has a function of recognizing the leading position of the image data signal in the scanning direction by counting up the number of horizontal synchronization signals in the previous frame. Is the case. The next condition is a case where a line memory for delaying the image data signal at the head position in the scanning direction by a necessary number or a circuit for latching analog data is provided.

  However, any of the above conditions has the following problems. First, when the output format of the image data signal (mainly the number of blanking) is changed, it is necessary to change the set value of the timing generation circuit 7 for generating the start signals STVO and STVE accordingly. A circuit that generates an image data signal when the timing generation circuit 7 that generates the start signals STVO and STVE recognizes the start position of the image data signal in the scanning direction by counting up the number of horizontal synchronization signals in the previous frame. If the output format of the image data signal fluctuates temporarily (for example, several frame periods) due to the circumstances, it may not be possible to follow. Further, a circuit having a scale corresponding to the resolution in the horizontal direction of the image data signal, such as a line memory or an analog latch circuit, is necessary. Further, in the output format of the image data signal, when there is no vertical synchronizing signal and horizontal synchronizing signal and only the data enable signal is used, the head position (G1) of the screen data signal has to be determined only by the data enable signal.

  In view of this, the image display apparatus according to the present embodiment employs a configuration in which the above-described problem is not caused in overlap scan driving in which clock signals are multiphased. Specifically, the image display apparatus according to the present embodiment employs a configuration in which the gate driver circuits 2 and 3 are controlled using only the synchronization signal in each vertical period (one frame), and the configuration is The driving method used is performed.

  FIG. 1 shows a configuration diagram of an image display apparatus according to the present embodiment. In the image display device shown in FIG. 1, the pixel array 1 has m columns × n rows of pixels 4, and the gate wiring G <b> 1 is connected to the first row of the pixels 4, and the gate wiring Gn is connected to the last row. ing. The gate driver circuit 2 shown in FIG. 1 includes shift register circuits SRCO1 to SRCONn + 1 that scan odd-numbered rows starting from the gate line G1 and ending to the gate line Gn-1. The shift register circuit SRCO1 supplies the gate signal SROUTO1 to the gate wiring G1, and the shift register circuit SRCON supplies the gate signal SROUTOn to the gate wiring Gn-1. In FIG. 1, a buffer section for driving the gate wiring is omitted for the sake of simplicity.

  Similarly, the gate driver circuit 2 shown in FIG. 1 includes shift register circuits SRCE1 to SRCEn + 1 that scan even-numbered rows starting from the gate line G2 and ending at the gate line Gn. The shift register circuit SRCE1 supplies the gate signal SROUTE1 to the gate wiring G2, and the shift register circuit SRCEn supplies the gate signal SROUTEn to the gate wiring Gn.

  Each of the gate driver circuits 2 and 3 includes a shift register circuit SRC having a plurality of stages for sequentially outputting a gate signal to each of a plurality of gate wirings. The IN terminal of each stage of the shift register circuit SRC includes a preceding stage. The output (output from the OUT terminal) is input from the stage. That is, the shift register circuit SRC activates the gate potential of the transistor that drives the gate wiring in synchronization with the previous gate signal, and outputs the gate signal in synchronization with the clock signal. The shift register circuit SRC is reset by the gate signal output from the subsequent stage. Note that the shift register circuit SRC is reset by the gate signal output from the subsequent stage is not described in each drawing of the present application.

  The gate driver circuits 2 and 3 shown in FIG. 1 are arranged on the left and right sides of the pixel array 1. However, the present invention is not limited to this, and any one can be used as long as the connection between the shift register circuit and the gate wiring is the same. Such an arrangement may be used. The shift register circuit SRC shown in FIG. 1 is supplied with the power supply voltage VDD from the power supply circuit 6, but the present invention is not limited to this, and may have a circuit configuration that does not supply the power supply voltage VDD.

  The source driver 5 shown in FIG. 1 writes an image data signal to each pixel 4 of the pixel array 1 via m columns of source wirings. The power supply circuit 6 shown in FIG. 1 supplies power supply voltages VDD and VSS to the gate driver circuits 2 and 3. A timing generation circuit 7 shown in FIG. 1 generates a timing required for the source driver 5 and the gate driver circuits 2 and 3 from a vertical synchronization signal, a horizontal synchronization signal, an image data signal, a data enable signal, a dot clock signal, and the like. The level shifter circuit 8 shown in FIG. 8 converts the control signal of the timing generation circuit 7 into a voltage level for driving the gate driver circuits 2 and 3. Here, the control signal includes a start signal STV and clock signals CKV and CKVB.

  When the timing generation circuit 7 is formed of a silicon transistor or the like, the drive voltage is smaller than the power supply voltage (voltage between VDD and VSS (about 30 V)) of the circuit using the a-Si (amorphous silicon) TFT. Therefore, the level shifter circuit 8 for changing the “H” voltage and “L” voltage levels of the control signal is necessary. Here, the level shifter circuit 8 is formed of a silicon transistor or a low-temperature polysilicon TFT. In FIG. 1, the power supply of the level shifter circuit 8 is not shown.

  The image display device shown in FIG. 1 is different from the image display device shown in FIG. 25 in that the shift register circuit SRCO1 that drives the gate wiring G1 of the gate driver circuit 2 has two circuits, a shift register circuit SRCO1A and a shift register circuit SRCO1B. It is configured. The outputs of the shift register circuit SRCO1A and the shift register circuit SRCO1B are both output to the gate wiring G1. The start signal STVO is supplied to each of the shift register circuit SRCO1A and the shift register circuit SRCO1B.

  In the image display device shown in FIG. 1, by providing the shift register circuits SRCO1A and SRCO1B, the driving capability of the gate wiring G1 as the first row is about twice that of the other gate wirings, and each vertical period (one frame) is included. The gate driver circuits 2 and 3 can be controlled using only the synchronization signal. The image display device shown in FIG. 1 has been described on the premise of a liquid crystal display device. However, as long as the display device sequentially scans the gate wiring, the image display device is not limited to the liquid crystal and may be an organic EL (Electro-Luminescence) or other display device. good.

  Next, the operation of the image display apparatus shown in FIG. 1 will be described using the timing chart shown in FIG. In the timing chart shown in FIG. 2, an input image signal, a source signal, a control signal for the gate driver circuit, and an output pulse (gate signal) to the gate wiring are shown, and a period from t0 to tn is one vertical period (one frame). It is said. The input image signal is composed of a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and an image data signal. The gate driver circuit control signals are start signals STVO, STVE, and four-phase clock signals CKVO, CKVE, CKVBO. , CKVBE. The operations of the source driver 5 and the timing generation circuit 7 shown in FIG. Further, “D” shown in the source signal of FIG. 2 is an abbreviation for a dummy signal.

  Since the gate driver circuits 2 and 3 shown in FIG. 1 are arranged on the left and right sides of the pixel array 1, the gate driver circuit 2 supplies odd-numbered gate wirings G1, G3,. The even-numbered gate wirings G2, G4,..., Gn are driven.

  The first stage shift register circuits SRCO1A and SRCO1B provided in the gate driver circuit 2 receive the start signal STVO and output the gate signal SROUTO1 to the gate line G1. Note that the shift register circuit SRCO at each stage incorporates a buffer amplifier (not shown) so that the output can charge the capacity of the gate wiring within a required time.

  The second stage shift register circuit SRCO2 receives the output of the first stage (gate signal SROUTO1) and outputs the gate signal SROUTO2 to the gate line G3. Similarly, the third-stage shift register circuit SRCO3 receives the second-stage output (gate signal SROUTO2) and outputs the gate signal SROUTO3 to the gate line G5. As described above, the shift register circuit SRCO of each stage receives the output of the previous stage and supplies the output (gate signal SROUTO) to the gate wiring corresponding to the stage.

  On the other hand, the first stage shift register circuit SRCE1 provided in the gate driver circuit 3 receives the start signal STVE and outputs a gate signal SROUTE1 to the gate line G2. Note that the shift register circuit SRCE at each stage incorporates a buffer amplifier (not shown) so that the output can charge the capacity of the gate wiring within a required time.

  The second stage shift register circuit SRCE2 receives the output of the first stage (gate signal SROUTE1) and outputs the gate signal SROUTE2 to the gate line G4. Similarly, the third stage shift register circuit SRCE3 receives the second stage output (gate signal SROUTE2) and outputs the gate signal SROUTE3 to the gate line G6. As described above, the shift register circuit SRCE of each stage receives the output of the previous stage and supplies an output (gate signal SROUTE) to the gate wiring corresponding to the stage. In the timing chart shown in FIG. 2, the gate signals SROUTO and SROUTE are shown as output pulses of the gate lines G1 to Gn.

  The output of the first stage shift register circuit SRCO1 provided in the gate driver circuit 2 is output to the first gate wiring G1 of the pixel array 1, and the output of the first stage shift register circuit SRCE1 provided in the gate driver circuit 3 is Are connected to the second gate wiring G2 of the pixel array 1, respectively. Then, when the clock signals CKV and CKVB and the start signal STV are input to the shift register circuits SRCO1 and SREO1, scanning is sequentially performed from the first gate wiring G1 to the nth gate wiring Gn of the pixel array 1, and the pixels An image is displayed on the array 1.

  In the timing chart shown in FIG. 2, the top horizontal synchronization period in which the image data signal is input from the outside is set to t0 (unit is 1H). In the timing chart shown in FIG. 2, since the control signals for the gate driver circuits 2 and 3 are generated using only the synchronizing signal in each vertical period (one frame), the start signal STVO, STVE cannot be output. Therefore, in the timing chart shown in FIG. 2, the start signals STVO and STVE are driven to become active during the t0 period, and the clock signal CKVO for driving the gate wiring G1 is activated during the t1 period. That is, in the image display device according to this embodiment, only the width of the clock signal (clock signal CKVO in the period t1) corresponding to the position of the gate wiring G1 is made shorter than the widths of the other clock signals. The “H” period of the output pulse is made shorter than the output pulses of the other gate wirings, and the gate driver circuits 2 and 3 are driven only by the synchronization signal in each vertical period (one frame).

  As described above, in the image display device according to the present embodiment, the gate supplied to at least one gate wiring in overlap scan driving in which part of the selection period of the gate signal supplied to the adjacent gate wiring overlaps. The signal selection period (in FIG. 2, the output of the gate line G1 in the period t1) is shorter than the selection period of the gate signal supplied to the other gate lines. Here, the selection period is a period during which the gate signal is active (“H” period when positive logic is adopted). In this embodiment, driving is performed so that a start signal is supplied to the shift register circuit at a timing after the head position of the image data signal supplied to the image display device.

  As shown in the timing chart of FIG. 2, if only the width of the clock signal CKVO corresponding to the output of the gate line G1 in the t1 period is shortened and driven, the display performance and the operation margin of the circuit are shifted to drive the gate line G1. It depends on the driving capability of the register circuit. If another shift register circuit is designed on the basis of the shift register circuit that drives the gate wiring G1, the gate wiring other than the gate wiring G1 has a surplus driving capability, which increases power consumption and layout area. It becomes useless.

  Therefore, in the image display device according to the present embodiment, as shown in FIG. 1, the shift register circuit that drives the gate wiring G1 that requires a large driving capability is configured with two circuits (shift register circuits SRCO1A and SRCO1B). . With the circuit configuration shown in FIG. 1, the driving capability of the shift register circuit that drives the gate wiring G1 can be improved by a factor of about 2 without destroying the layout ratio in the circuit.

  Further, the drive capability of the shift register circuit can be improved by increasing the output transistor size (gate width (W)) of the shift register circuit that drives the gate wiring G1 as compared with other shift register circuits. In general, it is known that when the gate width (W) of the output transistor is doubled, the driving capability is also doubled. However, when the gate width (W) is doubled only in the shift register circuit that drives the gate wiring G1, there is a problem that the layout ratio is lost due to the relationship with other shift register circuits.

(Embodiment 2)
FIG. 3 shows a configuration diagram of the image display apparatus according to the present embodiment. The image display device shown in FIG. 3 is basically the same as the image display device shown in FIG. 1 except that a shift register circuit for driving the gate wiring G1 is not provided and the output of the level shifter circuit 8 is directly gated. The difference is that the wiring G1 is driven. That is, in the image display device shown in FIG. 3, the start signal STVO that is the output of the level shifter circuit 8 is used as the gate signal SROUTO1 for driving the gate wiring G1, and is also input to the IN terminal of the shift register circuit SRCO2 in the next stage. The In the image display device shown in FIG. 3, the same components as those in the image display device shown in FIG.

  Next, FIG. 4 shows a timing chart of the image display apparatus shown in FIG. In the timing chart shown in FIG. 4, since the start signal STVO drives the gate wiring G1, the clock signal CKVO is not active until the period t4. Therefore, in the timing chart shown in FIG. 4, it is not necessary to activate the clock signal CKVO in the periods t0 and t1 as shown in FIG. 27, and the image display device shown in FIG. 3 is synchronized in each vertical period (one frame). The gate driver circuits 2 and 3 can be driven only by signals. In the timing chart shown in FIG. 4, unlike the case of FIG. 2, the start signal STVO is used as an output pulse for driving the gate wiring G 1, so that the falling edge of the start signal STVO and the gate wiring G 1 The output pulse falls at the same timing.

  In the image display device shown in FIG. 25, when the output pulse for driving the gate line G1 is set to two horizontal periods (2H), the start signal STVO supplied to the shift register circuit SRCO1 is set to be two horizontal periods (2H) before. It had to be in an active state during the period t-2 (timing chart shown in FIG. 27). Therefore, in the image display apparatus shown in FIG. 25, the gate driver circuits 2 and 3 cannot be driven only by the synchronization signal in each vertical period (one frame).

  However, in the image display device shown in FIG. 3, since the gate line G1 is directly driven by the start signal STVO, it is not necessary to supply the start signal STVO in advance for the output pulse of the gate line G1. Therefore, in the image display device shown in FIG. 3, the gate driver circuits 2 and 3 can be driven only by the synchronization signal in each vertical period (one frame).

  In the image display device shown in FIG. 3, an output pulse for driving the gate wiring G1 is supplied from the level shifter circuit 8 of an external circuit provided other than the substrate on which the pixels 4 are formed. Therefore, the level shifter circuit 8 of the external circuit can be formed on a single crystal silicon substrate or the like, and a circuit having a higher driving ability than that formed on amorphous silicon can be designed with a degree of freedom.

(Modification)
FIG. 5 shows a configuration diagram of an image display apparatus according to a modification of the present embodiment. In the image display device shown in FIG. 5, unlike the image display device shown in FIG. 3, the shift register circuit SRCE1 for driving the gate wiring G2 is not provided, and the output of the level shifter circuit 8 directly drives the gate wiring G2. . That is, in the image display device shown in FIG. 5, the start signals STVO and STVE that are the outputs of the level shifter circuit 8 are used as the gate signals SROUTO1 and SROUTE1 for driving the gate wirings G1 and G2, respectively, and the shift register circuit of the next stage. The signals are input to the IN terminals of SRCO2 and SRCE2, respectively. In the image display device shown in FIG. 5, the same components as those in the image display device shown in FIG.

  Next, FIG. 6 shows a timing chart of the image display device shown in FIG. In the timing chart shown in FIG. 6, since the start signal STVO drives the gate wiring G1, the clock signal CKVO is not active until the t4 period. In the timing chart shown in FIG. 6, since the start signal STVE drives the gate wiring G2, the clock signal CKVE is not active until the period t5. Therefore, even in the image display device shown in FIG. 5, the gate driver circuits 2 and 3 can be driven only by the synchronization signal in each vertical period (one frame). In the timing chart shown in FIG. 6, unlike the case of FIG. 2, the start signals STVO and STVE are used as output pulses for driving the gate wirings G1 and G2, so that the falling edge of the start signal STVO and the gate The fall of the output pulse of the wiring G1, the fall of the start signal STVE, and the fall of the output pulse of the gate wiring G2 have the same timing.

  As described above, the image display device according to the present embodiment has the effect that the gate wiring activation period (selection period) is the same in all gate wirings in addition to the effects of the first embodiment. Yes.

(Embodiment 3)
FIG. 7 shows a configuration diagram of the image display apparatus according to the present embodiment. The image display apparatus shown in FIG. 7 has a configuration in which the first embodiment and the second embodiment are combined. That is, the gate driver circuit 2 shown in FIG. 7 employs the configuration of the second embodiment in which the shift register circuit for driving the gate wiring G1 is not provided and the output of the level shifter circuit 8 directly drives the gate wiring G1. On the other hand, in the gate driver circuit 3 shown in FIG. 7, the shift register circuit for driving the gate wiring G2 has a two-circuit (SRCE1A, SRCE1B) configuration, and the configuration of the first embodiment is adopted. In the image display apparatus shown in FIG. 7, the same components as those in the image display apparatus shown in FIG.

  Next, FIG. 8 shows a timing chart of the image display device shown in FIG. In the timing chart shown in FIG. 8, since the start signal STVO drives the gate wiring G1, the clock signal CKVO is not active until the period t4. In the timing chart shown in FIG. 8, since the start signal STVE is active during the period t0 and t1, the clock signal CKVE is active only during the period t2. Therefore, in the timing chart shown in FIG. 8, based on the clock signal CKVE, the output pulse for driving the gate wiring G2 is also active only during the period t2.

  In the timing chart shown in FIG. 8, the output pulse of the gate line G2 is one horizontal period. However, the image display device shown in FIG. 7 uses only the synchronizing signal in each vertical period (one frame) and the gate driver circuits 2 and 3 Can be driven. In the timing chart shown in FIG. 8, the start signal STVO and the clock signal CSTVE have the same phase.

  As described above, in the image display device according to the present embodiment, in addition to the effects of the second embodiment, the start signal STVO and the clock signal CSTVE have the same phase, so that the start signal can be integrated into one line. Therefore, the control signal can be reduced. When the gate driver circuits 2 and 3 are arranged on both sides as shown in FIG. 7, the bus wiring of the start signal cannot be physically reduced. However, if the gate driver circuits 2 and 3 are arranged on one side, the bus wiring 1 This can be reduced, and the layout area of the circuit can be reduced.

  In the image display device according to the present embodiment, the second embodiment is applied to the gate wiring G1 and the first embodiment is applied to the gate wiring G2. However, the present invention is not limited to this, and the configuration is reversed. May be.

(Embodiment 4)
FIG. 9 shows a configuration diagram of the image display apparatus according to the present embodiment. The image display device shown in FIG. 9 has a configuration in which the clock signal of the image display device of FIG. 1 shown in Embodiment 1 is changed from four phases to eight phases. Therefore, in the image display device shown in FIG. 9, two circuits (SRC1-1A, SRC1-1B) are provided as shift register circuits for driving the gate wiring G1, and two circuits (SRC2-) are provided as shift register circuits for driving the gate wiring G2. 1A, SRC2-1B).

  In the image display device shown in FIG. 9, since the clock signal is made into eight phases, the shift signal circuit SRC1 driven by the start signal STV1, the clock signals CKV1, and CKVB1 in the gate driver circuit 2, the start signal STV2, and the clock signal CKV2, And a shift register circuit SRC2 driven by CKVB2. Similarly, in the image display device shown in FIG. 9, in the gate driver circuit 3, the shift register circuit SRC3 driven by the start signal STV3, the clock signals CKV3, CKVB3, and the shift register circuit driven by the start signal STV4, the clock signals CKV4, CKVB4. SRC4. In the image display apparatus shown in FIG. 9, the same components as those in the image display apparatus shown in FIG.

  Next, FIG. 10 shows a timing chart of the image display device shown in FIG. In the timing chart shown in FIG. 10, similarly to FIG. 2, the input image signal, the source signal, the control signal of the gate driver circuit, and the output pulse (gate signal) to the gate wiring are shown, and the period from t0 to tn (not shown) is shown. 1) is one vertical period (one frame). However, since the clock signal is divided into eight phases, the control signal of the gate driver circuit shown in FIG. 10 is composed of start signals STV1 to STV4, clock signals CKV1 to CKV4, and CKVB1 to CKV4.

  In the timing chart shown in FIG. 10, the output pulse of the gate line G1 is 1 horizontal period (1H), the output pulse of the gate line G2 is 2 horizontal periods (2H), and the output pulse of the gate line G3 is 3 horizontal periods (3H ), The clock signals CKV1 to CKV4 are controlled. Therefore, the image display device shown in FIG. 9 can drive the gate driver circuits 2 and 3 only with the synchronization signal in each vertical period (one frame).

  As described above, the image display apparatus according to the present embodiment has the effect of multi-phase clock signals in addition to the effect of the first embodiment. Specifically, the effects of multi-phase are that the driving frequency of the clock signal is reduced, the number of TFTs connected to one clock signal line is reduced and the load is reduced, and the driving frequency and the load are reduced. There is a point that power consumption can be reduced. Further, when the drive frequency is lowered, the shift register circuit can be charged for a long period of time, the size of the transistors constituting the circuit can be reduced, and the layout area of the circuit can be reduced.

  In the image display device according to the present embodiment, the clock signal is multiphased from 4 phases to 8 phases, but the present invention is not limited to this, and the number of phases is increased to 16 or more. It may be configured.

(Modification 1)
FIG. 11 shows a configuration diagram of an image display apparatus according to a modification of the present embodiment. The image display device shown in FIG. 11 has a configuration in which the clock signal of the image display device shown in FIG. 3 shown in Embodiment 2 is changed from four phases to eight phases. Therefore, in the image display device shown in FIG. 11, the gate wiring G1 is driven directly by the start signal STV1, the gate wiring G2 is driven by the start signal STV2, the gate wiring G3 is driven by the start signal STV3, and the gate wiring G4 is driven by the start signal STV4. . Note that the gate wiring G5 and subsequent gates are driven using a shift register circuit.

  Next, FIG. 12 shows a timing chart of the image display device shown in FIG. In the timing chart shown in FIG. 12, the output signal of the gate wiring G1 is set to two horizontal periods (2H) by setting the start signal STV1 to two horizontal periods (2H) of t0 and t1 periods. In the timing chart shown in FIG. 12, the output signal of the gate wiring G2 is set to 3 horizontal periods (3H) by setting the start signal STV2 to 3 horizontal periods (3H) from t0 to t2. As a result, even in the image display device according to this modification, the gate driver circuits 2 and 3 can be driven only by the synchronization signal in each vertical period (one frame).

  As described above, the image display apparatus according to the present embodiment has the effect of multi-phase clock signals in addition to the effect of the second embodiment.

(Modification 2)
FIG. 13 shows a configuration diagram of an image display apparatus according to another modification of the present embodiment. The image display device shown in FIG. 13 has a configuration in which the clock signal of the image display device in FIG. 5 shown in Embodiment 3 is changed from four phases to eight phases. Therefore, in the image display device shown in FIG. 13, the gate wiring G1 is directly driven by the start signal STV1, and the gate wiring G2 is directly driven by the start signal STV2.

  In the image display device shown in FIG. 13, two shift register circuits (SRC3-1A and SCR3-1B) for driving the gate line G3 and two shift register circuits (SRC4-1A) for driving the gate line G4 are used. , SCR4-1B). In the image display device shown in FIG. 13, the shift register circuits SRC3-1A and SCR3-1B are driven by the start signal STV1, and the shift register circuits SRC4-1A and SCR4-1B are driven by the start signal STV2. Compared with the image display devices indicated by 9 and 11, the lines of the start signals STV3 and STV4 can be reduced.

  Next, a timing chart of the image display device shown in FIG. 13 is shown in FIG. In the timing chart shown in FIG. 14, the output signal of the gate wiring G1 is set to two horizontal periods (2H) by setting the start signal STV1 to two horizontal periods (2H) of t0 and t1 periods. In the timing chart shown in FIG. 14, the output signal of the gate wiring G2 is set to two horizontal periods (2H) by setting the start signal STV4 to two horizontal periods (2H) of t1 and t2. Further, in the timing chart shown in FIG. 14, the clock signals CKV3 and CKV4 are controlled so that the output pulse of the gate line G3 is two horizontal periods (2H) and the output pulse of the gate line G4 is two horizontal periods (2H). . As a result, even in the image display device according to this modification, the gate driver circuits 2 and 3 can be driven only by the synchronization signal in each vertical period (one frame).

  As described above, the image display apparatus according to the present embodiment has the effect of making the clock signal more multiphase and the effect of reducing the lines of the start signals STV3 and 4 in addition to the effect of the third embodiment.

(Embodiment 5)
In the image display device according to the above-described embodiment, as shown in FIG. 15, the pixel array 1 has pixels 4 of m columns × n rows, and one pixel is constituted by three pixels (subpixels) 4 of RGB. It was the composition to do. That is, in the image display device according to the above-described embodiment, the resolution in the horizontal direction is m / 3 (RGB) and the resolution in the vertical direction is n. For this reason, in the image display device according to the above-described embodiment, the image data signal is transferred by the amount of horizontal resolution × 3 (RGB) within one horizontal period.

  However, the image display device according to the present invention is not limited to the configuration shown in FIG. 15, and may have a configuration in which the resolution in the vertical direction is larger than the number of rows (number of gate wirings). For example, a configuration in which one row of pixels 4 is driven by two gate wirings as in the pixel array 1 shown in FIG. 16 or a pixel 4 of the same color in the same gate wiring as in the pixel array 1 shown in FIG. A configuration in which one pixel is configured by driving and three gate wirings may be employed. The configuration shown in FIG. 16 is described in detail in “A-Si Gate Driver Integration with Time Shared Data Driving”, IWD'05, AMD P-7, with a horizontal resolution of m / 2 lines and a vertical direction. The resolution is n / 2. On the other hand, the configuration shown in FIG. 17 is described in detail in Non-Patent Document 1 described above, and the resolution in the horizontal direction is m and the resolution in the vertical direction is n / 3.

  In the configuration shown in FIG. 16, when the circuit configuration of the four-phase clock signal shown in FIG. 25 is adopted for the shift register circuit for driving the gate wiring, a timing chart as shown in FIG. 18 is obtained. Note that the image data signal is transferred by the resolution in the horizontal direction × 3 (RGB) within one horizontal period. Further, in the configuration shown in FIG. 16, when the circuit configuration of the 8-phase clock signal shown in FIG. 19 is adopted for the shift register circuit for driving the gate wiring, a timing chart as shown in FIG. 20 is obtained.

  When the configuration shown in FIG. 16 is adopted, the time for writing the image data signal to the pixel by one gate wiring is shorter than one horizontal period. Therefore, as shown in FIG. 18, the synchronization signal in each vertical period (one frame) Only by this, the gate driver circuits 2 and 3 can be easily driven. However, even when the configuration shown in FIG. 16 is adopted, when a circuit configuration of clock signals of eight phases or more is adopted, the gate driver circuit is formed only by the synchronization signal in each vertical period (one frame) as shown in FIG. 2 and 3 cannot be driven.

  Therefore, in the image display device according to the present embodiment, when the configuration shown in FIG. 16 is adopted, the circuit configuration shown in FIG. 9 or FIG. The gate driver circuits 2 and 3 can be driven only by the synchronization signal in the frame. Specifically, when the circuit configuration shown in FIG. 11 is adopted in the configuration shown in FIG. 16, the gate wirings G1 to G4 are directly driven by the start signals STV1 to STV4. Therefore, as shown in the timing chart of FIG. The gate driver circuits 2 and 3 can be driven only by the synchronization signal in (one frame).

  Similarly, in the configuration shown in FIG. 17, when the circuit configuration of the four-phase clock signal shown in FIG. 25 is adopted for the shift register circuit for driving the gate wiring, a timing chart as shown in FIG. 22 is obtained. Note that the image data signal is transferred by the resolution in the horizontal direction × 3 (RGB) within one horizontal period. Further, in the configuration shown in FIG. 17, when the circuit configuration of the 8-phase clock signal shown in FIG. 19 is adopted for the shift register circuit for driving the gate wiring, a timing chart as shown in FIG. 23 is obtained.

  When the configuration shown in FIG. 17 is adopted, the time for writing the image data signal to the pixel by one gate wiring is shorter than one horizontal period. Therefore, as shown in FIG. 22, the synchronization signal in each vertical period (one frame) Only by this, the gate driver circuits 2 and 3 can be easily driven. However, even when the configuration shown in FIG. 17 is adopted, if a circuit configuration of clock signals of eight phases or more is adopted, the gate driver circuit can be formed only with the synchronization signal in each vertical period (one frame) as shown in FIG. 2 and 3 cannot be driven.

  Therefore, in the image display device according to the present embodiment, when the configuration shown in FIG. 17 is adopted, the circuit configuration shown in FIG. 9 or FIG. The gate driver circuits 2 and 3 can be driven only by the synchronization signal in the frame. Specifically, when the circuit configuration shown in FIG. 11 is adopted in the configuration shown in FIG. 17, the gate wirings G1 to G4 are directly driven by the start signals STV1 to STV4. Therefore, as shown in the timing chart of FIG. The gate driver circuits 2 and 3 can be driven only by the synchronization signal in (one frame).

  Note that in the timing charts described in this application including FIGS. 21 and 24, in order to facilitate understanding of the operation, all the potentials of the clock signals CKV1 to CKV4 and CKVB1 to CKVB4 before the data enable signal rise are set to “L”. Yes. However, since the change in the clock signals CKV1 to CKV4 and CKVB1 to CKVB1 to CKV4 until the start signal is input does not affect the operation of the shift register circuit, the data enable for the operation of refreshing the node in the circuit, etc. The potentials of the clock signals CKV1 to CKV4 and CKVB1 to CKVB4 before the signal rises may be changed.

1 is a configuration diagram of an image display device according to Embodiment 1 of the present invention. 3 is a timing chart of the image display device according to the first embodiment of the present invention. It is a block diagram of the image display apparatus which concerns on Embodiment 2 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 2 of this invention. It is a block diagram of the image display apparatus which concerns on the modification of Embodiment 2 of this invention. It is a timing chart of the image display apparatus which concerns on the modification of Embodiment 2 of this invention. It is a block diagram of the image display apparatus which concerns on Embodiment 3 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 3 of this invention. It is a block diagram of the image display apparatus which concerns on Embodiment 4 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 4 of this invention. It is a block diagram of the image display apparatus which concerns on the modification 1 of Embodiment 4 of this invention. It is a timing chart of the image display apparatus which concerns on the modification 1 of Embodiment 4 of this invention. It is a block diagram of the image display apparatus which concerns on the modification 2 of Embodiment 4 of this invention. It is a timing chart of the image display apparatus which concerns on the modification 2 of Embodiment 4 of this invention. It is a figure for demonstrating the pixel structure of the image display apparatus which concerns on Embodiment 5 of this invention. It is a figure for demonstrating the pixel structure of the image display apparatus which concerns on Embodiment 5 of this invention. It is a figure for demonstrating the pixel structure of the image display apparatus which concerns on Embodiment 5 of this invention. It is a timing chart of the image display apparatus used as the premise of Embodiment 5 of this invention. It is a block diagram of the image display apparatus used as the premise of Embodiment 5 of this invention. It is a timing chart of the image display apparatus used as the premise of Embodiment 5 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 5 of this invention. It is a timing chart of the image display apparatus used as the premise of Embodiment 5 of this invention. It is a timing chart of the image display apparatus used as the premise of Embodiment 5 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 5 of this invention. It is a block diagram of the image display apparatus used as the premise of this invention. 3 is a timing chart of the image display apparatus as a premise of the present invention. 3 is a timing chart of the image display apparatus as a premise of the present invention.

Explanation of symbols

  1 pixel array, 2, 3 gate driver circuit, 4 pixels, 5 source driver, 6 power supply circuit, 7 timing generation circuit, 8 level shifter circuit.

Claims (6)

A plurality of pixels arranged in a matrix;
A gate line and a source line connected to each of the pixels;
An image display device comprising a gate driver circuit for supplying a gate signal to the connected gate wiring on the same substrate,
The gate driver circuit includes a shift register circuit having a plurality of stages for sequentially outputting the gate signal to each of the plurality of gate wirings,
A part of the selection period of the gate signal supplied to the adjacent gate wiring overlaps, and the selection period of the gate signal supplied to at least one of the gate wirings is supplied to the other gate wiring. An image display device, wherein a start signal is supplied to the shift register circuit at a timing after the start position of the image data signal supplied to the image display device, the start signal being shorter than the selection period of the gate signal. The image display device according to claim 1,
The image display device, wherein the gate driver circuit directly drives at least one of the gate wirings with a signal supplied from outside. The image display device according to claim 1 or 2,
In the gate driver circuit, an output transistor that drives the gate wiring to which the gate signal of the selection period shorter than the other gate wiring is supplied has a higher driving capability than the output transistor that drives the other gate wiring. An image display device characterized by that. The image display device according to claim 1 or 2,
The image display device, wherein the gate driver circuit assigns a plurality of stages of the shift register circuit to the gate wiring to which the gate signal of the selection period shorter than the other gate wiring is supplied. A plurality of pixels arranged in a matrix;
A gate line and a source line connected to each of the pixels;
An image display device comprising a gate driver circuit for supplying a gate signal to the connected gate wiring on the same substrate,
The gate driver circuit includes a shift register circuit having a plurality of stages for sequentially outputting the gate signal to each of the plurality of gate wirings,
A part of the selection period of the gate signal supplied to the adjacent gate wirings overlaps, and at least one of the gate wirings is directly driven by a signal supplied from the outside, thereby being supplied to the image display device. An image display device, wherein a start signal is supplied to the shift register circuit at a timing after the head position of the image data signal. A method for driving an image display device, comprising:
The image display device includes:
A plurality of pixels arranged in a matrix;
A gate line and a source line connected to each of the pixels;
A gate driver circuit for supplying a gate signal to the connected gate wiring is provided on the same substrate,
The shift register circuit provided in the gate driver circuit sequentially outputs the gate signal to each of the plurality of gate wirings,
A part of the selection period of the gate signal supplied to the adjacent gate wiring overlaps, and the selection period of the gate signal supplied to at least one of the gate wirings is supplied to the other gate wiring. Driving the image display device, wherein the start signal is supplied to the shift register circuit at a timing after the start position of the image data signal supplied to the image display device, shorter than the selection period of the gate signal. Method.

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