JP2009019897A - Flow detection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flow detection device capable of reducing detection errors by suppressing each temperature change of a resistor for setting the conversion rate and a capacitor for conversion. <P>SOLUTION: This flow detection device 10 is constituted of a bridge circuit 11, a V/F conversion circuit 19, or the like. In the V/F conversion circuit 19, an analog signal outputted from the bridge circuit 11 is converted into a current, and a capacitor 18 is charged by the current. Meanwhile, the capacitor 18 is discharged, each time a charge voltage of the capacitor 18 reaches a prescribed voltage. The V/F conversion circuit 19 outputs a digital signal, having a frequency corresponding to the analog signal based on the charge voltage of the capacitor 18. Here, the conversion rate of V/I conversion is set by the resistance value of the resistor 17, and the resistor 17 and the capacitor 18 are mounted separately, as long as a heat mitigation domain portion for mitigating heat transfer from a power transistor TR1 on a ceramic substrate 22 on which the bridge circuit 11 and the V/F conversion circuit 19 are mounted. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a flow rate detection device including a thermal flow meter, and more particularly to a flow rate detection device that detects an intake air amount of an internal combustion engine.

  Conventionally, a flow rate detection device including a flow rate detection circuit and a V / F conversion circuit (voltage / frequency conversion circuit) is known (see, for example, Patent Document 1). In such a flow rate detection device, an analog signal corresponding to the flow rate of the fluid to be detected is output by the flow rate detection circuit, and this analog signal is converted into a digital signal having a frequency corresponding to the same signal by the V / F conversion circuit. The

  The flow rate detection circuit includes a temperature sensitive resistor installed in the fluid flow path and a transistor provided in series with the temperature sensitive resistor, and maintains the temperature sensitive resistor at a predetermined temperature. It is known to output an analog signal corresponding to the power supplied to the temperature sensitive resistor while adjusting the power supply to the temperature sensitive resistor with the transistor.

  The V / F conversion circuit includes a V / I conversion unit that converts an analog signal output from the flow rate detection circuit into a current, and a conversion rate setting resistor that defines a conversion rate in the V / I conversion unit. And a conversion capacitor that is charged by the current converted by the V / I conversion unit, and an I / F conversion unit that discharges the capacitor every time the charging voltage of the conversion capacitor reaches a predetermined voltage. It has been. In this V / F conversion circuit, a digital signal having a frequency corresponding to the detection signal is output based on a change in the charging voltage of the conversion capacitor.

On the other hand, from the viewpoint of downsizing the flow rate detection device, it is conceivable that at least a part of the flow rate detection circuit excluding the temperature sensitive resistor and the V / F conversion circuit are mounted on the same circuit board.
Japanese Patent No. 3808038

  However, when the resistance value of the resistor and the capacitance of the capacitor change due to the temperature change of the conversion rate setting resistor and the conversion capacitor, a detection error occurs due to the change of the conversion rate in the V / F conversion circuit. . In particular, when at least a part of the flow rate detection circuit excluding the temperature sensitive resistor and the V / F conversion circuit are mounted on the same circuit board as described above, the conversion rate is set by the heat generated by the elements constituting these circuits. Since the temperature change of the resistor and the conversion capacitor becomes large, the detection error due to the temperature change may increase.

  The present invention has been made to solve the above-described problem, and mainly provides a flow rate detection device that reduces detection errors by suppressing temperature changes of a conversion rate setting resistor and a conversion capacitor. It is the purpose.

  Hereinafter, means for solving the above-described problems and the effects thereof will be described.

  The invention described in claim 1 includes a temperature sensitive resistor installed in the fluid flow path and a transistor provided in series with the temperature sensitive resistor, and maintains the temperature sensitive resistor at a predetermined temperature. A flow rate detection circuit that outputs an analog signal corresponding to the supply power to the temperature sensitive resistor while adjusting the power supplied to the temperature sensitive resistor as much as possible, and an analog signal output by the flow rate detection circuit as a current A V / I converter that converts and outputs the voltage, a conversion rate setting resistor that defines the conversion rate in the V / I converter, and a converter that is charged by the current output from the V / I converter A capacitor and an I / F converter that discharges the conversion capacitor every time the charging voltage of the conversion capacitor reaches a predetermined voltage, and responds to the analog signal based on a change in the charging voltage of the conversion capacitor. And a conversion circuit that outputs a digital signal of the frequency. According to this configuration, a digital signal having a frequency corresponding to the flow rate of the fluid flowing through the flow path is output.

  By the way, the heat generation amount of the transistor through which the supply current to the temperature sensitive resistor flows is larger than the other elements constituting the flow rate detection circuit and the elements constituting the V / F conversion circuit. The inventor pays attention to this point, and when the transistor and the conversion circuit are mounted on the same circuit board, the conversion rate setting resistor and the conversion capacitor are separated by a thermal relaxation region that reduces heat transfer from the transistor. I implemented it. Thereby, the temperature change of the conversion rate setting resistor and the conversion capacitor due to the heat generation of the transistor can be suppressed, and the detection error due to the temperature change can be reduced.

  According to the second aspect of the present invention, the V / I converter and the I / F converter are integrated as one integrated circuit, and the integrated circuit is arranged between the conversion rate setting resistor and the conversion capacitor and the transistor. Has been. Here, it is conceivable that the heat capacity of the integrated circuit in which the V / I converter and the I / F converter are integrated is increased. In this case, when the integrated circuit is arranged as described above, the ambient temperature of the integrated circuit is leveled, and the temperature difference between the integrated circuit, the conversion rate setting resistor, and the conversion capacitor is reduced. Thus, by increasing the correlation with respect to the temperatures of the integrated circuit, the conversion rate setting resistor, and the conversion capacitor, temperature compensation of the detection error due to the temperature change is facilitated.

  In the invention described in claim 3, the circuit board has a rectangular shape. A conversion rate setting resistor, a conversion capacitor, and a transistor are disposed in the vicinity of one side and the other side of the circuit board, respectively. Thus, by separating the conversion rate setting resistor and the conversion capacitor from the transistor, the detection error due to the temperature change can be reduced.

  The invention according to claim 4 further includes a heat dissipating member in the invention according to claim 3. The heat radiating plate is thermally connected to the transistor and extends along one side close to the transistor of the rectangular circuit board and the other side adjacent to the one side. Further, a conversion rate setting resistor and a conversion capacitor are arranged on the circuit board, avoiding a portion of the circuit board facing the heat dissipation member. According to this configuration, the conversion rate setting resistor and the conversion capacitor can be separated from the transistor and the heat dissipation plate while providing the heat dissipation plate having a large heat dissipation area. That is, while the temperature rise of the transistor is suppressed by the heat radiating plate, the temperature change of the conversion rate setting resistor and the conversion capacitor due to the heat received from the heat radiating plate can be suppressed.

  The invention according to claim 5 further includes a heat sink in the invention according to any one of claims 1 to 3. The heat radiating plate is thermally connected to the transistor and is provided to face a part of the circuit board. Then, a conversion rate setting resistor and a conversion capacitor are arranged on the circuit board, avoiding a portion of the circuit board facing the heat dissipation member. According to this configuration, the conversion rate setting resistor and the conversion capacitor can be separated from the transistor and the heat dissipation plate while providing the heat dissipation plate. That is, while the temperature rise of the transistor is suppressed by the heat radiating plate, the temperature change of the conversion rate setting resistor and the conversion capacitor due to the heat received from the heat radiating plate can be suppressed.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of the invention will be described with reference to the drawings. The present embodiment embodies the present invention as a flow rate detection device for detecting the intake air amount of an in-vehicle engine, and the detailed configuration thereof will be described below.

  First, a schematic configuration of the flow rate detection device 10 according to the present embodiment will be described with reference to FIG. The flow rate detection device 10 includes a bridge circuit 11, an energization control operational amplifier OP1, a power transistor TR1, a V / F conversion circuit module 16, and the like. An ECU 20 is connected to the flow rate detection device 10, and the ECU 20 calculates an intake air amount of the engine based on a detection signal output from the flow rate detection device 10.

  Specifically, a hot wire 12 and a cold wire 13 are provided in an intake pipe (intake passage) 21 of the engine shown in FIG. The hot wire 12 and the cold wire 13 are heat-sensitive resistance elements (elements whose resistance values change according to temperature), and form the bridge circuit 11 together with the resistors 14 and 15. The hot wire 12 as a temperature sensitive resistor is also a heating resistor element that generates heat when energized.

  An energization control operational amplifier OP1 is connected to the output terminal of the bridge circuit 11, and a power transistor TR1 is connected to the energization control operational amplifier OP1. The power transistor TR1 is connected to the power supply terminal of the bridge circuit 11. The conduction control operational amplifier OP1 adjusts the power supplied to the hot wire 12 through the transistor TR1 by outputting an adjustment signal to the power transistor TR1 so that the unbalanced voltage of the bridge circuit 11 becomes zero. To do.

  Thereby, the temperature of the hot wire 12 is kept at a predetermined temperature regardless of the intake air amount of the engine. Here, as described above, the supply power required to maintain the temperature of the hot wire 12 correlates with the intake air amount of the engine. Therefore, a voltage corresponding to the intake air amount of the engine is generated at the output terminal of the bridge circuit 11. A circuit including the bridge circuit 11, the operational amplifier OP1, and the power transistor TR1 corresponds to a “flow rate detection circuit”.

  A V / F conversion circuit module 16 is connected to the output terminal on the hot wire 12 side of the bridge circuit 11. The V / F conversion circuit module 16 forms a V / F conversion circuit 19 as a conversion circuit together with a conversion rate setting resistor 17 and a conversion capacitor 18, and an analog signal (engine) output from the bridge circuit 11. Output a digital signal having a frequency corresponding to the intake air amount.

  An ECU 20 is connected to the V / F conversion circuit module 16. The ECU 20 is an electronic control unit mainly composed of a known microcomputer provided with a CPU, a memory, and the like. The memory stores various programs and parameters. The CPU controls each part of the engine by executing a program stored in the memory. In this engine control, the ECU 20 calculates the intake air amount of the engine as one of the parameters for engine control based on the detection signal output from the V / F conversion circuit module 16.

  The power transistor TR1, the operational amplifier OP1, the V / F conversion circuit module 16, the conversion rate setting resistor 17, the conversion capacitor 18, and the resistors 14 and 15 are mounted on a ceramic substrate 22 as a circuit substrate. ing. The ceramic substrate 22 is accommodated in a housing (not shown), and the hot wire 12 and the cold wire 13 are attached to the housing so that a part thereof is exposed to the outside. The circuit board is not limited to a ceramic substrate.

  Next, the circuit configuration of the V / F conversion circuit 19 will be described with reference to FIG. The V / F conversion circuit module 16 converts the analog signal output by the bridge circuit 11 into a current and charges the conversion capacitor 18, and the charging voltage of the conversion capacitor 18 is set to a predetermined voltage. And an I / F converter 24 that discharges the capacitor 18 each time the capacitor 18 is reached.

  The V / I converter 23 is mainly composed of an operational amplifier OP2. The output terminal of the operational amplifier OP2 is connected to the base of an NPN transistor TR2, the negative input terminal is connected to the emitter of the NPN transistor TR2, and the positive input terminals have voltage dividing resistors 25 and 26. Is provided. The voltage dividing resistor 25 is connected to an input terminal (terminal for connecting the bridge circuit 11) 27, and the resistor 26 is connected to the ground. A PNP transistor TR3 is provided between the second power supply terminal 29 and the collector of the NPN transistor TR2. The base of the PNP transistor TR3 is connected to the collector of the NPN transistor TR2. On the other hand, the emitter of the NPN transistor TR2 is connected to an external resistance connection terminal (terminal for connecting the conversion rate setting resistor 17) 31.

  According to the above configuration, the emitter of the NPN transistor TR2 has the same potential as the positive input terminal of the operational amplifier OP2. As a result, the supply current I1 to the conversion rate setting resistor 17 by the PNP transistor TR3 is adjusted as shown in the following equation (1). In the following equation (1), Io is the current value of the supply current I1 to the conversion rate setting resistor 17, N is the voltage division ratio by the voltage dividing resistors 25 and 26, and Vin is output by the bridge circuit 11. The voltage of the analog signal, R, indicates the resistance value of the conversion rate setting resistor 17.

Io = N · Vin / R (1)
A PNP transistor TR4 is provided between the second power supply terminal 29 and the external capacitor connection terminal (terminal for connecting the conversion capacitor 18) 32. The base of the PNP transistor TR4 is connected to the collector of the NPN transistor TR2. Thus, since the PNP transistor TR4 operates in synchronization with the PNP transistor TR3, a current proportional to the supply current I1 from the PNP transistor TR3 is output by the PNP transistor TR4. In the following description, it is assumed that the supply current I2 from the PNP transistor TR4 is set to twice the supply current I1 to the conversion rate setting resistor 17 by the PNP transistor TR3 for convenience of description. However, the supply current I2 may be set to any multiple of the supply current I1.

  The I / F conversion unit 24 is configured mainly by the comparator COMP1. Specifically, the comparator COMP1 compares the charging voltage of the conversion capacitor 18 with a predetermined voltage (hereinafter referred to as “reference voltage”), and the conversion capacitor 18 is discharged based on the comparison result. ing.

  Specifically, an NPN transistor TR5 is connected to the output terminal of the comparator COMP1 via the resistor 33, and an external capacitor connection terminal 32 (emitter of the PNP transistor TR4) is connected to the positive input terminal thereof. A reference voltage setting circuit is connected to the negative input terminal. This reference voltage setting circuit includes voltage dividing resistors 34 and 35 connected to the third power supply terminal 30, and an NPN transistor TR6 provided between the resistor 35 and the ground. The base of the NPN transistor TR6 is connected to the output terminal of the comparator COMP1 via the resistor 36.

  According to the reference voltage setting circuit, when the NPN transistor TR6 is in the OFF state, the reference voltage is set to the voltage (Vcc3) of the third power supply terminal 30. On the other hand, when the NPN transistor TR6 is in the ON state, the voltage (Vcc3) of the third power supply terminal 30 is divided by the voltage dividing resistors 34 and 35, so that the reference voltage is lower than Vcc3. Is set. Hereinafter, the reference voltage set when the NPN transistor TR6 is in the off state is referred to as “Vhi”, and the reference voltage set when the NPN transistor TR6 is in the on state is referred to as “Vlo”.

  A discharge circuit (circuit for discharging the conversion capacitor 18) is connected to the collector of the NPN transistor TR5. Specifically, an NPN transistor TR7 provided between the external capacitor connection terminal 32 and the ground, and a PNP transistor TR8 provided between the second power supply terminal 29 and the base of the NPN transistor TR7, The NPN transistors TR9 and TR10 are connected to the base of the transistor TR7 in order to control on / off of the NPN transistor TR7.

  The base of the PNP transistor TR8 is connected to the collector of the NPN transistor TR2 of the V / I converter 23. On the other hand, the collectors of the NPN transistors TR9 and TR10 are connected to the collector of the PNP transistor TR8, the base of the NPN transistor TR9 is connected to the base of the NPN transistor TR7 and the collector of the PNP transistor TR8, and the NPN transistor TR10. Is connected to the collector of an NPN transistor TR5 through a resistor 37. In the following description, the collector current I3 in the ON state of the NPN transistor TR7 is set to four times the supply current I1 to the conversion rate setting resistor 17 by the PNP transistor TR3 for convenience of description. To do. However, the collector current I3 may be set to any multiple of the supply current I1.

  According to the configuration of the discharge circuit, when the NPN transistor TR10 is in the on state, the NPN transistor TR7 is turned off, so that the conversion current is supplied by the supply current I2 from the PNP transistor TR4 in the V / I converter 23. The capacitor 18 is charged. On the other hand, when the NPN transistor TR10 is in the off state, the NPN transistor TR7 is turned on. As a result, the supply current I2 from the PNP transistor TR4 of the V / I converter 23 and the discharge current I4 from the conversion capacitor 18 are obtained. Flows to the ground via the NPN transistor TR7.

  An open collector type output circuit is connected to the collector of the NPN transistor TR5. This output circuit comprises an NPN transistor TR11 and an NPN transistor TR12.

  Next, the operation of the V / F conversion circuit 19 will be described with reference to FIG. 3, (a) is the charging voltage of the conversion capacitor 18, (b) is the output of the comparator COMP1, (c) is ON / OFF of the NPN transistors TR5 and TR6, and (d) is the ON of the NPN transistor TR10. OFF, (e) indicates ON / OFF of the NPN transistor TR7.

  Immediately after the operation of the V / F conversion circuit 19 is started, the charging voltage of the conversion capacitor 18 is lower than Vlo, and the output of the comparator COMP1 is saturated negatively. As a result, the NPN transistor TR6 is turned off, and the reference voltage is set to Vhi on the high voltage side in the reference voltage setting circuit. Therefore, at the timing t1 when the charging voltage of the conversion capacitor 18 reaches Vlo for the first time after the operation of the V / F conversion circuit 19 is started, the reference voltage is set to Vhi, and the output of the comparator COMP1 is saturated negatively ( (Refer FIG. 3 (a), (b)). As a result, the NPN transistor TR10 is turned on and the NPN transistor TR7 is turned off (see FIGS. 3D and 3E). Therefore, the conversion capacitor 18 is supplied by the supply current I2 from the PNP transistor TR4. Is charged (see FIG. 3A).

  When the charging voltage of the conversion capacitor 18 rises to Vhi at timing t2, the comparator COMP1 is positively saturated. As a result, the NPN transistor TR6 is turned on (see FIG. 3C), and the reference voltage is set to Vlo on the low voltage side in the reference voltage setting circuit (see FIG. 3A). Since the NPN transistor TR10 is turned off and the NPN transistor TR7 is turned on (see FIGS. 3D and 3E), the conversion capacitor 18 is discharged (FIG. 3A). reference).

  When the charging voltage of the conversion capacitor 18 drops to Vlo at the timing t3, the comparator COMP1 is saturated again negatively (see FIGS. 3A and 3B). As a result, the NPN transistor TR6 is turned off (see FIG. 3C), and the reference voltage is set to Vhi on the low voltage side in the reference voltage setting circuit (see FIG. 3A). Further, since the NPN transistor TR10 is turned off and the NPN transistor TR7 is turned on (see FIGS. 3D and 3E), the conversion capacitor 18 is caused by the supply current I2 from the PNP transistor TR4. The battery is charged (see FIG. 3A).

  Thus, as a result of repeated charging and discharging of the conversion capacitor 18, the charging voltage of the capacitor 18 shows a triangular wave pulsating between Vlo and Vhi, and the output signal of the V / F conversion circuit 19 is the same charge. A square wave having the same cycle as the voltage cycle is shown (see cycle T shown in the following equation (2)). That is, the output signal of the V / F conversion circuit 19 becomes a digital signal having a frequency corresponding to the analog signal output from the bridge circuit 11 (see the frequency F shown in the following equation (3)). In the following equations (2) and (3), N, Vin, and R are the voltage dividing ratios of the voltage dividing resistors 25 and 26, respectively, and the voltage of the analog signal output from the bridge circuit 11 as in the equation (1). The resistance value of the conversion rate setting resistor 17 is shown. C represents the capacitance of the conversion capacitor 18.

T = C · (Vhi−Vlo) / Io (2)
F = N · Vin / (R · C · (Vhi−Vlo)) (3)
In this way, the detection signal of the intake air amount of the engine is digitized and transmitted to the ECU 20, so that an error caused by noise superimposed during the transmission (the intake air amount calculated in the ECU 20 and the actual intake air amount) Difference) can be reduced.

  Next, the configuration in the vicinity of the ceramic substrate 22 will be described in detail with reference to FIG. 4A is a plan view of the vicinity of the ceramic substrate 22, and FIG. 4B is a cross-sectional view taken along line A1-A1 of FIG. In FIG. 4, it is assumed that the energization control operational amplifier OP 1, the V / F conversion circuit module 16, the resistor 14, and the resistor 15 are integrated as one integrated circuit 41.

  The ceramic substrate 22 shown in FIG. 4 has a rectangular shape and is attached to the housing 42. Specifically, the ceramic substrate 22 is fixed to the housing 42 via an insulating resin member 44 with an adhesive 43 (see FIG. 4B). Here, a relatively large current supplied to the bridge circuit 11 flows through the power transistor TR1. Therefore, the amount of heat generated by the power transistor TR1 is larger than the amount of heat generated by other heat generating elements (for example, the integrated circuit 41) mounted on the ceramic substrate 22.

  Therefore, the heat radiating plate 45 is thermally connected to the power transistor TR1. That is, the thermal conductivity in the path through which the heat generated in the power transistor TR1 is transmitted to the heat radiating plate 45 is relatively high. Specifically, a heat radiating plate 45 is provided close to the power transistor TR1. Specifically, a heat radiating plate 45 is provided between the power transistor TR 1 and the housing 42. As a result, the heat generated in the power transistor TR1 is transmitted to the heat radiating plate 45 and radiated from the heat radiating plate 45, so that the temperature rise of the power transistor TR1 is reduced.

  The integrated circuit 41 may be a monolithic integrated circuit in which circuit elements formed on one semiconductor chip are connected by wiring such as an aluminum vapor deposition film, or a multi-chip module in which a plurality of semiconductor chips are connected. Alternatively, a hybrid integrated circuit in which a semiconductor chip and individual components such as resistors are connected may be used. Further, the integrated circuit 41 may be packaged or may be mounted on a bare chip.

  Incidentally, the conversion rate (conversion rate from the voltage of the input signal to the frequency of the output signal) in the V / F conversion circuit 19 described above is the resistance value R of the conversion rate setting resistor 17 and the capacitance of the conversion capacitor 18. Depends on C. Therefore, when the resistance value R and the capacitance C change due to the temperature change of the resistor 17 and the capacitor 18, the detection error increases.

  Therefore, in the present embodiment, first, in the ceramic substrate 22, the conversion rate setting resistor 17 and the conversion capacitor 18 are made to be a thermal relaxation region that relaxes heat transfer from the power transistor TR 1 that generates a relatively large amount of heat. It is mounted with a distance. Specifically, the conversion rate setting resistor 17 and the conversion capacitor 18 are arranged in the vicinity of the opposite side of the ceramic substrate 22 and the vicinity of the other side, respectively. Second, the integrated circuit 41 is disposed between the conversion rate setting resistor 17 and the conversion capacitor 18 and the power transistor TR1. Thirdly, a heat radiating plate 45 extending along one side of the ceramic substrate 22 is opposed to the peripheral part of one side where the power transistor TR1 is close.

  Next, the effect by this embodiment is demonstrated based on FIG. FIG. 5 is a drawing for explaining the temperature distribution on the ceramic substrate 22. Specifically, in FIG. 5, (a) is a diagram for explaining the temperature distribution according to the present embodiment, and (b) is a state (conversion) in which the arrangement of the integrated circuit 41 is different from that of the present embodiment. (C) is a diagram for explaining the temperature distribution in a state where the integrated circuit 41 is not disposed between the rate setting resistor 17 and the conversion capacitor 18 and the power transistor TR1. On the other hand, the temperature distribution in a state in which the arrangement of the integrated circuit 41 is changed in the same manner as in FIG. It is drawing for demonstrating. 5 (a) to 5 (c), the graph shown by a solid line shows the temperature distribution in the state of each drawing described above, and the graph shown by a broken line shows a state where no heat sink is provided in the state of each drawing mentioned above. The temperature distribution in FIG.

  According to FIGS. 5A to 5C, it can be seen that the temperature on the ceramic substrate 22 decreases as the distance from the power transistor TR1 increases. Therefore, by separating the conversion rate setting resistor 17 and the conversion capacitor 18 from the power transistor TR1 as described above, the temperature change of the resistor 17 and the capacitor 18 due to the heat generation of the transistor TR1 is suppressed.

  Further, from comparison between FIGS. 5A and 5B, by arranging the integrated circuit 41 between the conversion rate setting resistor 17 and the conversion capacitor 18 and the power transistor TR1, these resistors 17 are arranged. It can be seen that the temperature difference between the capacitor 18 and the integrated circuit 41 is reduced. This is because the heat capacity of the integrated circuit 41 is relatively large and the temperature around the integrated circuit 41 is leveled.

  5 (b) and 5 (c), the heat radiation plate 45 extending along one side is opposed to the peripheral portion of one side where the power transistor TR1 of the ceramic substrate 22 is close to the heat radiation plate 45. It can be seen that the change in temperature of the conversion rate setting resistor 17 and the conversion capacitor 18 due to heat reception is suppressed. Specifically, as shown in FIG. 5C, when the heat radiating plate 45 is opposed to the entire surface of the ceramic substrate 22, the temperature on the substrate 22 is leveled over the entire surface, but at a position away from the power transistor TR1. The temperature on the substrate 22 becomes relatively high as heat is received from the heat sink 45. On the other hand, when the heat radiation plate 45 extending along one side is opposed to the peripheral portion of one side of the ceramic substrate 22 where the power transistor TR1 is close, the amount of heat received from the heat radiation plate 45 is separated from the heat radiation plate 45. Therefore, the temperature on the substrate 22 at a position away from the transistor TR1 becomes relatively low. Therefore, by providing the heat radiating plate 45 as described above, it is possible to suppress temperature changes of the conversion rate setting resistor 17 and the conversion capacitor 18 due to heat received from the heat radiating plate 45.

  According to the embodiment described in detail above, the following excellent effects can be obtained.

  The conversion rate setting resistor 17 and the conversion capacitor 18 are separated from the power transistor TR1 that generates a relatively large amount of heat, and an integrated circuit is provided between the conversion rate setting resistor 17 and the conversion capacitor 18 and the power transistor TR1. 41 was placed. Thereby, since the temperature change of the conversion rate setting resistor 17 and the conversion capacitor 18 due to the heat generation of the power transistor TR1 is suppressed, the detection error due to this temperature change can be reduced.

  An integrated circuit 41 is disposed between the conversion rate setting resistor 17 and the conversion capacitor 18 and the power transistor TR1. As a result, the temperature difference among the integrated circuit 41, the conversion rate setting resistor 17, and the conversion capacitor 18 is reduced, so that the temperature compensation of the detection error caused by the temperature change is facilitated.

  Further, a heat radiating plate 45 extending along one side of the ceramic substrate 22 facing the power transistor TR1 is opposed to the peripheral part. That is, the ceramic substrate 22 was disposed on one side opposite to the conversion rate setting resistor 17 and the conversion capacitor 18. Thereby, while the temperature rise of power transistor TR1 is suppressed with the heat sink 45, the temperature change of the conversion rate setting resistor 17 and the conversion capacitor | condenser 18 accompanying the heat receiving from the heat sink 45 can be suppressed.

(Other embodiments)
The present invention is not limited to the description of the above embodiment, and may be implemented as follows, for example.

  In the above embodiment, the insulating resin member is provided between the power transistor TR1 and the heat radiating plate 45, but a member having high thermal conductivity may be provided therebetween. Specifically, as shown in FIG. 6, a solid pattern 46 may be formed on the back surface of the ceramic substrate 22 opposite to the surface on which the power transistor TR1 is mounted. As a result, the heat transfer coefficient from the power transistor TR1 to the heat radiating plate 45 is increased, so that the temperature rise of the power transistor TR1 can be suppressed.

  Moreover, in the said embodiment, the heat sink 45 extended along the one side was made to oppose the peripheral part of the one side where power transistor TR1 of the ceramic substrate 22 adjoins. However, as shown in FIG. 7, a heat radiating plate extending along one side of the ceramic substrate 22 adjacent to the power transistor TR <b> 1 and the peripheral part of the other side adjacent to the one side may be opposed. That is, even if the C-shaped heat sink is opposed to the three sides of the ceramic substrate 22 and the conversion rate setting resistor 17 and the conversion capacitor 18 are mounted on the portion not facing the heat sink near the other side. Good. Moreover, you may provide an L-shaped heat sink so that the said conditions may be satisfy | filled.

  According to this configuration, the conversion rate setting resistor 17 and the conversion capacitor 18 can be separated from the power transistor TR1 and the heat dissipation plate 45 while providing a heat dissipation plate having a large heat dissipation area. That is, while the temperature rise of the power transistor TR1 is effectively suppressed by the heat radiating plate 45, the temperature change of the conversion rate setting resistor 17 and the conversion capacitor 18 due to the heat received from the heat radiating plate 45 can be suppressed.

  In the above embodiment, the integrated circuit 41 is disposed between the conversion rate setting resistor 17 and the conversion capacitor 18. However, as long as the detection error of the flow rate detection device 10 can be reduced within the specification range, the integrated circuit 41 may not be disposed between the conversion rate setting resistor 17 and the conversion capacitor 18.

  In the above embodiment, the current-carrying control operational amplifier OP1, the V / F conversion circuit module 16, the resistor 14, and the resistor 15 are integrated as one integrated circuit 41. However, these may be integrated as a plurality of integrated circuits or may be individual devices. Further, the V / I conversion unit 23 and the I / F conversion unit 24 of the V / F conversion circuit module 16 may be integrated as different integrated circuits.

  Moreover, in the said embodiment, although the rectangular ceramic board | substrate 22 was illustrated as a circuit board, a circuit board may not be rectangular shape. Further, although the circuit configuration of the V / F conversion circuit 19 has been specifically shown and described, the circuit configuration is not limited to this.

  In the above embodiment, the flow rate detection device 10 that detects the intake air amount of the engine has been described. However, the detection target of the present invention is not limited to the intake air amount, and may be, for example, an engine exhaust amount or an annular flow rate of exhaust gas to the intake air.

The figure which shows the flow volume detection apparatus by this embodiment. The figure which shows the V / I conversion circuit by this embodiment. The timing chart which shows the action | operation of a V / I conversion circuit. (A) is a top view which shows the structure of the ceramic substrate vicinity of a flow volume detection apparatus, (b) is sectional drawing by the A1-A1 line of (a). The figure for demonstrating the effect of this embodiment. The figure for demonstrating the flow volume detection apparatus by other embodiment. The figure for demonstrating the flow volume detection apparatus by other embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Flow rate detection apparatus, 11 ... Bridge circuit (flow rate detection circuit), 12 ... Hot wire (temperature-sensitive resistor), 13 ... Cold wire, 14 ... Resistor, 15 ... Resistor, 16 ... Circuit module for conversion, 17 Conversion factor setting resistor, 18 Conversion capacitor, 19 V / F conversion circuit (conversion circuit), 20 ECU, 21 Intake pipe (fluid flow path), 22 Ceramic substrate (circuit board), 23 ... V / I converter, 24 ... I / F converter, 41 ... integrated circuit, 45 ... heat sink, 46 ... solid pattern, OP1 ... operation control operational amplifier (flow rate detection circuit), TR1 ... power transistor (flow rate detection circuit) , Transistor).

Claims (5)

A temperature sensing resistor installed in the fluid flow path and a transistor provided in series with the temperature sensing resistor, the supply to the temperature sensing resistor to keep the temperature sensing resistor at a predetermined temperature A flow rate detection circuit that outputs an analog signal corresponding to the power supplied to the temperature sensitive resistor while adjusting the power by the transistor;
A V / I converter that converts an analog signal output from the flow rate detection circuit into a current and outputs the current, a conversion rate setting resistor that sets a conversion rate in the V / I converter, and the V / I conversion A conversion capacitor that is charged by the current converted by the unit, and an I / F conversion unit that discharges the conversion capacitor every time the charging voltage of the conversion capacitor reaches a predetermined voltage. A conversion circuit that outputs a digital signal having a frequency corresponding to the analog signal based on a change in the charging voltage of
The transistor and the conversion circuit are flow rate detection devices mounted on the same circuit board,
The flow rate detecting device, wherein the conversion rate setting resistor and the conversion capacitor are mounted on the circuit board so as to be separated by a heat relaxation region for relaxing heat transfer from the transistor. The V / I converter and the I / F converter are integrated as one integrated circuit,
The flow rate detection device according to claim 1, wherein the integrated circuit is disposed between the conversion rate setting resistor, the conversion capacitor, and the transistor. The circuit board has a rectangular shape,
The flow rate detection device according to claim 1, wherein the conversion rate setting resistor, the conversion capacitor, and the transistor are arranged in the vicinity of one side and the other side of the circuit board, respectively. A heat dissipating member thermally connected to the transistor and extending along one side of the circuit board close to the transistor and the other side adjacent to the one side;
The flow rate detection device according to claim 3, wherein the conversion rate setting resistor and the conversion capacitor are arranged on the circuit board while avoiding a portion of the circuit board facing the heat dissipation member. A heat dissipating member thermally connected to the transistor and provided to face a part of the circuit board;
4. The flow rate detection device according to claim 1, wherein the conversion rate setting resistor and the conversion capacitor are disposed on the circuit board while avoiding a portion of the circuit board facing the heat dissipation member. 5. .

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