JP2009017141A - Programmable logic circuit device, programmable logic circuit reconfiguration method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a programmable logic circuit device capable of obtaining the most suitable performance using a software IP. <P>SOLUTION: The programmable logic circuit device includes a plurality of computing elements 10 each of which includes a first path to which a flip flop circuit 16 having a first clock signal inputted thereto is connected and a second path to which a lookup table 12 and a flip flop circuit 14 having a second clock signal inputted thereto are connected. The first path and second path are set per computing element 10. The computing elements 10 are so connected that two computing elements 10 mounted as applications are in both ends and a plurality of computing elements 10 serving as buffers are in the middle. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a programmable logic circuit device, a programmable logic circuit reconfiguration method, and a program that directly implement a program by hardware.

  A PLD (Programmable Logic Device) is known as a reconfigurable device that directly implements program execution by hardware (for example, Patent Document 1).

  The PLD changes the connection logic between logic circuits by giving logic data as a program, thereby obtaining an operation result in hardware. By performing the calculation using the PLD, the calculation result can be obtained at a higher speed than the calculation by the CPU (Central Processing Unit) mounted on the conventional general-purpose computer.

By the way, the reconfigurable device by the technique of patent document 1 is implement | achieved using hardware IP (Intellectual Property) from the reason that delay calculation is complicated and test design is difficult. Furthermore, according to the hardware IP, the best device in terms of performance and area can be created.
Japanese Patent No. 3540796

  However, with the hardware IP described above, customization for each user is difficult because the semiconductor vendor is limited. In order to overcome these disadvantages, it is appropriate to use software IP.

  The present invention has been made in view of the above problems, and an object thereof is to provide a programmable logic circuit device capable of obtaining optimum performance using software IP.

In order to achieve the above object, a programmable logic circuit device according to the first aspect of the present invention provides:
A first path to which the first flip-flop circuit for inputting the first clock signal is connected, and a second path to which the arithmetic unit and the second flip-flop circuit for inputting the second clock signal are connected A plurality of computing element elements comprising:
Path setting means for setting the first path and the second path for each computing element;
A plurality of computing element elements set in the first route or the second route by the route setting means at both ends, and a plurality of routes set by the previous route setting means in the first route or the second route. An element connection means for connecting the operation element with the operation element of
It is characterized by providing.

  For example, it further comprises period setting means for setting the period of the first clock signal and the second clock signal for each arithmetic element based on the number of arithmetic elements connected in the middle by the element connection means. Good.

  For example, the computing unit may include a lookup table and / or an ALU (Arithmetic Logic Unit).

The programmable logic circuit reconfiguration method according to the second aspect of the present invention includes:
A first path to which the first flip-flop circuit for inputting the first clock signal is connected, and a second path to which the arithmetic unit and the second flip-flop circuit for inputting the second clock signal are connected A programmable logic circuit reconfiguration method for changing the logical configuration of a programmable logic circuit comprising:
A path setting step for setting the first path and the second path for each computing element;
A plurality of computing elements set in the first route or the second route at both ends of the two computing element elements set in the route setting step at the first route or the second route. An element connection step for connecting the operation element with the operation element of
It is characterized by providing.

  For example, the method further includes a cycle setting step of setting the cycle of the first clock signal and the second clock signal for each calculator element based on the number of the calculator elements connected in the middle in the element connection step. Good.

  For example, the computing unit may include a lookup table and / or an ALU (Arithmetic Logic Unit).

The program according to the third aspect of the present invention is:
A first path to which the first flip-flop circuit for inputting the first clock signal is connected, and a second path to which the arithmetic unit and the second flip-flop circuit for inputting the second clock signal are connected A computer comprising a plurality of computing element elements comprising:
Path setting means for setting the first path and the second path for each computing element;
A plurality of computing element elements set in the first route or the second route by the route setting means at both ends, and a plurality of routes set by the previous route setting means in the first route or the second route. Element connection means for connecting the operation element with the operation element of
It is made to function as.

For example, period setting means for setting the period of the first clock signal and the second clock signal for each arithmetic element based on the number of arithmetic elements connected in the middle by the element connection means,
It may be made to function as.

  For example, the computing unit may include a lookup table and / or an ALU (Arithmetic Logic Unit).

  According to the present invention, it is possible to easily obtain optimum performance using a software IP in a programmable logic circuit device.

  Hereinafter, a programmable logic device (PLD) 100 according to an embodiment of the present invention will be described. The PLD 100 can directly and dynamically implement program execution by hardware.

  As shown in FIG. 1, the PLD 100 includes a plurality of processor elements (PE) 10, a control unit 20, an I / O unit 30, and a plurality of wirings 40 that are two-dimensionally arranged. ing.

  A plurality of the arithmetic element 10 are two-dimensionally arranged. Each computing element 10 can generate an arbitrary logical function by changing the internal circuit configuration. Each computing element 10 includes a first path and a second path.

  As shown in FIG. 2, the arithmetic element 10 includes a selector circuit (hereinafter referred to as a selector) 11, a lookup table (hereinafter referred to as LUT) 12, a selector circuit 13, and a D-flip flop circuit (hereinafter referred to as FF) 14. A selector circuit 15, a D-flip-flop circuit 16, and a selector circuit 17. The computing element 10 includes a selector 11, an LUT 12, and an FF 14 on the first path, and a selector 15 and an FF 16 on the second path.

  The selector 11 is an m-input one-output circuit, and outputs any one of m input signals from the wiring 40 to the LUT 12 under the control of the control unit 20. In the case of a four-input LUT as shown in FIG. 2, four selectors 11 are arranged.

  The LUT 12 uses input bits as memory addresses and stores output values corresponding to the memory addresses. That is, the LUT 12 can realize any combinational logic circuit that outputs output signals corresponding to a plurality of input signals under the control of the control unit 20. The LUT 12 outputs an output signal based on the input signals from the four selectors 11 and the combinational logic circuit to the FF 14.

  The selector 13 is a circuit with two inputs and one output, and outputs any one of the input application clock signal and system clock signal to the FF 14 based on the control of the control unit 20.

  The FF 14 is a D-flip flop circuit, which receives a data signal and a clock signal, and outputs a signal holding the value of the data signal at the rising edge of the clock signal for each cycle of the clock signal. The FF 14 is used to synchronize signals in each part in the apparatus. Note that an application clock signal or a system clock signal is input to the FF 14 as a clock signal from the selector 13.

  The selector 15 is an m-input one-output circuit, and outputs any one of m input signals from the wiring 40 to the FF 16 under the control of the control unit 20. Two selectors 15 are arranged.

  The FF 16 is a D-flip flop circuit, which receives a data signal and a clock signal, and outputs a signal holding the value of the data signal at the rising edge of the clock signal for each cycle of the clock signal. The FF 16 is used to synchronize signals in each part in the apparatus. Note that an application clock signal or a system clock signal is input to the FF 16 as a clock signal.

  The selector 17 is a two-input one-output circuit, and outputs any one of the input application clock signal and system clock signal to the FF 16 based on the control of the control unit 20.

  The control unit 20 controls the entire PLD 100. Specifically, the control unit 20 performs setting of the first path and the second path of each computing element 10, connection of a plurality of computing elements 10, realization of arbitrary logic in the LUT 12, and the like. .

  The I / O unit 30 is located in the peripheral portion of the PLD 100 and exchanges signals with the outside.

  The wiring 40 connects the arithmetic element 10 and the I / O unit 30 to realize an arbitrary logic circuit. Further, the wiring 40 includes a selector 41.

  The selector 41 is a circuit of two inputs and one output, and connects the FF 14 and the wiring 40 or the FF 16 and the wiring 40, and based on the control of the control unit 20, the input signal from the wiring 40 and the input signals from the FFs 14 and 16 are connected. Either one is output to the wiring 40.

  The PLD 100 includes rewritable memory elements such as SRAM and DRAM included in the LUT 12 and the like, and includes a configuration memory (not shown) configured by these memory elements.

  When an address is given to this configuration memory (not shown) and new circuit information data is stored, the LUT 12 in the arithmetic element 10, the selector, the selector on the wiring 40, and the like are regenerated according to this circuit information. Composed. This series of operations is called a configuration. This configuration can also be performed during operation.

  The PLD 100 is a clock network for providing a clock signal to the FFs 14 and 16 of each arithmetic element 10, as shown in FIG. 3, a clock input unit 31, a PLL (Phase-locked loop) circuit 60, Clock control circuits 61 and 62, clock buffers 63 and 64, and wirings 65 and 66 are provided.

  The clock input unit 31 is a part of the I / O unit 30, acquires a clock signal from the outside, and supplies it to the PLL circuit 60.

  The PLL circuit 60 converts the clock signal supplied from the clock input unit 31 into a clock signal having an arbitrary frequency (system clock signal; hereinafter, sysCLK signal) and supplies the clock signal to the clock control circuits 61 and 62.

  The clock control circuit 61 supplies the sysCLK signal supplied from the PLL circuit 60 to the clock buffer 63. The clock control circuit 61 controls whether or not to supply the sysCLK signal to the clock buffer 63.

  The clock control circuit 62 converts an arbitrary high state clock of the sysCLK signal supplied from the PLL circuit 60 into a low state, and a clock signal (application clock signal; hereinafter, “appCLK”) having a cycle that is a predetermined multiple of the sysCLK signal. Signal) to the clock buffer 64. The clock control circuit 62 controls whether or not to supply the appCLK signal to the clock buffer 64.

  The clock buffer 63 excites the sysCLK signal supplied from the clock control circuit 61 and supplies it to the wiring 65.

  The clock buffer 64 excites the appCLK signal supplied from the clock control circuit 62 and supplies it to the wiring 66.

  The wiring 65 supplies the sysCLK signal supplied from the clock buffer 63 to the selector 13 and the selector 17 of each arithmetic element 10.

  The wiring 66 supplies the appCLK signal supplied from the clock buffer 64 to the selector 13 and the selector 17 of each arithmetic element 10.

  The PLD 100 having the above configuration is used by being incorporated in an information processing system 1000 as shown in FIG. 5, for example.

  For example, the information processing system 1000 includes a PLD 100, an interface 200, a CPU (Central Processing Unit) 300, a ROM (Read Only Memory) 400, a hard disk 500, a RAM (Random Access Memory) 600, and a display unit 700. , An operation unit 800 and a PCI (Peripheral Components Interconnect) bus 900.

  The PLD 100 is connected to the PCI bus 900 via the interface 200.

  The hard disk 500 stores application programs and configuration codes for configuring the PLD 100.

  The CPU 300 loads an application program from the hard disk 500 to the RAM 600 and executes it. Further, the CPU 300 reads circuit information from the hard disk 500 as needed during execution of the application program, loads it into the configuration memory (not shown) of the PLD 100, configures an arbitrary logic circuit on the PLD 100, and Data processing is performed on the circuit.

  That is, the CPU 300 controls the configuration (reconfiguration) in the PLD 100 and the input / output of data to the logic circuit configured on the PLD 100.

  Hereinafter, operations of the PLD 100 and the information processing system 1000 having the above-described configurations will be described.

  First, logic circuit reconfiguration processing performed by the information processing system 1000 will be described. In brief, the information processing system 1000 writes a logic circuit synthesized based on a logic code such as RTL (Register Transfer Level) into the PLD 100.

  Hereinafter, the logic circuit reconfiguration process will be described in detail with reference to the flowchart shown in FIG.

  First, when the CPU 300 receives a request for starting an application program (hereinafter, reconfiguration program) for configuring the PLD 100 from the user via the operation unit 800, the CPU 300 starts the reconfiguration program (step S100). ).

  Next, the CPU 300 logically synthesizes a logical code described in a development language such as VHDL (VHSIC Hardware Description Language) or Verilog that is input by the user via the operation unit 800 or stored in the hard disk 500. It is assumed that the arranged and routed configuration information is acquired (step S200).

  Here, assuming that a request for writing a logic circuit based on the logic code to the PLD 100 is received from the user via the operation unit 800, the CPU 300 writes the logic circuit to the PLD 100 (step S300) and ends the process. To do.

  In this way, according to the logic circuit reconfiguration process, the information processing system 1000 writes a logic circuit based on an arbitrary logic code to the PLD 100 and directly executes the program in the hardware (PLD 100). Can do.

  Here, the logic circuit in steps S200 and S300 will be described.

  In steps S200 and S300, as shown in FIG. 7, the arithmetic element 10 on the PLD 100 includes an arithmetic element serving as a buffer (here, only a flip-flop is indicated) and an arithmetic unit mounted as an application. It is set to have an element, that is, a logic circuit written in RTL (Register Transfer Level) (here, only a flip-flop is indicated).

  A computing element (hereinafter referred to as a buffer computing element) serving as a buffer updates and outputs data for each cycle of the sysCLK signal as shown in FIG.

  Of the logic blocks implemented as an application, an element (hereinafter referred to as an application computing element) in which a flip-flop circuit existing in the RTL is installed updates data for each cycle of the appCLK signal as shown in FIG. And output.

  Further, the period of the appCLK signal is determined based on the number of buffer arithmetic elements between the application arithmetic elements based on the period of the sysCLK signal.

  For example, in the path example shown in FIG. 8A, a computing element 10b set as a buffer computing element between a computing element 10a set as an application computing element and a computing element 10e. 10d are arranged.

  When the path example in FIG. 8A is represented as a path for the flip-flop circuit, as shown in FIG. 8B, the sysCLK signal is input between the FF 14a and the FF 14e to which the appCLK signal is input. FFs 16b to 16d are arranged. However, the FFs 14a, 16b, 16c, 16d, and 14e are flip-flop circuits included in the arithmetic element 10a to 10e, respectively.

At this time, since the number of critical paths between the FF 14a and the FF 14e is 4, as shown in FIG. 4, the appCLK signal is set to include one clock with respect to the four clocks in the sysCLK signal. Is done.
That is, when only “n−1” buffer calculator elements are arranged between two application calculator elements, and the number of critical paths between the FFs 14 of the two application calculator elements is “n”, The appCLK signal is set to include one clock for “n” clocks in the sysCLK signal.

  Here, an actual data flow in the route example of FIG. 8 will be described with reference to FIG.

  FIG. 9 is a diagram illustrating a clock signal input to each flip-flop circuit and data to be held and output for each time.

  As shown in FIG. 9, the FF 14a holds and outputs data A1 at time “3 to 11” because the rising time of the clock of the input appCLK signal is time “3, 11, 19”. -19 "holds and outputs data B1, and holds and outputs data C1 at time" 19 ".

  As shown in FIG. 9, in the FF 16b, the rising time of the clock of the input sysCLK signal is time “1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23”. The FF 16b receives the data A1 from the FF 14a at time “5, 7, 9, 11”. The FF 16b receives the data B1 from the FF 14a at the time “13, 15, 17, 19”. The FF 16b receives the data C1 from the FF 14a at time “21, 23”.

Therefore, data A1 is held / output at time “5-7”, data is updated at time “7”, data A1 is held / output at time “7-9”, and data is updated at time “9”. The data A1 is held / output at time “9-11”, the data is updated at time “11”, the data A1 is held / output at time “11-13”, and the data is updated at time “13”. To do.
Data B1 is held / output at time “13-15”, data is updated at time “15”, data B1 is held / output at time “15-17”, and data is updated at time “17”, Data B1 is held / output at time “17-19”, data is updated at time “19”, data B1 is held / output at time “19-21”, and data is updated at time “21”.
Data C1 is held / output at time “21-23”, data is updated at time “23”, and data C1 is held / output at time “23-”.

  Since the data flow of the FF 16c and the FF 16d is substantially the same, the description thereof is omitted.

  As shown in FIG. 9, the FF 14e has a time “3, 11, 19” when the clock of the input appCLK signal rises. Further, the data A1 is input to the FF 14e from the FF 16d at time “11”. The FF 14e receives the data B1 from the FF 16d at time “19”.

Therefore, data is updated at time “11”, data A1 is held / output at time “11-19”, data is updated at time “19”, and data B1 is held / output at time “19”. .
As shown in FIGS. 10 and 11, if the clock interval of the appCLK signal is the same, the FF 14e performs the same operation as the FF 14e even if any of the FFs 16b to d in FIGS.

  Note that the FFs 16b to 16d in FIG. 8B may be replaced with the FFs 14 to which the sysCLK signal is input by the selector 13, respectively. Further, the FFs 14 a and 14 e in FIG. 8B may be replaced by the FF 16 to which the sysCLK signal is input by the selector 17.

  In such a logic circuit, all the arithmetic element elements are synchronized by the flip-flop circuit, and there is no loop that cannot be interposed between the flip-flop circuits, so the current LSI (Large Scale Integration) design flow Fits. Automatic test synthesis can be used. Unlike the static timing analysis (STA), it is not necessary to add the delay value of each arithmetic element individually when the RTL is mounted, and the clock frequency can be determined by the number of stages of the flip-flop circuit. Because of these advantages, the PLD design period can be shortened. Optimal performance can be obtained using software IP.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation and application are possible.

  In the above embodiment, one computing element includes one lookup table, but one computing element may include a plurality of lookup tables.

  In the above embodiment, the four-input one-output arithmetic element is provided with a flip-flop circuit on the output side. However, the present invention is not limited to this, and p input q provided with a flip-flop circuit on the output side. An output computing element may be used. However, p and q are natural numbers.

  Further, since the appCLK signal only needs to mask a plurality of clocks of the sysCLK signal, as shown in FIG. 13, the selector 13 is configured by an AND or OR circuit, and the selector 13 masks the plurality of clocks of the sysCLK signal. However, it may be configured to switch between the appCLK signal and the sysCLK signal.

In this case, the selector 13 is composed of an OR circuit 13A and an AND circuit 13B as shown in FIG.
In this case, the clock network includes a clock input unit 31, a PLL circuit 60, wirings 65 and 66, and a counter circuit 67, as shown in FIG.

The PLL circuit 60 outputs a clock signal as shown in FIG.
As shown in FIG. 14B, the counter circuit 67 counts the number of clocks of the PLL output signal input from the PLL circuit 60, and outputs one clock for each number of clocks set by the control unit 20 (counter output). Output a signal).
The OR circuit 13A receives the configuration signal (0 or 1) designated from the control unit 20 and the counter output signal from the counter circuit 67. When the configuration signal is 0, the OR circuit 13A outputs the counter output signal as it is. When 1 is 1, 1 is output.
The AND circuit 13B receives the PLL output signal from the PLL circuit 60 and the output signal from the OR circuit 13A. Further, when the configuration signal input to the OR circuit 13A is 1, the AND circuit 13B outputs the PLL output signal as it is as the sysCLK signal as shown in FIG. 14C, and is input to the OR circuit 13A. When the configuration signal is 0, a clock signal depending on the counter output signal is output as an appCLK signal as shown in FIG.

  Therefore, according to the clock network and the selector 13 as shown in FIGS. 13 and 14, the sysCLK signal and the appCLK signal can be switched by the configuration information (0 or 1).

  Similarly, the selector 17 may be configured by an AND or OR circuit, and the selector 13 may be switched between the appCLK signal and the sysCLK signal depending on whether or not the plurality of clocks of the sysCLK signal are masked.

  Further, specific details of the structure and the like can be changed as appropriate.

It is a 1st block diagram of PLD which concerns on embodiment of this invention. It is a block diagram of the computing element element of FIG. 1 and its peripheral part. It is a block diagram of the clock network of PLD which concerns on embodiment of this invention. 5 is a graph for explaining a clock signal used in the PLD according to the embodiment of the present invention. 1 is a configuration diagram of an information processing system according to an embodiment of the present invention. It is a flowchart for demonstrating a logic circuit reconfiguration process. It is a 1st figure for demonstrating operation | movement of PLD which concerns on embodiment of this invention. It is a 2nd figure for demonstrating operation | movement of PLD which concerns on embodiment of this invention. It is a 3rd figure for demonstrating operation | movement of PLD which concerns on embodiment of this invention. It is a 4th figure for demonstrating operation | movement of PLD which concerns on embodiment of this invention. It is a 5th figure for demonstrating operation | movement of PLD which concerns on embodiment of this invention. It is a block diagram of the clock network of PLD which concerns on the modification of embodiment of this invention. It is a block diagram of the selector which concerns on the modification of embodiment of this invention. It is a graph for demonstrating the clock signal used for PLD which concerns on the modification of embodiment of this invention.

Explanation of symbols

10 arithmetic element 10a to e arithmetic element 11 selector circuit 12 lookup table 13 selector circuit 13A OR circuit 13B AND circuit 14 D-flip flop circuit 14a, e D-flip flop circuit 15 selector circuit 16 D-flip flop circuit 16b ˜d D flip-flop circuit 20 control unit 30 I / O unit 31 clock input unit 40 wiring 41 selector circuit 60 PLL circuit 61, 62 clock control circuit 63, 64 clock buffer 65, 66 wiring 67 counter circuit 100 PLD
200 interface 300 CPU
400 ROM
500 Hard disk 600 RAM
700 Display Unit 800 Operation Unit 1000 Information Processing System

Claims (9)

A first path to which a first flip-flop circuit for inputting a first clock signal is connected, and a second path to which an arithmetic unit and a second flip-flop circuit for inputting a second clock signal are connected A plurality of computing element elements comprising:
Path setting means for setting the first path and the second path for each computing element;
A plurality of computing elements set by the path setting means for the first path or the second path at both ends, and a plurality of sets for which the path setting means set for the first path or the second path And an element connection means for connecting the calculator elements with the calculator element as an intermediate,
A programmable logic circuit device. The apparatus further comprises period setting means for setting the period of the first clock signal and the second clock signal for each arithmetic element based on the number of arithmetic elements connected in the middle by the element connection means.
The programmable logic circuit device according to claim 1. The arithmetic unit includes a lookup table and / or an ALU (Arithmetic Logic Unit).
The programmable logic circuit device according to claim 1 or 2. A first path to which the first flip-flop circuit for inputting the first clock signal is connected, and a second path to which the arithmetic unit and the second flip-flop circuit for inputting the second clock signal are connected A programmable logic circuit reconfiguration method for changing the logical configuration of a programmable logic circuit comprising:
A path setting step for setting the first path and the second path for each computing element;
A plurality of computing element elements set to the first path or the second path at both ends of the path setting step and the path setting means set to the first path or the second path; An element connection step for connecting the calculator elements with the calculator element of
And a programmable logic circuit reconfiguration method. A cycle setting step of setting the cycle of the first clock signal and the second clock signal for each calculator element based on the number of calculator elements connected in the middle in the element connection step;
The programmable logic circuit reconfiguration method according to claim 4. The arithmetic unit includes a lookup table and / or an ALU (Arithmetic Logic Unit).
6. The programmable logic circuit reconfiguration method according to claim 4 or 5, wherein: A first path to which the first flip-flop circuit for inputting the first clock signal is connected, and a second path to which the arithmetic unit and the second flip-flop circuit for inputting the second clock signal are connected A computer comprising a plurality of computing element elements comprising:
Path setting means for setting the first path and the second path for each computing element;
A plurality of computing elements set by the path setting means for the first path or the second path at both ends, and a plurality of sets for which the path setting means set for the first path or the second path Element connection means for connecting the operation element with the operation element of
A program characterized by functioning as A period setting means for setting the period of the first clock signal and the second clock signal for each arithmetic element based on the number of arithmetic elements connected in the middle by the element connection means;
The program according to claim 7, wherein the program is made to function as: The arithmetic unit includes a lookup table and / or an ALU (Arithmetic Logic Unit).
The program according to claim 7 or 8, characterized in that.

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