JP2009015757A - Abnormal state handling system in signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow high-speed fault handling when a signal processor having a processor, a volatile memory, and a nonvolatile memory fails, in an abnormal state handling system in the signal processor. <P>SOLUTION: In the signal processor configured to connect, the nonvolatile memory which holds a program and a fault handling routine, and a volatile memory which copies the program and the fault handling routine from the nonvolatile memory to a system bus and perform processing by the program of the volatile memory, the system bus is provided with a bus monitoring circuit, and two interruption vectors for entering the fault handling routine when the fault occurs, the system is restarted by processing the fault handling routine of the nonvolatile memory when program destruction is detected by the bus monitoring circuit and processing of the fault handling routine of the volatile memory is executed when a fault except the program destruction is detected. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an abnormal state processing method in a signal processing device that performs real-time signal processing, such as a mobile communication radio base station.

  In a signal processing device equipped with a processor that performs real-time signal processing, such as a radio base station for mobile communications, it has a function to stop or restore the system when interrupted for processor failure processing, and collects error logs And a function to perform storage processing.

  In the conventional system, a conventional control method in the case where the processor detects an abnormality and performs the processing of the failure processing routine due to the cause will be described below.

  FIG. 5 shows the configuration of Conventional Example 1, and FIG. 6 shows the control method of Conventional Example 1. In FIG. 5, 50 is a processor, 51 is a WDT (Watch Dog Timer) monitoring unit for checking the normality of the processor by checking the response by interrupting the processor at a fixed period, 52 A volatile memory that performs high-speed operation, 520 is a program operation area, 521 is a failure processing routine, 522 is an interrupt vector, 53 is a non-volatile memory that operates at low speed, 530 is a program storage unit, and 54 is a system bus.

  FIG. 6 shows a control method in the configuration of Conventional Example 1 in FIG. First, as processor activation processing, a program is copied from the program storage unit 530 of the nonvolatile memory 53 to the volatile memory 52 (S1 in FIG. 6). Thereby, the program area 520 of the volatile memory 520 and the failure processing routine 521 are set. Thereafter, the processor 50 enters a state in which normal processing is being executed according to the program in the volatile memory 52 (S2 in FIG. 6). Thereafter, when a program breakage occurs (such as overwriting in the program area of the nonvolatile memory 52) and a fault interrupt occurs due to a WDT timeout in the WDT monitoring unit 51 (S3 in FIG. 6), fault handling corresponding to the interrupt The routine interrupt vector 522 is read (S4). The interrupt vector jumps to the fault processing routine on the volatile memory 52 (S5 in FIG. 6), executes the fault processing routine 521 on the volatile memory 52 (S6), and the program on the volatile memory 52 Processor restart processing is performed (S7).

  According to the control method of the conventional example 1, since the failure processing routine due to the occurrence of an interrupt is expanded on the volatile memory, there is a problem that normal operation cannot be guaranteed if the program area is destroyed.

  As a method for solving this problem, there is a method of Conventional Example 2, FIG. 7 shows a configuration of Conventional Example 2, and FIG. 8 shows a control method of Conventional Example 2. In FIG. 7, reference numerals 50 to 54 are the same as those denoted by the same reference numerals in FIG. 7 differs from FIG. 5 in that only the program area 520 is provided in the volatile memory 52 of FIG. 7 and the nonvolatile memory 53 includes a program storage unit 530, a failure processing routine 531 and an interrupt vector 532.

  The control method of Conventional Example 2 will be described. First, in processor startup processing, a program is copied from the nonvolatile memory 53 to the volatile memory 52 (S1 in FIG. 8), and the processor 50 enters a state in which normal processing is being executed. (S2), when a fault interrupt occurs due to a WDT monitoring timeout due to program destruction (S3), unlike the conventional example 1, the fault processing routine interrupt vector 532 is read on the nonvolatile memory 53 (Same 4). . Therefore, the process jumps to the failure processing routine of the nonvolatile memory 53 (S5 in FIG. 8), executes the failure processing routine (S6), and executes the processor restart process on the nonvolatile memory (S7).

  In the control method of Conventional Example 2, since the failure processing routine is expanded on the nonvolatile memory, the influence of program destruction can be avoided, but the operation is performed on the nonvolatile memory (low-speed memory). The execution time of the failure processing routine becomes longer, and the service interruption time until restart is increased.

  In general, the latency of volatile memory (SDRAM system) is about 5.4 ns or 6.0 ns, which is high speed. Compared with that, non-volatile memory is generally 60 ns or 90 ns, and address control is performed. In consideration of such overhead, the volatile memory SDRAM is 10 times faster.

  As a technique for recording failure information of a multiprocessor system, each processor package has a processor and a nonvolatile memory, and a control routine is stored in the nonvolatile memory. There is a technology that collects fault data by the control routine in the memory and stores it as fault data in the non-volatile memory. The fault data of each of the multiple processors is collected at system startup and stored in the main memory. (See Patent Document 1).

In addition, in the technology of a system in which each of a plurality of processors including a monitoring processor has a nonvolatile memory and a volatile memory, and a maintenance target program of an external storage device is loaded into the volatile memory of each processor and executed, maintenance is performed. If a problem occurs during execution of the target program, the monitoring processor is notified. The monitoring processor disables the interrupted processor, and develops a patch routine stored in the nonvolatile memory in the volatile memory for processing. Start, search the external storage device for maintenance information related to the current trouble by the patch routine, enter the correction information into the maintenance target program of the external storage device, record it as logging information, and store the maintenance target program on the processor Trouble software that causes the same phenomenon when deployed Patch technology exists to put already (see Patent Document 2).
JP-A-9-288603 JP-A-4-77937

  According to the above-described conventional example 2, even if the program destruction of the volatile memory occurs, the log storage processing and the recovery processing can be executed by the failure processing routine of the nonvolatile memory. Compared to 10 times longer, the performance is inferior in terms of processing speed, the system interruption time (service interruption) for resumption becomes longer, and there is a problem that the influence on the system that performs real-time signal processing is large. . Further, the technique of Patent Document 1 described above is applied to a system in which high-speed processing is not required when performing failure processing in a multiprocessor system, in which processing is performed by a non-volatile memory control routine as in Conventional Example 2. However, there is a problem with real-time signal processing devices that require high-speed processing. The technique of Patent Document 2 is a technique for obtaining information related to a failure by searching maintenance information of an external storage device by a patch routine of a nonvolatile memory when a failure occurs, and supplying a correction patch to the external storage device. It does not perform high-speed failure handling when it occurs.

  An object of the present invention is to provide an abnormal state processing method in a signal processing device that enables high-speed failure processing when a failure occurs in a signal processing device including a processor, a volatile memory, and a nonvolatile memory.

  FIG. 1 shows the principle configuration of the present invention. In the figure, 1 is a processor, 2 is a bus monitoring circuit, 2a is a program destruction monitoring means for detecting a program area destruction in the volatile memory 3 and a parity error on the volatile memory, 2b is a parity error other than the volatile memory 3, and Parity error monitoring means for monitoring parameter violation during program operation, 2c is an interrupt vector switching means, 3 is a volatile memory, 3a is a program area, 3b is a failure processing routine, 4 is a non-volatile memory holding a program, 4a Is a program storage unit, 4b is a failure processing routine, 5 is an interrupt vector nonvolatile memory, 5a is a first interrupt vector, 5b is a second interrupt vector, and 6 is a system bus.

  In FIG. 1, first, the contents of the program storage unit 4a of the nonvolatile memory 4 and the first failure processing routine 4b are copied to the volatile memory 3 and stored as the program area 3a and the second failure processing routine 3b. Further, in the interrupt vector nonvolatile memory 5, the first interrupt vector 5 a is set to the content specifying the failure processing routine 3 b of the volatile memory 3, and the second interrupt vector 5 b is stored in the nonvolatile memory 4. It is set to the contents specifying the failure processing routine 4b. In addition, the range to be monitored is set in the program destruction monitoring means 2a and the parity error monitoring means 2b.

  Thereafter, when the processor 1 executes normal processing according to the program in the program area 3 a of the volatile memory 3, the bus monitoring circuit 2 monitors the system bus 6, and the program destruction monitoring means 2 a detects the program area 3 a on the volatile memory 3. And writing to the area of the failure processing routine 3b (destruction), monitoring whether a parity error on the volatile memory 3 has occurred, and detecting a program corruption, it indicates that an error has occurred in the volatile memory 3. Thus, the failure processing using the nonvolatile memory 4 is selected, and the interrupt vector switching means 2c outputs an interrupt signal (failure processing start timing) including switching to the second interrupt vector 5b to the processor 1 in response to this. . As a result, the processor 1 reads the second interrupt vector 5b of the interrupt vector nonvolatile memory 5, shifts to the processing of the failure processing routine 4b of the nonvolatile memory 4 designated by the vector, and executes the failure processing. . In this case, it is necessary to execute a process including a copy of the program from the nonvolatile memory 4 in the volatile memory 3 in the restart process.

  Further, if a parity error other than the volatile memory is detected by the parity error monitoring means 2b of the bus monitoring circuit 2 or a parameter violation or the like is detected during the program operation, it is assumed that no abnormality has occurred in the volatile memory 3. In response to the failure processing using the volatile memory 3, the interrupt vector switching means 2c outputs an interrupt signal (failure processing start timing) including switching of the first interrupt vector 5a to the processor 1. As a result, the processor 1 reads the first interrupt vector 5a of the interrupt vector nonvolatile memory 5, shifts to the processing of the failure processing routine 3b of the volatile memory 3 designated by the vector, and executes the failure processing. .

  According to the present invention, log collection processing and failure notification processing are reliably performed even when high-speed volatile memory program destruction or exception processing occurs while performing high-speed operation with a built-in processor / external volatile memory. It becomes possible to do. Further, when an exception process that can be remedied with normal volatile memory occurs, it is not necessary to shift to the resumption process flow, and it is possible to minimize the failure recovery time and the system instantaneous interruption time.

  FIG. 2 is a processing flow of the embodiment, and processing is performed in the processor 1 of FIG. 1 in cooperation with the bus monitoring circuit 2 and each memory. The volatile memory 3 is composed of, for example, an SDRAM memory, and the nonvolatile memory 4 is composed of, for example, a FLASH memory.

  In the processor activation processing, copying is performed from the nonvolatile memory 4 (program storage unit 4a, failure processing routine 4b) to the volatile memory 3 (S1 in FIG. 2), the program is activated (S2 in the same), and the volatile memory 3 Normal processing is executed by the program (S3). During execution of this normal processing, the bus monitoring circuit 2 performs a monitoring operation. Thereafter, steps S4 to S8 are executed in the bus monitoring circuit 2. That is, it is determined whether or not a failure has occurred during execution of normal processing (detection of presence or absence of detection output from the bus monitoring circuit 2) (S4 in FIG. 2). A determination is made (S5). At this time, it is determined whether or not the failure causes program destruction (S6 in FIG. 2). This determination is based on whether a volatile memory error has occurred by writing (overwriting) to the program area in the volatile memory 3 or detecting a parity error on the volatile memory 3, or detecting a parity error other than the volatile memory 2 or Judges whether parameter violation was detected during program operation. If a failure including program destruction on the volatile memory is detected, the volatile memory is abnormal, so the second interrupt vector 5b is selected to cause the nonvolatile memory to select a process (S6 in FIG. 2), In the case of a failure such as detection of a parity error other than the volatile memory, since the volatile memory is normal, the first interrupt vector 5a is selected to cause the volatile memory to select processing (S7), and step S6 , S7, an interrupt signal (including an interrupt vector) and a failure processing start timing are issued from the bus monitoring circuit 2 and supplied to the processor 1 (S8).

  When this is received, the processor 1 reads the failure processing routine interrupt vector (S8 in FIG. 2). That is, either the first interrupt vector 5a or the second interrupt vector 5b is selected. As a result, the processing of the processor 1 jumps to the failure processing routine of the volatile memory or nonvolatile memory (S10 in FIG. 2), executes the failure processing routine (S11), and detects the failure from the bus monitoring circuit 1 described above. As a situation at the time, it is determined whether or not the program has been destroyed (S12). If there is no program destruction, the processor restart processing (the program development (copy) to the volatile memory 3 is omitted) is performed, and step S2 If the program is destroyed, the processor restart process (recopying the program to the volatile memory 3) is executed, and the process returns to step S1.

  FIG. 3 is a processing flow for program destruction monitoring in the bus monitoring circuit and corresponds to the processing function in the program destruction monitoring means 2a of FIG.

  First, the bus monitoring circuit is initialized (S1 in FIG. 3). At this time, (1) a monitoring start (START) address and a monitoring end (END) address are set as program areas, and these areas are a program operation area and a failure processing routine area on the volatile memory (3 in FIG. 1). .

  Thereafter, monitoring is started (S2), and writing (WRITE) operation monitoring is performed on the monitoring area as needed (S3), and it is determined whether the writing operation is performed (S4). When a write operation is detected, if it is detected that the write to the monitoring area (program destruction) is detected (S5 in FIG. 3), a vector is set by interrupt vector switching control (S6). In this case, the second interrupt vector (5b in FIG. 1) on the nonvolatile memory (4 in FIG. 1) side is selected. Next, an interrupt is issued from the bus monitoring circuit to the processor for notification (S7 in FIG. 3). That is, an interrupt signal is activated to activate the fault processing. Thereby, the monitoring of the bus monitoring circuit is stopped (S8 in FIG. 3).

  In step S4 in FIG. 3, writing to the program area and the failure processing routine area of the volatile memory is monitored. However, when a parity error on the volatile memory is detected, the processing from step S6 is similarly performed. Is executed.

  FIG. 4 is a processing flow of parity error monitoring in the bus monitoring circuit, and corresponds to the processing function in the parity error monitoring means 2b of FIG.

  First, parity error monitoring initial setting is performed (S1 in FIG. 4). At this time, a parity error (exception processing during program operation and device failure of the nonvolatile memory) in the nonvolatile memory other than the volatile memory (the program storage unit 4a and the failure processing routine 4b in FIG. 1) is monitored. , Monitoring start (START) address and monitoring end (END) address (nonvolatile memory address) are set. Subsequently, monitoring is started (S2 in FIG. 4), and reading (READ) operation monitoring is performed on the monitoring area as needed (S3) to determine whether an error is detected (S4). When an error is detected and an error is detected for the monitoring area (S5 in FIG. 4), a vector is set by interrupt vector switching control (S6). In this case, the second interrupt vector (5a in FIG. 1) on the volatile memory (3 in FIG. 1) side is selected. Next, an interrupt is issued to the processor for notification (S7 in FIG. 4). Specifically, an interrupt signal is activated to activate fault processing. Thereafter, the bus monitoring circuit stops monitoring (S8 in FIG. 3).

  In this way, when only part of the failure processing routine (important log collection processing and recovery detection) is stored in the non-volatile memory and normal "program corruption detection" is performed at the same time, program corruption does not occur It is possible to maintain system maintenance performance by executing fault processing (low-speed processing: non-volatile memory) reliably when program failure is detected by enabling high-speed fault processing (volatile memory processing) Become.

  In the processing flow shown in FIG. 3 above, the program destruction of the volatile memory and the parity error of the volatile memory are monitored. In the processing flow shown in FIG. 4, the parity error other than the volatile memory and the exception processing during the program operation are monitored. However, even when other failures in the volatile memory are detected, the same control (selecting the second interrupt vector) is performed by the processing flow shown in FIG. Needless to say, even when a failure other than the error shown in FIG. 4 is detected, the same control (selecting the first interrupt vector) can be performed by the processing flow shown in FIG.

  (Supplementary note 1) A non-volatile memory that holds a processor, a program, and a fault handling routine, and a volatile memory that copies the program and the fault handling routine from the non-volatile memory are connected to a system bus. In an abnormal state processing method in a signal processing device that performs processing, when a bus monitoring circuit is provided on the system bus and two interrupt vectors for jumping a failure processing routine when a failure occurs, a program destruction is detected by the bus monitoring circuit The system restarts by executing the failure processing routine of the non-destructed nonvolatile memory, and executes the processing of the volatile memory failure processing routine when a failure other than program destruction is detected. An abnormal state processing method in a signal processing apparatus.

  (Supplementary note 2) In the supplementary note 1, when the bus monitoring circuit is provided with means for detecting program destruction of the volatile memory, and the program destruction is detected by the means for detecting program destruction, the nonvolatile memory is selected from the interrupt vector. An abnormal state processing method in a signal processing device, wherein an interrupt signal is generated in the processor, the system is restarted by the failure processing routine of the nonvolatile memory.

  (Supplementary note 3) In Supplementary note 1, the bus monitoring circuit is provided with means for detecting a parity error of data other than the volatile memory, and when an error is detected by the means for detecting the parity error, the volatile data is detected from the interrupt vector. When the failure processing routine of the volatile memory is selected and an interrupt signal is generated in the processor, the failure processing by the volatile memory is performed.

  (Additional remark 4) The abnormal state processing system in the signal processing apparatus according to any one of additional remarks 1 to 3, wherein log collection processing and failure notification processing are reliably executed when a failure is detected by the bus monitoring circuit.

  (Additional remark 5) In any one of additional remarks 1 thru | or 4, the said signal processing apparatus processes the signal in the radio | wireless base station of a mobile communication system, The abnormal condition processing system in the signal processing apparatus characterized by the above-mentioned.

It is a figure which shows the principle structure of this invention. It is a figure which shows the processing flow of an Example. It is a figure which shows the processing flow of the program destruction monitoring in a bus monitoring circuit. It is a figure which shows the processing flow of the parity error monitoring in a bus monitoring circuit. It is a figure which shows the structure of the prior art example 1. FIG. It is a figure which shows the control method of the prior art example 1. FIG. It is a figure which shows the structure of the prior art example 2. FIG. It is a figure which shows the control method of the prior art example 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Processor 2 Bus monitoring circuit 2a Program destruction monitoring means 2b Parity error monitoring means 2c Interrupt vector switching means 3 Volatile memory 3a Program area 3b Fault processing routine 4 Non-volatile memory 4a Program storage unit 4b Fault processing routine 5 Non-volatile for interrupt vector Memory 5a First interrupt vector 5b Second interrupt vector 6 System bus

Claims (3)

A non-volatile memory that holds a processor, a program, and a fault handling routine, and a volatile memory that copies the program and the fault handling routine from the non-volatile memory are connected to the system bus, and a signal that is normally processed by the program in the volatile memory In the abnormal state processing method in the processing device,
The system bus is provided with a bus monitoring circuit and two interrupt vectors for jumping a fault processing routine when a fault occurs.
When program destruction is detected by the bus monitoring circuit, the system is restarted by executing the failure processing routine of the non-destructed nonvolatile memory, and when a failure other than program destruction is detected, the volatile memory failure processing An abnormal state processing method in a signal processing device, characterized in that routine processing is executed. In claim 1,
The bus monitoring circuit is provided with means for detecting program destruction of the volatile memory,
When the program destruction is detected by the means for detecting the program destruction, the non-volatile memory fault processing routine is selected from the interrupt vector, an interrupt signal is generated to the processor, and the non-volatile memory fault processing routine is selected. An abnormal state processing method in a signal processing device, characterized in that the system is restarted according to the above. In claim 1,
Means for detecting a parity error of data other than the volatile memory in the bus monitoring circuit;
When an error is detected by the means for detecting the parity error, the failure processing routine of the volatile memory is selected from the interrupt vector, and when the interrupt signal is generated to the processor, the failure processing by the volatile memory is performed. An abnormal state processing method in a signal processing device.

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