JP2009015689A - Interface device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface device for a new communication protocol without re-developing ASIC. <P>SOLUTION: A Flash ROM 12 stores a program for controlling communication with an external device according to a communication protocol. An output data buffer control circuit 6 and an output signal synchronization circuit 7 control the synchronization of data and control signals to be transmitted to the external device. A CPU 1 generates the control signals, which are transmitted to the external device, according to the program. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an interface device that communicates with an external device.

Some electronic devices have ASICs (application-specific ICs). A device such as an ASIC has an interface device, and exchanges data with other devices provided in the apparatus via the interface device. As such an interface device, by including a selector for selecting an interface unit to be operated from among a plurality of interface units having different data transfer methods, other peripheral devices are employed by upgrading the version of the device. When the communication protocol is updated, there is one that supports the update of the communication protocol without redeveloping the ASIC (see, for example, Patent Document 1).
JP 2004-348580 A

  However, in the conventional interface device, if the updated communication protocol is not compatible with the interface device prepared in advance, it will be necessary to redevelop the ASIC, resulting in extra development costs and man-hours. It does not describe the point of view.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an interface device that can support a new communication protocol without re-developing an ASIC.

  The inventor of the present invention has focused on changing the program for operating the CPU so that it can cope with a new communication protocol without redeveloping the ASIC. In particular, a common configuration is provided for each communication protocol for controlling the synchronization between data transmitted or received with an external device and a control signal, and synchronization between data and control signals that differ for each communication protocol is provided. The idea was to realize the method by changing the program.

  In view of the above points, the present invention transmits between a storage unit (corresponding to FlashROM 12 in FIG. 1) for storing a program for controlling communication performed with an external device according to a communication protocol, and the external device. Or a synchronization control unit for controlling the synchronization between received data and a control signal (the input data buffer control circuit 4, the output data buffer control circuit 6, the output signal synchronization circuit 7 in FIG. 1, and the input data buffer control circuit 4 in FIG. 9). , Corresponding to the output data buffer control circuit 6 and the output signal synchronization circuit 15), and a CPU that generates the control signal to be transmitted to the external device according to the program.

  The communication interface device of the present invention further includes a data buffer (corresponding to the input data buffer 3 and the output data buffer 5 in FIG. 1) for temporarily storing the data, and the synchronization control unit stores the data in the data buffer. The transferred data is controlled based on the control signal input from the CPU or the external device.

  In the communication interface device of the present invention, the synchronization control unit (corresponding to the output data buffer control circuit 6 in FIG. 3) is a value stored in a register (corresponding to the data output permission register 6a in FIG. 3) by the CPU. And the transfer of the data stored in the data buffer is controlled based on at least one of the control signal value input from the external device.

  In the communication interface device of the present invention, the synchronization control unit (corresponding to the output signal synchronization circuit 7 in FIG. 3) controls the transfer of the data stored in the data buffer (read request signal in FIG. 3). The control signal transmitted to the external device is controlled based on the control signal generated by the CPU and the control signal generated by the CPU.

  In the communication interface device of the present invention, the synchronization control unit (corresponding to the input data buffer control circuit 4 in FIG. 8) outputs the control signal generated by the CPU to the external device. Control is performed according to the amount of the data stored in the buffer.

  The communication interface device of the present invention further includes an input control signal buffer (corresponding to the input control signal buffer 2 in FIG. 1) for temporarily storing the control signal input from the external device.

  In the communication interface device of the present invention, the synchronization control unit (corresponding to the input data buffer control circuit 4 in FIG. 13) receives the control signal input from the external device or the data input from the external device. Only when it changes, writing of the data to the data buffer or writing of the control signal to the input control signal buffer is permitted.

  The communication interface device according to the present invention further includes an output control signal buffer (corresponding to the output control signal buffer 14 in FIG. 9) for temporarily storing the control signal transmitted to the external device.

  In the above description, the description in parentheses is for the purpose of associating the embodiment of the present invention described later with the components of the present invention for convenience, and the contents of the present invention are not limited by this description. Absent.

  According to the present invention, by changing the program for operating the CPU, it is possible to cope with a new communication protocol without redeveloping the ASIC.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows the configuration of the interface device according to the present embodiment. In FIG. 1, an interface device includes a CPU 1, an input control signal buffer 2, an input data buffer 3, an input data buffer control circuit 4, an output data buffer 5, an output data buffer control circuit 6, an output signal synchronization circuit 7, an internal circuit I / F8, internal circuit 9, memory controller 10, SDRAM 11, FlashROM 12, and bus 13 are provided.

  FIG. 2 shows the configuration of the CPU 1. The CPU 1 includes an ALU 1a (arithmetic unit), a general-purpose register 1b, a load / store unit 1c, an interrupt controller 1d, a register 1e, a falling differentiation circuit 1f, a rising differentiation circuit 1g, and a selector 1h. The ALU 1a performs an operation. The general-purpose register 1b stores a value used by the ALU 1a for an operation and an execution result of the operation. The load / store unit 1 c executes data transfer via the bus 13. The interrupt controller 1d detects the occurrence of an interrupt to the CPU 1 based on the input interrupt signal. The register 1e stores a value used by the ALU 1a for an operation and an execution result of the operation.

  The falling differentiation circuit 1f outputs a signal corresponding to the falling edge of the input signal. The rising differentiation circuit 1g outputs a signal corresponding to the rising edge of the input signal. The selector 1h selects and outputs one of the outputs of the register 1e, the falling differentiation circuit 1f, and the rising differentiation circuit 1g. Each bit of the general-purpose register 1b corresponds to each control signal. Basically, when the ALU 1a writes a value to the general-purpose register 1b, the value is output as a control signal (output) to an external device (external device). . However, the output of the register 1e is connected to the falling differentiation circuit 1f and the rising differentiation circuit 1g, and the output selected by the selector 1h among the outputs of the falling differentiation circuit 1f and the rising differentiation circuit 1g and the output of the register 1e. Is output to the external device. With the configuration described above, it is also possible to output a pulse-like waveform in addition to outputting an arbitrary level of output at an arbitrary timing.

  In FIG. 1, an input control signal buffer 2 temporarily stores a control signal (input) input from an external device. The input data buffer 3 temporarily stores data input from an external device. The input data buffer control circuit 4 controls the input data buffer 3. The output data buffer 5 temporarily stores data output to the external device. The output data buffer control circuit 6 controls the output data buffer 5. The output signal synchronization circuit 7 can generate a control signal (output) to an external device, and controls the synchronization of data output to the external device and the control signal (output). The internal circuit I / F 8 transfers data between the input data buffer 3 and output data buffer 5 and the internal circuit 9. The internal circuit 9 executes predetermined data processing.

  The memory controller 10 controls access to the SDRAM 11 and the Flash ROM 12 by the CPU 1. The SDRAM 11 is a memory that the CPU 1 uses as a work area. The FlashROM 12 stores a rewritable program for controlling communication performed with an external device according to a communication protocol.

  The outline of the operation of the interface apparatus according to the present embodiment is as follows. A program that records instructions of the CPU 1 is stored in the Flash ROM 12. When the drive power is supplied to the CPU 1 and the reset is released, the CPU 1 reads the program from the Flash ROM 12 via the memory controller 10 and develops it in the SDRAM 11. After the development of the program, the CPU 1 operates by fetching an instruction from the SDRAM 11. The CPU 1 determines the operation state of the internal circuit 9 and comprehensively determines the control signal (input) from the external device written to the input control signal buffer 2 at every clock (every cycle), and input data as necessary. At the same time as controlling the buffer control circuit 4 and the output data buffer control circuit 6, a control signal (output) to an external device is generated.

  FIG. 3 shows the configuration of the output data buffer control circuit 6 and the output signal synchronization circuit 7. The output data buffer control circuit 6 includes a data output permission register 6a, an AND circuit 6b, a selector 6c, and an AND circuit 6d. The data output permission register 6a stores a value indicating whether or not to permit data output. The AND circuit 6b outputs an AND operation result of the output of the data output permission register 6a and the control signal (input) input from the external device.

  The selector 6c selects and outputs either one of the data output permission register 6a and the AND circuit 6b. The AND circuit 6d outputs an AND operation result of the empty signal “empty” output from the output data buffer 5 and indicating whether or not the output data buffer 5 is empty and the output of the selector 6c. The output of the AND circuit 6d is a read request signal rdreq that instructs reading (output) of data from the output data buffer 5.

  The output of the data output permission register 6a is connected to the terminal of the read request signal rdreq of the output data buffer 5 via the selector 6c and the AND circuit 6d. By controlling the value of the data output permission register 6a, the output data It is possible to control the update. However, when no data is stored in the output data buffer 5, the empty signal empty is not asserted (does not become 1), so the request signal rdreq is not asserted.

  On the other hand, the request signal rdreq can be controlled by a control signal (input) from an external device. When the selector 6c selects the output of the AND circuit 6b, if the control signal (input) is not asserted, the read request signal rdreq is not asserted and output regardless of the state of the data output permission register 6a. Data is not updated. With this configuration, the output data buffer 5 can be controlled in response to a BUSY signal, a WAIT signal, a READY signal, and the like from an external device.

  The output signal synchronization circuit 7 includes flip-flops 7a and 7b, an AND circuit 7c, and a selector 7d. The flip-flop 7a holds a control signal (output) generated by the CPU 1 and output to the external device. As an enable signal for controlling the operation of the flip-flop 7a, the read request signal rdreq from the AND circuit 6d is used. With this configuration, it is possible to match the update timing of the output data with the update timing of the control signal (output).

  The flip-flop 7 b holds the empty signal empty output from the output data buffer 5. The AND circuit 7c outputs an AND operation result of the outputs of the flip-flops 7a and 7b. With this configuration, it is possible to prevent an extra signal from being output as a control signal (output) when no data is stored in the output data buffer 5 (empty signal empty = 0). The selector 7d selects one of the outputs of the flip-flop 7a and the AND circuit 7c, and outputs it to the external device as a control signal (output).

  Next, a method for realizing a communication protocol using a general request / grant / valid in this embodiment will be described. FIG. 4 shows an operation in which the interface apparatus according to the present embodiment transmits data to an external apparatus. It is assumed that 0 is stored in the data output permission register 6a in the initial state. First, when the CPU 1 confirms that sufficient data has been stored in the output data buffer 5, the CPU 1 uses the rising differentiation circuit 1g to output a pulse-like request signal REQ for requesting permission of data output from the external device. appear. When receiving the request signal REQ, the external device returns a grant signal GRT indicating permission of data output if it is in a receivable state. The value of this grant signal GRT is stored in the input control signal buffer 2.

  The CPU 1 reads the value of the grant signal GRT from the input control signal buffer 2. If the value of the read grant signal GRT is 1, the CPU 1 sets the valid signal VLD indicating the validity of the data to 1, and then stores 1 in the data output permission register 6a in the output data buffer control circuit 6. . The CPU 1 controls the output data buffer control circuit 6 in advance and sets the input of the selector 6c to the output side of the data output permission register 6a. When the value of the data output permission register 6a changes from 0 to 1, the selector 1 The output of 6c also changes from 0 to 1.

  The output of the selector 6c is input to the AND circuit 6d. An empty signal empty from the output data buffer 5 is also input to the AND circuit 6d. Since the output data buffer 5 is not empty, the empty signal empty is asserted (empty signal empty = 1). Therefore, when 1 is stored in the data output permission register 6a, the request signal rdreq, which is the output of the AND circuit 6d, becomes 1, and data is output from the output data buffer 5.

  On the other hand, the valid signal VLD generated by the CPU 1 is input to the flip-flop 7 a of the output signal synchronization circuit 7. Since the request signal rdreq is an enable signal for the flip-flop 7a, the output of the flip-flop 7a becomes 1 when the request signal rdreq becomes 1. The CPU 1 controls the output signal synchronization circuit 7 in advance and sets the input of the selector 7d to the output side of the AND circuit 7c. The output of the flip-flop 7a (valid signal VLD) and the output of the flip-flop 7b (empty signal empty = 1) are input to the selector 7d. Therefore, when the output of the flip-flop 7a changes from 0 to 1, the output of the selector 7d (valid signal VLD) also changes from 0 to 1. By the above operation, as shown in FIG. 4, the data output from the output data buffer 5 and the valid signal VLD are updated synchronously.

  FIG. 5 shows an operation in which the interface apparatus according to the present embodiment receives data from an external apparatus. When the external device determines that it is in a transmittable state, the external device outputs a request signal REQ. The value of the request signal REQ is stored in the input control signal buffer 2. The CPU 1 reads the value of the request signal REQ from the input control signal buffer 2. When the value of the read request signal REQ is 1, the CPU 1 outputs a pulse signal as a grant signal GRT to an external device using the rising differentiation circuit 1g.

  The external device that has received the grant signal GRT outputs data and also changes the valid signal VLD from 0 to 1 and outputs it. The value of the valid signal VLD is stored in the input control signal buffer 2. The CPU 1 reads the value of the valid signal VLD from the input control signal buffer 2. When the value of the read valid signal VLD is 1, since it can be determined that the data input simultaneously with the valid signal VLD and stored in the input data buffer 3 is valid, the CPU 1 controls the internal circuit I / F 8. The data is transferred from the input data buffer 3 to the internal circuit 9. The method for realizing the synchronization between the valid signal VLD and the data is the same as the method described with reference to FIG.

  Next, a method for realizing a communication protocol using general valid / busy in this embodiment will be described. FIG. 6 shows an operation in which the interface apparatus according to the present embodiment transmits data to an external apparatus. It is assumed that 0 is stored in the data output permission register 6a in the initial state. Further, it is assumed that the busy signal BSY output from the external device and indicating whether it is in the busy state is 1 in the initial state (the external device is not in the busy state). First, when the CPU 1 confirms that sufficient data is stored in the output data buffer 5, the CPU 1 sets the valid signal VLD to 1, and then stores 1 in the data output permission register 6a.

  The CPU 1 controls the output data buffer control circuit 6 in advance and sets the input of the selector 6c to the output side of the AND circuit 6b. The busy signal BSY from the external device is input to the AND circuit 6b. When the value of the data output permission register 6a changes from 0 to 1, the output of the selector 6c also changes from 0 to 1. The output of the selector 6c is input to the AND circuit 6d. The empty signal empty of the output data buffer 5 is also input to the AND circuit 6d. Since the output data buffer 5 is not empty, the empty signal empty is 1. Therefore, when 1 is stored in the data output permission register 6a, the request signal rdreq, which is the output of the AND circuit 6d, becomes 1, and data is output from the output data buffer 5.

  On the other hand, the valid signal VLD generated by the CPU 1 is input to the flip-flop 7 a of the output signal synchronization circuit 7. Since the request signal rdreq is an enable signal for the flip-flop 7a, the output of the flip-flop 7a becomes 1 when the request signal rdreq becomes 1. The CPU 1 controls the output signal synchronization circuit 7 in advance and sets the input of the selector 7d to the output side of the AND circuit 7c. The output of the flip-flop 7a (valid signal VLD) and the output of the flip-flop 7b (empty signal empty = 1) are input to the selector 7d. Therefore, when the output of the flip-flop 7a changes from 0 to 1, the output of the selector 7d (valid signal VLD) also changes from 0 to 1. By the above operation, as shown in FIG. 6, the data output from the output data buffer 5 and the valid signal VLD are updated synchronously.

  When the external device sets the busy signal BSY to 0 to notify the interface device that it is busy, the busy signal BSY is input to the AND circuit 6b. Therefore, 0 is output from the AND circuit 6b. Since the input of the selector 6c is set on the output side of the AND circuit 6b, when 0 is output from the AND circuit 6b, the output of the selector 6c becomes 0. Since this signal is input to the AND circuit 6d, the request signal rdreq, which is the output of the AND circuit 6d, becomes 0, the data in the output data buffer 5 is not updated, and the same data is output while the external device is busy. continue.

  When no data is stored in the output data buffer 5, the empty signal empty is 0, and the output of the AND circuit 7c is 0. Since the input of the selector 7d is set on the output side of the AND circuit 7c, when 0 is output from the AND circuit 7c, the output (valid signal VLD) of the selector 7d is also 0. With this operation, it is possible to prevent the external device from erroneously acquiring invalid data.

  FIG. 7 shows an operation in which the interface apparatus according to the present embodiment receives data from an external apparatus. FIG. 8 shows the configuration of the input data buffer control circuit 4 that realizes this operation. The input data buffer control circuit 4 includes an input data amount comparison value register 4a, comparison circuits 4b and 4c, and an OR circuit 4d.

  The input data amount comparison value register 4a stores a threshold value used for data amount comparison. The comparison circuit 4b outputs the data amount based on the signal usedw output from the input data buffer 3 and indicating the data amount stored in the input data buffer 3, and the threshold (≠≠) stored in the input data amount comparison value register 4a. 0) and a signal corresponding to the comparison result is output. When the amount of data based on the signal usedw matches the threshold, the comparison circuit 4b outputs 1. When the data amount based on the signal usedw does not match the threshold value, the comparison circuit 4b outputs 0.

  The comparison circuit 4c compares the data amount based on the signal usedw output from the input data buffer 3 with 0 and outputs a signal corresponding to the comparison result. When the amount of data based on the signal usedw matches 0, the comparison circuit 4c outputs 1. When the data amount based on the signal usedw does not match 0, the comparison circuit 4c outputs 0. The OR circuit 4d outputs an OR operation result of the outputs of the comparison circuits 4b and 4c. The signal output from the OR circuit 4d is input to the interrupt controller 1d of the CPU 1 as an interrupt signal.

  When data is received from an external device, the operation of the interface device is as follows. When data and a valid signal VLD are input from an external device to the interface device, the data is stored in the input data buffer 3, and the value of the valid signal VLD is stored in the input control signal buffer 2. The CPU 1 reads the value of the valid signal VLD from the input control signal buffer 2. When the value of the read valid signal VLD is 1, since it can be determined that the data input simultaneously with the valid signal VLD and stored in the input data buffer 3 is valid, the CPU 1 controls the internal circuit I / F 8. The data is transferred from the input data buffer 3 to the internal circuit 9.

  When the amount of data stored in the input data buffer 3 matches the threshold stored in the input data amount comparison value register 4a, the comparison circuit 4b outputs 1. For this reason, the OR circuit 4d outputs 1 as an interrupt signal. When the CPU 1 detects that the interrupt signal becomes 1 by the interrupt controller 1d, the CPU 1 sets the busy signal BSY to 0 and notifies the external device that it is busy.

  If the clock used for data transfer between the interface device and the external device is faster than the system clock of the interface device, the input control signal buffer 2 and the input data buffer 3 may overflow. Therefore, when the amount of data stored in the input data buffer 3 reaches the threshold value stored in the input data amount comparison value register 4a, an interrupt to the CPU 1 is generated, and the CPU 1 sets the busy signal BSY to 0. As a result, overflow of the input control signal buffer 2 and the input data buffer 3 can be prevented.

  When the data amount stored in the input data buffer 3 becomes 0 after the interface device once becomes busy by the CPU 1 setting the busy signal BSY to 0, the comparison circuit 4c outputs 1. For this reason, the OR circuit 4d outputs 1 as an interrupt signal. When the CPU 1 detects that the interrupt signal becomes 1 by the interrupt controller 1d, the CPU 1 sets the busy signal BSY to 1 to notify the external device that it is no longer busy.

  If the amount of data stored in the input data buffer 3 between the occurrence of an interrupt to the CPU 1 and the CPU 1 setting the busy signal to 0 is N, and the size of the input data buffer 3 is M, the input data amount The value set in the comparison value register 4a is smaller than (MN). In the above description, an interrupt is generated for the CPU 1 in accordance with the amount of data stored in the input data buffer 3, but the CPU 1 is instructed in accordance with the amount of control signal stored in the input control signal buffer 2. An interrupt may be generated in the same manner as.

  The method for realizing a general communication protocol has been described above, but any communication protocol is classified as one of the above communication protocols. Therefore, in order to support a new communication protocol, a program for operating the CPU may be changed. Thereby, it is possible to cope with a new communication protocol without redeveloping the ASIC. In addition, by controlling the transfer of data stored in the data buffer based on a control signal input from the CPU or an external device, it is possible to realize synchronization of data transmission or reception and control signal according to the communication protocol. it can.

  Further, the output data buffer control circuit 6 shown in FIG. 3 can realize synchronization between the change in the state of the control signal from the external device and the transfer operation of the data stored in the output data buffer 5. Further, the output signal synchronization circuit 7 shown in FIG. 3 can realize the synchronization between the transfer operation of the data stored in the output data buffer 5 and the state change of the control signal to the external device.

  Further, the input data buffer control circuit 4 shown in FIG. 8 can realize synchronization between the data transfer operation and the control signal state change without breaking the communication protocol.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 9 shows the configuration of the interface device according to the present embodiment. The interface apparatus shown in FIG. 9 is newly provided with an output control signal buffer 14 that temporarily stores a control signal (output) output from the CPU 1 to the external apparatus, as compared with the interface apparatus shown in FIG. Further, an output signal synchronization circuit 15 is provided instead of the output signal synchronization circuit 7 of FIG.

  Hereinafter, a method for realizing an SPI (Serial Peripheral Interface) according to the present embodiment will be described. FIG. 10 shows an operation in which the interface apparatus according to the present embodiment receives data from an external apparatus. FIG. 11 shows the configuration of the output data buffer control circuit 6 and the output signal synchronization circuit 15 that realize this operation.

  The output data buffer control circuit 6 includes a data output permission register 6a, an AND circuit 6b, a selector 6c, and an AND circuit 6d as in FIG. The output signal synchronization circuit 15 includes a flip-flop 15a, an AND circuit 15b, and a selector 15c. Although not shown in FIG. 11, it is assumed that an output signal synchronization circuit 15 having the same configuration is provided for each control signal.

  The flip-flop 15 a holds the empty signal empty of the output data buffer 5. The AND circuit 15b outputs an AND operation result of the control signal output of the output control signal buffer 14 and the output of the flip-flop 15a. The selector 15c selects and outputs one of the output of the AND circuit 15b, the control signal output of the output control signal buffer 14, and the control signal input of the output control signal buffer 14.

  When data is transmitted to an external device, the operation of the interface device is as follows. First, the CPU 1 sets the chip select signal CS to 1. In the output signal synchronization circuit 15 related to the chip select signal CS, the selector 15c selects and outputs the control signal input of the output control signal buffer 14.

  In the output data buffer 5, as shown in FIG. 12A, data including an address and an operation code is stored in advance by the CPU 1. After setting the chip select signal CS to 1, the CPU 1 stores 1 in the data output permission register 6a. The CPU 1 controls the output data buffer control circuit 6 in advance and sets the input of the selector 6c to the output side of the data output permission register 6a. When the value of the data output permission register 6a changes from 0 to 1, the selector 1 The output of 6c also changes from 0 to 1.

  The output of the selector 6c is input to the AND circuit 6d. An empty signal empty from the output data buffer 5 is also input to the AND circuit 6d. Since the output data buffer 5 is not empty, the empty signal empty is asserted (empty signal empty = 1). Therefore, when 1 is stored in the data output permission register 6a, the request signal rdreq output from the AND circuit 6d becomes 1, and the data shown in FIG. 12A becomes the output data buffer 5 as the data SI shown in FIG. Are output sequentially.

  Further, as shown in FIG. 12B, the output control signal buffer 14 stores a value in which 1 and 0 are alternately arranged by the CPU 1 in advance. When the CPU 1 stores 1 in the data output permission register 6a after setting the chip select signal CS to 1, the request signal rdreq, which is the output of the AND circuit 6d, becomes 1, as described above. Since this request signal rdreq is also input to the output control signal buffer 14, 1 and 0 stored in the output control signal buffer 14 are output in synchronization with the clock CLK, and are output to the flip-flop 15 a in the output signal synchronization circuit 15. Entered. The flip-flop 15a alternately outputs 1 and 0 to the AND circuit 15b.

  The CPU 1 controls the output signal synchronization circuit 15 in advance and sets the output of the selector 15c to the output side of the AND circuit 15b. Since the empty signal empty is 1, 1 and 0 are alternately output from the AND circuit 15b. The selector 15c outputs the output of the AND circuit 15b to the external device as the serial clock SCK.

  Usually, since the CPU 1 needs to calculate the ALU 1a and store the value in the general-purpose register 1b in order to output the control signal, it is difficult to generate and output a control signal whose value changes every clock in real time. It is. However, in the present embodiment, the control signal generated in advance is temporarily buffered in the output control signal buffer 14, and the control signal is output in synchronization with the clock, so that the control signal whose value changes for each clock is output. Can do. Therefore, it is possible to cope with a communication protocol in which the value of the control signal changes every clock.

(Third embodiment)
Next, a modification of the third embodiment of the present invention will be described. FIG. 13 shows a partial configuration of the interface apparatus according to the present embodiment. Configurations other than the configuration shown in FIG. 13 are the same as those in the first embodiment or the second embodiment. The input data buffer control circuit 4 of this embodiment has an input data amount comparison value register 4a, comparison circuits 4b and 4c, an OR circuit 4d, and a differentiation circuit 4e. The input data amount comparison value register 4a, the comparison circuits 4b and 4c, and the OR circuit 4d are the same as those in FIG. The differentiation circuit 4e outputs a signal corresponding to the rise and fall of the control signal input from the external device. In the present embodiment, a counter 16 and a counter buffer 17 are provided. The counter 16 counts up the value (count value) in synchronization with the clock. The counter buffer stores the count value output from the counter 16.

  In this embodiment, the value is stored in the input control signal buffer 2 only when the value of the control signal changes. Therefore, the CPU 1 cannot know the period during which the value stored in the input control signal buffer 2 is held. For this reason, the counter 16 and the counter buffer 17 are provided, and the period during which the value stored in the input control signal buffer 2 is held is counted and stored. In order to prevent overflow of the counter buffer 17, a signal usedw indicating the amount of value stored in the counter buffer 17 is input to the comparison circuits 4 b and 4 c of the input data buffer control circuit 4.

  FIG. 14 shows an operation in which the interface apparatus according to the present embodiment receives data from an external apparatus. Assume that the input control signal buffer 2 stores the value of the valid signal VLD from the external device. In the initial state, K−1 values indicating the value of the valid signal VLD are stored in the input control signal buffer 2, and the count value K−1 corresponding to them is stored in the counter buffer 17. Shall. Further, it is assumed that K is stored as the input data amount comparison value in the input data amount comparison value register 4a.

  When the valid signal VLD input from the external device changes from 0 to 1, the output of the differentiating circuit 4e changes from 0 to 1. The signal output from the differentiation circuit 4e is input to the input control signal buffer 2 and the counter buffer 17 as a write request signal wrreq instructing writing. Thus, the value (= 1) of the valid signal VLD at that time is stored in the input control signal buffer 2, and the count value (= N) output from the counter 16 is stored in the counter buffer 17. The count value N represents the length of the period when the value of the valid signal VLD is 0. The signal output from the differentiation circuit 4e is also input to the counter 16, and the count value of the counter 16 is initialized to 1 when the value of the signal changes from 0 to 1.

  As the count value stored in the counter buffer 17 increases by one, the value of the signal usedw output from the counter buffer 17 becomes K. Since this value matches the input data amount comparison value stored in the input data amount comparison value register 4a, the signal output from the comparison circuit 4b is 1, and the interrupt signal output from the OR circuit 4d is also 1. Become. As a result, an interrupt to the CPU 1 occurs.

  When an interrupt occurs, the CPU 1 sets a read request signal rdreq for the input control signal buffer 2 and the counter buffer 17 to 1, and reads a value from the input control signal buffer 2 and the counter buffer 17. Subsequently, the CPU 1 compares the K values read from the input control signal buffer 2 with the count value K read from the counter buffer 17, and the number of clocks during which the valid signal VLD is 0 or 1 is several. Determine if it was a period. For example, the period in which the valid signal VLD is 0 is N clock periods based on the last value (= 1) stored in the input control signal buffer 2 and the last value (= N) stored in the counter buffer 17. CPU1 judges that it was.

  When the period during which the valid signal VLD is 0 or 1 is known, it can be determined whether the data corresponding to the period is valid or invalid. The CPU 1 performs an operation on the data stored in the input data buffer 3 according to the above determination result. Even when the value of the valid signal VLD changes from 1 to 0, the value (= 0) of the valid signal VLD at that time is stored in the input control signal buffer 2 and the count value of the counter 16 is stored in the counter buffer 17. Stored.

  Therefore, according to the present embodiment, it is possible to realize a communication protocol that performs writing to the input control signal buffer 2 only when the state of the control signal is changed. Similarly to the above, the signal output from the differentiating circuit 4e is input to the input data buffer 3 as the write request signal wrreq, so that writing to the input data buffer 3 is performed only when the data state has changed. The communication protocol to be performed can also be realized.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

It is a block diagram which shows the structure of the interface apparatus by the 1st Embodiment of this invention. It is a block diagram which shows the structure of CPU with which the interface apparatus by the 1st Embodiment of this invention is provided. FIG. 3 is a block diagram illustrating a configuration of an output data buffer control circuit and an output signal synchronization circuit included in the interface device according to the first embodiment of the present invention. 5 is a timing chart showing an operation of transmitting data to an external device by the interface device according to the first embodiment of the present invention. 4 is a timing chart showing an operation of receiving data from an external device by the interface device according to the first embodiment of the present invention. 5 is a timing chart showing an operation of transmitting data to an external device by the interface device according to the first embodiment of the present invention. 4 is a timing chart showing an operation of receiving data from an external device by the interface device according to the first embodiment of the present invention. It is a block diagram which shows the structure of the input data buffer control circuit with which the interface apparatus by the 1st Embodiment of this invention is provided. It is a block diagram which shows the structure of the interface apparatus by the 2nd Embodiment of this invention. 12 is a timing chart illustrating an operation of an interface device according to the second embodiment of the present invention transmitting data to an external device. It is a block diagram which shows the structure of the output data buffer control circuit with which the interface apparatus by the 2nd Embodiment of this invention is provided, and an output signal synchronizing circuit. FIG. 9 is a reference diagram illustrating states of data and control signals stored in an output data buffer and an output control signal buffer included in an interface device according to a second embodiment of the present invention. It is a block diagram which shows the partial structure of the interface apparatus by the 3rd Embodiment of this invention. 12 is a timing chart illustrating an operation of an interface device according to the third embodiment of the present invention receiving data from an external device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Input control signal buffer, 3 ... Input data buffer, 4 ... Input data buffer control circuit, 5 ... Output data buffer, 6 ... Output data buffer control circuit 7, 15 ... Output signal synchronization circuit, 8 ... Internal circuit I / F, 9 ... Internal circuit, 10 ... Memory controller, 11 ... SDRAM, 12 ... FlashROM, 13. ..Bus 14 ... Output control signal buffer 16 ... Counter 17 ... Counter buffer

Claims (8)

A storage unit for storing a program for controlling communication with an external device according to a communication protocol;
A synchronization control unit that controls synchronization of data and control signals transmitted or received with the external device;
A CPU for generating the control signal to be transmitted to the external device according to the program;
An interface device. A data buffer for temporarily storing the data;
The interface device according to claim 1, wherein the synchronization control unit controls transfer of the data stored in the data buffer based on the control signal input from the CPU or the external device.   The synchronization control unit controls transfer of the data stored in the data buffer based on at least one of a value stored in a register by the CPU and a value of the control signal input from the external device The interface device according to claim 2, wherein:   The synchronization control unit controls the control signal transmitted to the external device based on a signal for controlling transfer of the data stored in the data buffer and the control signal generated by the CPU. The interface device according to claim 2 or claim 3, wherein   The synchronization control unit controls the output of the control signal generated by the CPU to the external device in accordance with the amount of the data stored in the data buffer. The interface device according to claim 4.   6. The interface device according to claim 2, further comprising an input control signal buffer for temporarily storing the control signal input from the external device.   The synchronization control unit writes the data into the data buffer or the data into the input control signal buffer only when the control signal input from the external device or the data input from the external device changes. 7. The interface device according to claim 6, wherein writing of the control signal is permitted.   The interface apparatus according to claim 2, further comprising an output control signal buffer that temporarily stores the control signal transmitted to the external apparatus.

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