JP2009010820A - Storage device, storage control method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase capacity of storage on a recording medium by compressing and then storing signals. <P>SOLUTION: An oversampling circuit 101 converts a video signal of M bits and a sampling frequency fs into a sampling frequency N×fs. A delta-sigma modulation circuit 102 converts the video signal of M bits into a video signal of 1 bit. The video signal of 1 bit and sampling frequency N×fs is then written on a recording medium 105A. Furthermore, a bit expansion circuit 107 converts the video signal of 1 bit and sampling frequency N×fs read from the recording medium 105A into the video signal of M bits. A decimation circuit 109 converts the video signal of M bits and sampling frequency fs from which a high frequency component has been removed at a low-pass filter circuit 108, into a video signal of sampling frequency fs and outputs it. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a storage device, a storage control method, and a program, and in particular, a storage device and a storage control capable of increasing a capacity that can be stored in a recording medium by compressing and storing a signal. The present invention relates to a method and a program.

  Video signals and audio signals are sampled at a predetermined sampling frequency and stored in a predetermined storage device as digital data quantized with a predetermined number of bits (see, for example, Patent Document 1).

  FIG. 1 is a block diagram illustrating an example of a configuration of a conventional video signal storage device that stores a video signal in a storage device.

  The video signal storage device 1 in FIG. 1 includes a write circuit 11, a storage device control circuit 12, a storage device 13, and a read circuit 14. The storage device 13 has a recording medium 13A therein.

  In the video signal storage device 1, a video signal having a quantization bit rate of M bits and a sampling frequency fs is input, stored (recorded) in the recording medium 13 A of the storage device 13, and read from the recording medium 13 A of the storage device 13. The output video signal is output with a quantization bit number of M bits and a sampling frequency fs. In the following description, when simply described as an M-bit video signal or the like, the number of bits represents the number of quantization bits of the video signal.

  The video signal of M bits and sampling frequency fs input to the video signal storage device 1 is supplied to the writing circuit 11. The writing circuit 11 supplies a write command to the storage device control circuit 12, and also supplies a video signal having a sampling frequency fs with M bits to the storage device control circuit 12, and stores the writing of the supplied video signal to the recording medium 13A. The apparatus control circuit 12 is made to execute.

  The storage device control circuit 12 writes the video signal having the sampling frequency fs with M bits supplied from the write circuit 11 together with the write command to the recording medium 13 A of the storage device 13 in accordance with the write command from the write circuit 11. Further, the storage device control circuit 12 reads a video signal recorded on the recording medium 13 A of the storage device 13 in accordance with a read command from the read circuit 14 and supplies the read video signal to the read circuit 14.

  The storage device 13 includes a recording medium 13A, and stores a predetermined video signal by recording the predetermined video signal on the recording medium 13A. Here, the recording medium 13A is, for example, a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only Memory), DVD (Digital Versatile Disc), etc.), a magneto-optical disk, or a semiconductor memory. It can be.

  The read circuit 14 supplies a read command to the storage device control circuit 12, and reads the video signal having the sampling frequency fs with M bits recorded on the recording medium 13 A of the storage device 13 to the storage device control circuit 12. And supply. The video signal of M bits and sampling frequency fs supplied from the storage device control circuit 12 is output to the outside of the video signal storage device 1.

  In the video signal storage device 1 configured as described above, access to the storage device 13 occurs in proportion to 2 × M × fs.

  In recent years, the number of quantization bits M or the sampling frequency fs described above tends to increase with an increase in gradation or resolution of a video display device. In this case, access to the storage device 13 also increases.

JP 2004-288365 A

  However, the amount of access to the storage device 13 within a certain time is limited to a predetermined amount or less determined by the storage device control circuit 12 and the storage device 13. In order to cope with the access amount exceeding the predetermined amount determined by the storage device control circuit 12 and the storage device 13, it is necessary to add the storage device 13 as a result, and as a result, the cost of the video signal storage device 1 is reduced. It was supposed to increase.

  The present invention has been made in view of such a situation, and it is possible to increase the capacity that can be stored in a recording medium by compressing and storing a signal.

  A storage device according to one aspect of the present invention is a storage device that stores an input signal in a predetermined recording medium. The signal having a quantization bit number of M bits and a sampling frequency fs is N times the sampling frequency N ×. Oversampling means for oversampling to fs, and the signal of M bits and sampling frequency N × fs obtained by oversampling to the signal of 1 bit and sampling frequency N × fs by performing delta-sigma modulation Conversion means for converting, recording medium control means for reading or writing the signal of 1 bit and sampling frequency N × fs to the recording medium, and 1 bit of sampling signal N × fs read from the recording medium M bit and sampling the signal Bit extension means for converting to the signal of frequency N × fs, removal means for removing high frequency components of the signal of M bits and sampling frequency N × fs, and M bits and sampling frequency N from which the high frequency components have been removed Thinning means for thinning out the xfs signal so that the sampling frequency becomes 1 / N;

  A storage control method according to one aspect of the present invention is a storage control method for a storage device that stores an input signal in a predetermined recording medium. The signal of M bits and sampling frequency N × fs obtained by over-sampling to a sampling frequency N × fs of 1 bit and delta-sigma modulation of the signal obtained by over-sampling is obtained. 1 bit and the signal having the sampling frequency N × fs is read or written to the recording medium, and the 1 bit read from the recording medium and the signal having the sampling frequency N × fs is M bits and Converted to the above sampling frequency N × fs signal, M bits And removing the high frequency component of the signal having the sampling frequency N × fs and thinning out the M bit from which the high frequency component has been removed and the signal having the sampling frequency N × fs so that the sampling frequency becomes 1 / N. Including.

  The program according to one aspect of the present invention is a program for causing a computer to execute a storage control process for storing an input signal in a predetermined recording medium, wherein the signal having a quantization bit number of M bits and a sampling frequency fs is Oversampling to N times the sampling frequency N × fs, the signal of M bits and sampling frequency N × fs obtained by being oversampled is subjected to delta-sigma modulation to obtain 1 bit and sampling frequency N × fs. The signal is converted into the signal, the signal having 1 bit and the sampling frequency N × fs is read or written to the recording medium, and the signal having 1 bit and the sampling frequency N × fs read from the recording medium is converted into M Bit and sampling frequency N × fs The signal is converted into the signal, the high frequency component of the signal of M bits and sampling frequency N × fs is removed, and the signal of M bit and sampling frequency N × fs from which the high frequency component has been removed is converted to a sampling frequency of 1 / Causing the computer to execute storage control processing including a step of thinning out to N.

  In one aspect of the present invention, an M-bit signal obtained by over-sampling a signal having a sampling frequency fs with a quantization bit number of M bits and an N-times sampling frequency N × fs, and the sampling frequency N is obtained. The signal of xfs is converted into a signal of 1 bit and a sampling frequency Nxfs by performing delta-sigma modulation. Also, the 1-bit and sampling frequency N × fs signal read from the recording medium is converted into an M-bit and sampling frequency N × fs signal, and the high-frequency component is removed from the M-bit and sampling frequency N × fs. Are thinned out so that the sampling frequency becomes 1 / N.

  According to an aspect of the present invention, the capacity that can be stored in the recording medium can be increased by compressing and storing the signal.

  Embodiments of the present invention will be described below. Correspondences between the constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is intended to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even if there is an embodiment which is described in the specification or the drawings but is not described here as an embodiment corresponding to the constituent elements of the present invention, that is not the case. It does not mean that the form does not correspond to the constituent requirements. Conversely, even if an embodiment is described herein as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

  A storage device according to one aspect of the present invention is a storage device that stores an input signal in a predetermined recording medium (for example, the video signal storage device 100 in FIG. 2), and the number of quantization bits is M bits and the sampling frequency fs. Oversampling means (for example, the oversampling circuit 101 in FIG. 2) that oversamples the signal to a sampling frequency N × fs that is N times the sampling frequency fs; The conversion means (for example, the delta sigma modulation circuit 102 in FIG. 2) that converts the signal of xfs to the signal of 1 bit and sampling frequency Nxfs by performing delta sigma modulation, and 1 bit and sampling frequency N Xfs of the signal to the recording medium Recording medium control means for performing reading or writing (for example, the writing circuit 103 and the reading circuit 106 in FIG. 2), 1 bit read from the recording medium and the signal of the sampling frequency N × fs are converted into M bits and Bit expansion means (for example, the bit expansion circuit 107 in FIG. 2) for converting the signal having the sampling frequency N × fs, and removal means (for example, the high frequency component of the signal having M bits and the sampling frequency N × fs). The low-pass filter circuit 108 in FIG. 2 and thinning means (for example, the decimation in FIG. 2) that thins out the M bit from which the high-frequency component has been removed and the signal having the sampling frequency N × fs so that the sampling frequency becomes 1 / N. Circuit 109).

  A storage control method according to one aspect of the present invention is a storage control method for a storage device that stores an input signal in a predetermined recording medium. Oversampling to N times the sampling frequency N × fs (for example, step S1 in FIG. 7), and performing delta-sigma modulation on the M bits obtained by oversampling and the signal having the sampling frequency N × fs Is converted into the signal of 1 bit and sampling frequency N × fs (for example, step S2 in FIG. 7), and the signal of 1 bit and sampling frequency N × fs is read or written to the recording medium (for example, FIG. 7 step S3), 1 bit read from the recording medium. And the signal having the sampling frequency N × fs is converted into the signal having M bits and the sampling frequency N × fs (for example, step S12 in FIG. 8), and the high frequency component of the signal having M bits and the sampling frequency N × fs is converted. (For example, step S13 in FIG. 8), the M-bit signal from which the high frequency component has been removed and the signal having the sampling frequency N × fs are thinned out so that the sampling frequency becomes 1 / N (for example, in FIG. 8). Step S14) includes a step.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 shows a configuration example of an embodiment of a video signal storage device to which the present invention is applied.

  2, the video signal storage device 100 includes an oversampling circuit 101, a delta-sigma modulation circuit 102, a writing circuit 103, a storage device control circuit 104, a storage device 105, a reading circuit 106, a bit expansion circuit 107, a low-pass filter circuit 108, And a decimation circuit 109. The storage device 105 has a recording medium 105A therein.

  The video signal storage device 100 receives a video signal having a quantization frequency of M bits and a sampling frequency fs. The video signal storage device 100 converts the input video signal into a video signal of a predetermined format, and then stores it in the recording medium 105 </ b> A of the storage device 105. Also, the video signal storage device 100 converts the video signal read from the recording medium 105A of the storage device 105 into a video signal having M bits and a sampling frequency fs, and outputs the video signal to the outside.

  More specifically, the oversampling circuit 101 performs N-times oversampling on the M bits input from the outside of the video signal storage device 100 and the video signal having the sampling frequency fs, and the resulting M bits and A video signal having a sampling frequency N × fs is supplied to the delta-sigma modulation circuit 102. Here, the oversampling multiple N is an integer smaller than the quantization bit number M.

  The delta sigma modulation circuit 102 converts a video signal having M bits and a sampling frequency N × fs into a video signal having 1 bit and a sampling frequency N × fs by performing delta sigma modulation. The converted video signal of 1 bit and sampling frequency N × fs is supplied to the writing circuit 103.

  The writing circuit 103 supplies a write command to the storage device control circuit 104 and also supplies a video signal of 1 bit and a sampling frequency N × fs to the storage device control circuit 104 and supplies the storage device control circuit 104 with the video signal. The video signal is written into the recording medium 105 A of the storage device 105.

  The storage device control circuit 104 writes the 1-bit and sampling frequency N × fs video signal supplied from the write circuit 103 to the recording medium 105 A of the storage device 105 in accordance with the write command from the write circuit 103. Further, the storage device control circuit 104 reads the video signal of 1 bit and sampling frequency N × fs recorded in the recording medium 105 A of the storage device 105 in accordance with a read command from the read circuit 106 and supplies the read video signal to the read circuit 106. To do.

  The storage device 105 includes a recording medium 105A, and stores a video signal by writing a video signal of 1 bit and a sampling frequency N × fs to the recording medium 105A. Here, as in the case of FIG. 1, the recording medium 105A is, for example, a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only Memory), DVD (Digital Versatile Disc), etc.). , Magneto-optical disk, or semiconductor memory.

  The read circuit 106 supplies a read command to the storage device control circuit 104, and the video signal of 1 bit and sampling frequency N × fs recorded in the recording medium 105 A of the storage device 105 is supplied to the storage device control circuit 104. Read and feed. The video signal supplied from the storage device control circuit 104 is supplied to the bit extension circuit 107.

  The bit expansion circuit 107 expands the video signal of 1 bit and sampling frequency N × fs supplied from the readout circuit 106 to the same M bits as the input signal, and the resulting video of M bit and sampling frequency N × fs The signal is supplied to the low pass filter circuit 108.

  The low-pass filter circuit 108 removes the high-frequency component of the supplied video signal of M bits and sampling frequency N × fs, and supplies the video signal of M bits and sampling frequency N × fs after removal to the decimation circuit 109. As a result, the noise component of the video signal having M bits and the sampling frequency N × fs is removed.

  The decimation circuit 109 performs a thinning process for thinning out the M-bit and sampling frequency N × fs video signals supplied from the low-pass filter circuit 108 so that the sampling frequency becomes 1 / N. The decimation circuit 109 outputs a video signal having M bits and a sampling frequency fs obtained as a result of the thinning process to the outside of the video signal storage device 100.

  FIG. 3 is a block diagram illustrating a detailed configuration example of the oversampling circuit 101.

  The oversampling circuit 101 is composed of two delay circuits, a delay circuit 201 and a delay circuit 202.

  In the oversampling circuit 101, a video signal having M bits and a sampling frequency fs is input to the delay circuit 201 from the outside of the video signal storage device 100, and is also external to the video signal storage device 100 or inside the video signal storage device 100. A clock signal having a frequency (clock frequency) fs is input to the delay circuit 201 and a clock signal having a frequency N × fs is input to the delay circuit 202 from an oscillator (not shown) or the like.

  The delay circuit 201 latches the input video signal of M bits and sampling frequency fs at the clock frequency fs. The delay circuit 202 latches the signal from the delay circuit 201 at the clock frequency fs. As a result, in the oversampling circuit 101, the video signal having the sampling frequency fs is converted into a video signal having the sampling frequency N × fs and output.

  FIG. 4 is a block diagram illustrating a detailed configuration example of the delta-sigma modulation circuit 102.

  The delta sigma modulation circuit 102 includes a subtracter 301, an adder 302, a delay circuit 303, a quantization circuit 304, and a bit extension circuit 305.

  The subtractor 301 subtracts the M bit and sampling frequency N × fs video signal output from the bit extension circuit 305 from the input M bit and sampling frequency N × fs video signal, and the result is the adder 302. To supply.

  The adder 302 adds the video signal supplied from the subtracter 301 and the video signal output from the delay circuit 303, and supplies the result to the delay circuit 303. More specifically, the adder 302 adds the video signal supplied from the subtracter 301 and the video signal output by the adder 302 itself at the time one clock before, and supplies the result to the delay circuit 303. .

  The delay circuit 303 delays the video signal supplied from the adder 302 by a time corresponding to one clock, and supplies it to the adder 302 and the quantization circuit 304.

  The quantization circuit 304 binarizes the video signal supplied from the delay circuit 303. The video signal binarized and output by the quantization circuit 304 and having a sampling frequency of N × fs is output to the writing circuit 103 (FIG. 2) and also to the bit expansion circuit 305.

  The bit expansion circuit 305 expands the number of bits so that the 1-bit and sampling frequency N × fs video signal supplied from the quantization circuit 304 becomes an M-bit video signal and supplies the video signal to the subtractor 301.

  FIG. 5 is a block diagram illustrating a detailed configuration example of the low-pass filter circuit 108.

  The low-pass filter circuit 108 includes Q delay circuits 401-1 to 401-Q, multipliers 402-1 to 402-Q, storage circuits 403-1 to 403-Q, and an adder 404. .

  The delay circuit 401-q (q = 1, 2,..., Q) delays the video signal input thereto for a predetermined time, and then delays the delay circuit 401- (q + 1) and the multiplier 402-q in the subsequent stage. To supply. However, since no delay circuit is provided in the subsequent stage of the delay circuit 401-Q, the delay circuit 401-Q supplies the delayed video signal only to the multiplier 402-Q.

The multiplier 402-q multiplies the video signal supplied from the delay circuit 401-q by the coefficient k _q supplied from the storage circuit 403-q and supplies the multiplication result to the adder 404. Storage circuit 403-q stores a coefficient k _q, and supplies the coefficient k _q to the multiplier 402-q.

  The adder 404 adds the video signals supplied from the multipliers 402-1 to 402-Q and outputs the addition result.

  The number of delay circuits 401-1 to 401-Q, multipliers 402-1 to 402-Q, and memory circuits 403-1 to 403-Q in the low-pass filter circuit 108 may be any number as long as it is two or more. The higher the number, the better the high-frequency cutoff characteristics, but on the other hand, the circuit scale increases.

  FIG. 6 is a block diagram illustrating a detailed configuration example of the decimation circuit 109.

  The decimation circuit 109 is composed of two delay circuits, a delay circuit 501 and a delay circuit 502.

  In the decimation circuit 109, a video signal having M bits and a sampling frequency N × fs is input from the low-pass filter circuit 108 to the delay circuit 501, and is not shown outside the video signal storage device 100 or inside the video signal storage device 100. A clock signal having a frequency (clock frequency) N × fs is input to the delay circuit 501 and a clock signal having the frequency fs is input to the delay circuit 502 from an oscillator or the like.

  The delay circuit 501 latches an input video signal having M bits and a sampling frequency N × fs at a clock frequency N × fs. The delay circuit 502 latches the video signal from the delay circuit 501 at the clock frequency fs. As a result, in the decimation circuit 109, the video signal having the sampling frequency N × fs is converted into a video signal having the sampling frequency fs and output.

  Next, a writing process, which is a process of writing an input video signal to the recording medium 105A of the storage device 105, in the video signal storage device 100 will be described with reference to the flowchart of FIG.

  First, in step S1, the oversampling circuit 101 oversamples a video signal having M bits and a sampling frequency fs input from the outside of the video signal storage device 100 N times. As a result, the video signal having M bits and the sampling frequency N × fs after oversampling is supplied to the delta-sigma modulation circuit 102.

  In step S2, the delta-sigma modulation circuit 102 converts the M-bit signal into a 1-bit signal string by performing delta-sigma modulation. As a result, a video signal having 1 bit and a sampling frequency of N × fs is supplied to the writing circuit 103.

  In step S <b> 3, the writing circuit 103 supplies a write command to the storage device control circuit 104 and also supplies a video signal having 1 bit and a sampling frequency N × fs to the storage device control circuit 104, whereby the storage device control circuit 104. On the other hand, the supplied video signal of 1 bit and sampling frequency N × fs is written into the recording medium 105 A of the storage device 105. After the writing of all the supplied video signals is completed, the process is finished.

  Next, a reading process of the video signal storage device 100, which is a process of reading the video signal written in the recording medium 105A of the storage device 105, will be described with reference to the flowchart of FIG.

  First, in step S <b> 11, the read circuit 106 supplies a read command to the storage device control circuit 104, so that the storage device control circuit 104 receives a video signal of 1 bit and a sampling frequency N × fs in the storage device 105. Read from the recording medium 105A. The reading circuit 106 supplies the 1-bit video signal having the sampling frequency N × fs supplied from the storage device control circuit 104 to the bit expansion circuit 107.

  In step S12, the bit extension circuit 107 extends the 1-bit and sampling frequency N × fs video signal supplied from the readout circuit 106 to the same M-bit video signal as the input signal. The resulting M bit and sampling frequency N × fs video signal is supplied to the low-pass filter circuit 108.

  In step S13, the low-pass filter circuit 108 removes the high-frequency component of the video signal having M bits and the sampling frequency N × fs. The video signal having M bits and the sampling frequency N × fs after the removal is supplied to the decimation circuit 109.

  In step S14, the decimation circuit 109 thins out the video signal of M bits and sampling frequency N × fs supplied from the low-pass filter circuit 108 so that the sampling frequency becomes 1 / N. Then, the decimation circuit 109 outputs the video signal having the thinned M bits and the sampling frequency fs to the outside of the video signal storage device 100 and ends the processing.

  As described above, the video signal storage device 100 converts the input video signal having M bits and the sampling frequency fs into the sampling frequency N × fs in the oversampling circuit 101 and then the 1-bit in the delta-sigma modulation circuit 102. It is converted into a video signal and written to the recording medium 105A as a video signal of 1 bit and sampling frequency N × fs. Also, the video signal storage device 100 converts the 1-bit and sampling frequency N × fs video signal read from the recording medium 105A into an M-bit video signal in the bit expansion circuit 107, and the low-pass filter circuit 108 converts the video signal to high. After removing the band components, the decimation circuit 109 converts the signal into a video signal having a sampling frequency fs, and outputs the video signal as an M signal having a sampling frequency fs.

  Accordingly, since the video signal is compressed and stored (recorded) in the recording medium 105A, the capacity that can be stored in the storage device 105 can be increased. As a result, when a conventional video signal having M bits and sampling frequency fs is stored as it is, even if the storage capacity is increased by adding a storage device, the necessary video signal can be obtained without adding a storage device. Can be remembered. That is, an increase in cost due to the addition of a storage device can be prevented.

  The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software executes various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a program recording medium in a general-purpose personal computer or the like.

  FIG. 9 is a block diagram illustrating a hardware configuration example of a computer that executes the above-described series of processing by a program.

  In a computer, a CPU (Central Processing Unit) 601, a ROM (Read Only Memory) 602, and a RAM (Random Access Memory) 603 are connected to each other by a bus 604.

  An input / output interface 605 is further connected to the bus 604. The input / output interface 605 includes an input unit 606 including a keyboard, a mouse, and a microphone, an output unit 607 including a display and a speaker, a storage unit 608 including a hard disk and a nonvolatile memory, and a communication unit 609 including a network interface. A drive 610 for driving a removable medium 611 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is connected.

  In the computer configured as described above, the CPU 601 loads the program stored in the storage unit 608 to the RAM 603 via the input / output interface 605 and the bus 604 and executes the program, for example. Processing or reading processing is performed.

  The program executed by the computer (CPU 601) is, for example, a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only Memory), DVD (Digital Versatile Disc), etc.), a magneto-optical disk, or a semiconductor. It is recorded on a removable medium 611 that is a package medium composed of a memory or the like, or provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.

  The program can be installed in the storage unit 608 via the input / output interface 605 by attaching the removable medium 611 to the drive 610. Further, the program can be received by the communication unit 609 via a wired or wireless transmission medium and installed in the storage unit 608. In addition, the program can be installed in the ROM 602 or the storage unit 608 in advance.

  The program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.

  In the example described above, the example in which the video signal is stored in the recording medium 105A of the video signal storage device 100 has been described. However, the same processing can be performed for other signals other than the video signal, for example, an audio signal. It is.

  In addition, in the present specification, the steps described in the flowcharts are executed in parallel or individually even if they are not necessarily processed in time series, as well as processes performed in time series in the described order. It also includes processing.

  The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows an example of a structure of the conventional video signal storage device. It is a block diagram which shows the structural example of one Embodiment of the video signal storage device to which this invention is applied. It is a block diagram which shows the detailed structural example of an oversampling circuit. It is a block diagram which shows the detailed structural example of a delta-sigma modulation circuit. It is a block diagram which shows the detailed structural example of a low-pass filter circuit. It is a block diagram which shows the detailed structural example of a decimation circuit. It is a flowchart explaining the write-in process of a video signal storage device. It is a flowchart explaining the read-out process of a video signal storage device. It is a block diagram which shows the structural example of one Embodiment of the computer to which this invention is applied.

Explanation of symbols

  100 video signal storage device, 101 oversampling circuit, 102 delta-sigma modulation circuit, 103 writing circuit, 104 storage device control circuit, 105 storage device, 105A recording medium, 106 reading circuit, 107 bit expansion circuit, 108 low-pass filter circuit, 109 Decimation circuit

Claims (3)

In a storage device for storing an input signal in a predetermined recording medium,
Oversampling means for oversampling the signal having a quantization bit rate of M bits and a sampling frequency fs to N times the sampling frequency N × fs;
Conversion means for converting the signal of M bits and sampling frequency N × fs obtained by being oversampled into the signal of 1 bit and sampling frequency N × fs by performing delta-sigma modulation;
Recording medium control means for reading or writing the signal of 1 bit and sampling frequency N × fs with respect to the recording medium;
Bit extension means for converting the signal of 1 bit and sampling frequency N × fs read from the recording medium into the signal of M bit and sampling frequency N × fs;
Removing means for removing high-frequency components of the signal having M bits and a sampling frequency of N × fs;
A storage device comprising: thinning means for thinning out the M-bit signal from which the high-frequency component has been removed and the sampling frequency N × fs so that the sampling frequency becomes 1 / N. In a storage control method of a storage device for storing an input signal in a predetermined recording medium,
Oversampling the signal having a quantization bit rate of M bits and a sampling frequency fs to N times the sampling frequency N × fs,
The M bit and the sampling frequency N × fs obtained by being oversampled are converted into the signal of 1 bit and the sampling frequency N × fs by performing delta-sigma modulation,
1 bit and a sampling frequency N × fs of the signal is read or written to the recording medium,
Converting the signal of 1 bit and sampling frequency N × fs read from the recording medium into the signal of M bit and sampling frequency N × fs,
Removing high-frequency components of the signal with M bits and sampling frequency N × fs,
A storage control method including a step of thinning out the M-bit signal from which the high frequency component has been removed and the sampling frequency N × fs so that the sampling frequency becomes 1 / N. In a program for causing a computer to execute storage control processing for storing an input signal in a predetermined recording medium,
Oversampling the signal having a quantization bit rate of M bits and a sampling frequency fs to N times the sampling frequency N × fs,
The M bit and the sampling frequency N × fs obtained by being oversampled are converted into the signal of 1 bit and the sampling frequency N × fs by performing delta-sigma modulation,
1 bit and a sampling frequency N × fs of the signal is read or written to the recording medium,
Converting the signal of 1 bit and sampling frequency N × fs read from the recording medium into the signal of M bit and sampling frequency N × fs,
Removing high-frequency components of the signal with M bits and sampling frequency N × fs,
A program for causing a computer to execute a storage control process including a step of thinning out the M bit from which high-frequency components have been removed and the sampling frequency N × fs so that the sampling frequency becomes 1 / N.

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