JP2009010621A - Digital broadcast demodulation device, and digital broadcast demodulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent deterioration of receiving characteristics caused by a spurious component and to suppress power consumption. <P>SOLUTION: A digital broadcast demodulation device 30 receives a signal from a tuner and demodulates the signal from the tuner using an internal clock synchronous with a reference signal. The digital broadcast demodulation device 30 includes internal clock generating means 34 and 35 for generating the internal clock, and internal clock frequency controlling means 36 and 37 for performing such control as to switch the frequency of the internal clock to a frequency which never causes the corresponding received channel and spurious component according to the received channel. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a digital broadcast demodulating apparatus and a digital broadcast demodulating method, and more particularly to a digital broadcast demodulating apparatus and a digital broadcast demodulating which receive an output signal from a tuner and perform predetermined demodulation processing using an internal clock synchronized with a reference signal. Regarding the method.

  In recent years, terrestrial digital broadcasting (one-segment broadcasting) for mobile terminals has been started. For example, one-segment broadcasting that is used by being inserted into a portable terminal such as a mobile phone or PDA having a reception function of one-segment broadcasting or a USB terminal of a computer is used. A receiving device or the like is provided.

  FIG. 1 is a block diagram schematically showing an example of the overall configuration of a digital broadcast receiver to which a digital broadcast demodulator is applied, and shows an example of a mobile phone having a one-segment broadcast reception function.

  In FIG. 1, reference numeral 1 is an antenna, 2 is a tuner (RF unit), 3 is a digital broadcast demodulator (OFDM demodulator), 4 is a digital broadcast receiving module (one-segment broadcast receiving module), and 5 is image / audio processing. Reference numeral 6 denotes a CPU, 7 denotes a display, and 8 denotes a speaker.

  As shown in FIG. 1, for example, a one-segment broadcasting receiver includes an antenna 1, a one-segment broadcasting reception module (front-end unit) 4 that receives a signal (UHF signal) of each channel via the antenna 1, and a one-segment broadcasting An image / sound processing unit (Back-end unit) 5 that processes a digital signal from the broadcast receiving module 4, a CPU 6, a display 7 that displays an image, and a speaker 8 that outputs sound are provided.

  The one-segment broadcasting reception module 4 includes an RF unit 2 that once converts a signal of a reception channel into an intermediate frequency signal (IF signal), and an OFDM demodulation unit that reproduces a digital signal (MPEG2, TS: transport stream) from the IF signal. 3 is provided.

  The TS signal from the OFDM demodulator 3 is processed by the image / sound processor 5, the processed image is displayed on the display 7, and the processed sound is output from the speaker 8. Here, the one-seg broadcast receiving module 4 and the image / sound processing unit 5 perform processing in accordance with the control of the CPU 6 of the main body of a mobile phone or the like, for example.

  Note that the digital broadcast receiver is not limited to the one for receiving the one-segment broadcast, and the digital broadcast receiver is not limited to the one installed in the mobile phone.

FIG. 2 is a block diagram showing an example of a conventional digital broadcast demodulator.
As shown in FIG. 2, a conventional digital broadcast demodulator (OFDM demodulator) 300 receives a signal and a reference clock from a tuner (RF unit) 2 and outputs TS data and a TS clock. A / D conversion circuit 301, demodulation processing circuit 302, error correction circuit 303, PLL circuit 304, and frequency divider circuit 305 are provided.

  The A / D conversion circuit 301 receives a signal (IF signal) from the RF unit 2, performs analog / digital conversion according to the clock (internal clock) from the frequency dividing circuit 305, and the demodulation processing circuit 302 The output signal of the D conversion circuit 301 is demodulated in accordance with the clock from the frequency dividing circuit 305, and the error correction circuit 303 performs error correction on the output signal of the demodulation processing circuit 302 in accordance with the clock from the frequency dividing circuit 305, and TS Output data.

  The PLL circuit 304 receives the reference clock and outputs a signal synchronized with the reference clock to the frequency dividing circuit 305. The frequency dividing circuit 305 divides the output signal of the PLL circuit 304 and performs A / D conversion. A predetermined frequency-divided clock is supplied to each of the circuit 301, the demodulation processing circuit 302, and the error correction circuit 303, and the TS clock is output to the image / audio processing unit 5 described above.

  The demodulation processing circuit 303 demodulates the output signal of the A / D conversion circuit in accordance with the clock from the frequency dividing circuit 305 and outputs an MPEG2 TS signal via the error correction circuit 303.

  By the way, as a conventional device for digitizing and detecting a received signal, first and second RF frequency signals are digitized at first and second clock rates, respectively, to generate first and second digital signals. Measuring the signal quality of the first and second digital signals and selecting one of the first and second digital signals based on the measured quality of the first and second signals An analog / digital converter is operated by using one of the digital signals thus produced to avoid a decrease in sensitivity and accuracy of a wideband receiver (see, for example, Patent Document 1).

  Further, conventionally, data corresponding to the frequency error of the down converter of a plurality of antennas is obtained from the operation result of the synchronous pull-in circuit or the AFC circuit and stored in a memory, and the frequency error corresponding to the antenna is changed every time the antenna is switched. There has also been proposed a receiver that reads out data, converts it into a voltage, and inputs it to a voltage controlled oscillator so as to obtain a normal reception state in a short time (see, for example, Patent Document 2).

Japanese National Patent Publication No. 11-504192 Japanese Patent Laid-Open No. 06-014072

  Conventionally, for example, in a fine one-seg broadcast receiving module for a portable terminal as described above, harmonics of the TS output frequency appear as spurious in the RF stage of the tuner, degrading the reception characteristics of the demodulation device (for example, about 5 dB) Deteriorated).

  In addition, for example, it is conceivable to increase the clock frequency of the demodulation processing circuit to widen the interval between harmonics and avoid spurious generation within the desired band. In this case, however, the demodulation processing circuit is increased as the clock frequency is increased. Power consumption becomes large (for example, about 17% larger).

  The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a digital broadcast demodulating apparatus and a digital broadcast demodulating method capable of suppressing deterioration of reception characteristics due to spurious. Another object of the present invention is to provide a digital broadcast demodulating device and a digital broadcast demodulating method that can suppress an increase in power consumption.

  According to a first aspect of the present invention, there is provided a digital broadcast demodulator that receives a signal from a tuner and demodulates the signal from the tuner using an internal clock synchronized with a reference signal. Digital clock comprising: internal clock generation means for generating; and internal clock frequency control means for controlling switching of the frequency of the internal clock to a frequency that does not generate spurious and the reception channel according to the reception channel. A broadcast demodulator is provided.

  According to a second aspect of the present invention, there is provided a digital broadcast demodulating method for receiving a signal from a tuner and demodulating the signal from the tuner using an internal clock synchronized with a reference signal. And a method of selecting and generating an internal clock having a frequency that does not generate spurious with the reception channel among at least two internal clocks having different frequencies. Is done.

  According to the present invention, it is possible to provide a digital broadcast demodulating device and a digital broadcast demodulating method capable of suppressing deterioration of reception characteristics due to spurious.

  Hereinafter, embodiments of a digital broadcast demodulating apparatus and a digital broadcast demodulating method according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram showing an embodiment of a digital broadcast demodulator according to the present invention.
As shown in FIG. 3, the digital broadcast demodulator (OFDM demodulator) 30 of this embodiment receives a signal and a reference clock from the tuner (RF unit) 2 and outputs TS data and a TS clock. Like the digital broadcast demodulator 300 shown in FIG. 2, the A / D converter circuit 31, the demodulator circuit 32, the error correction circuit 33, the PLL circuit 34, and the frequency divider circuit 35 are provided. Furthermore, the digital broadcast demodulator 30 of this embodiment includes a memory 36 and a frequency division ratio selection circuit 37.

  The A / D conversion circuit 31 receives a signal (IF signal) from the RF unit 2 and performs analog / digital conversion in accordance with a clock from the frequency dividing circuit 35. Further, the demodulation processing circuit 32 includes an A / D conversion circuit 31. The error correction circuit 33 performs error correction on the output signal of the demodulation processing circuit 32 according to the clock from the frequency dividing circuit 35 and outputs TS data. .

  The PLL circuit 34 receives the reference clock and outputs a signal synchronized with the reference clock to the frequency dividing circuit 35. The frequency dividing circuit 35 divides the output signal of the PLL circuit 34 and performs A / D conversion. The circuit 31, the demodulation processing circuit 32, and the error correction circuit 33 are each supplied with a predetermined frequency-divided clock, and the TS clock is output to the image / audio processing unit 5.

  The demodulation processing circuit 33 demodulates the output signal of the A / D conversion circuit in accordance with the clock from the frequency dividing circuit 35 and outputs an MPEG2 TS signal via the error correction circuit 33.

  Here, the frequency division ratio selection circuit 37 stores in advance a memory 36 in order to prevent, for example, harmonics of the TS output frequency from appearing as spurious in the RF unit 2 (RF stage of the tuner 2) according to the received channel. The frequency dividing ratio of the frequency dividing circuit 35 is controlled using the data stored in.

  The data stored in the memory 36 in advance includes, for example, a channel that generates spurious by a 2.08695 MHz clock (first internal clock having a first frequency), and a 2.4 MHz that does not generate spurious with the channel. The data is a combination of clocks (second internal clocks of the second frequency).

  Thereby, the clock output from the frequency dividing circuit 35 to the A / D conversion circuit 31, the demodulation processing circuit 32, and the error correction circuit 33 has a frequency at which the harmonics of the clock do not appear as spurious in the RF unit 2. Be controlled.

  FIG. 4 is a diagram conceptually showing the relationship between the frequency band of terrestrial digital broadcasting (one-segment broadcasting) for mobile terminals as an example of digital broadcasting and the clock used in one embodiment of the digital broadcasting demodulating device of the present invention. It is.

  As shown in FIG. 4, specifically, 17 channels of UHF broadcasting (one-segment broadcasting) have a center frequency of 497.143 MHz and a bandwidth of 428 KHz, and 18 channels have a center frequency of 503.143 MHz and a bandwidth of 428 KHz. The 19 channels have a center frequency of 509.143 MHz and a band of 428 KHz.

  At this time, in the digital broadcast demodulator 30 of this embodiment, for example, when 17 channels are selected and received, a 2.08695 MHz clock (first internal clock of the first frequency) is used. When 18 channels and 19 channels are selected and received, a 2.4 MHz clock (a second internal clock having a second frequency) is used.

  That is, when the low frequency 2.08695 MHz clock does not generate spurious with the reception channel (for example, 17 channels), the 2.08695 MHz clock is used to reduce the power consumption in the digital broadcast demodulator 30. Suppresses the increase, and if the 2.08695 MHz clock generates spurs with the receive channel (for example, 18 and 19 channels), it generates spurs with all channels, although at a higher frequency than 2.08695 MHz. A 2.4 MHz clock is used.

  For example, when the reception channel is 18 channels, a 2.4 MHz clock is used. At this time, power consumption in the digital broadcast demodulator 30 is larger than when a 2.08695 MHz clock is used. Needless to say.

  As described above, according to the present embodiment, when the first internal clock with a low frequency (2.08695 MHz clock) does not generate spurious with the reception channel, the first internal clock is used. When the clock generates spurious signals and reception channels, it uses the second internal clock (2.4 MHz clock), which has a high frequency and does not generate spurious signals, thereby suppressing degradation of reception characteristics due to spurious signals. In addition, an increase in power consumption can be suppressed.

  Note that the second internal clock is not a clock having a frequency that does not generate spurious with all the reception channels (2.4 MHz clock), but is a frequency that is different from the first internal clock and is a reception channel that generates spurious with the first internal clock. On the other hand, it is also possible to use a clock having a frequency that does not cause spurious. Further, the second internal clock can be a plurality of clocks having different frequencies from the first internal clock.

  5 and 6 are diagrams specifically showing the relationship between the frequency band used in one-segment broadcasting and the clock used in one embodiment of the digital broadcast demodulating apparatus of the present invention. Here, FIG. 5 shows the relationship between the one-segment band of UHF channel 13 to 62 and the internal clock (first internal clock) of 2.08695 MHz, and FIG. 6 shows the UHF channel 13 to 62. The one seg band and the 2.4 MHz internal clock (second internal clock) are shown.

  First, as shown in FIG. 5, since the first internal clock of 2.08695 MHz includes its harmonics in the one-segment band of a predetermined channel, spurious is generated in the RF stage of the tuner in the predetermined channel. As a result, reception characteristics are degraded.

  Specifically, for example, a harmonic of 241 times the first internal clock (2.08695 MHz × 241 = 502.95495 MHz) matches the vicinity of the minimum frequency in 18 channels with a one-segment band of 502.929 MHz to 503.357 MHz. Spurious is generated, and 244 times higher harmonics of the internal clock (2.08695 MHz × 244 = 5099.2158 MHz) are spurious because the one-seg band coincides with the vicinity of the highest frequency in 19 channels from 508.929 MHz to 509.357 MHz. Will occur. Note that in “OUT at minimum frequency” and “OUT at maximum frequency” in FIG. 5, a channel where “1” is generated is a channel in which spurious is generated by the first internal clock of 2.08695 MHz (the minimum frequency of each one-segment band). Side or maximum frequency side).

  On the other hand, as shown in FIG. 6, since the second internal clock of 2.4 MHz does not match the one-segment band of all channels 1 to 62, the spurious is not generated for all channels. It does not occur.

  In the present embodiment, a channel in which spurious is not generated (specifically, channels 13 to 17; 20 to 25; 28 to 33; 36 to 41) with respect to the first internal clock of 2.08695 MHz that requires low frequency and low power consumption. 44 to 49; 52 to 57 and 60 to 62), the first internal clock is used, and a channel (specifically, channels 18, 19; 26, 27) in which the first internal clock and spurious are generated. 34, 35; 42, 43; 50, 51 and 58, 59), a 2.4 MHz second internal clock that does not generate spurious with these channels is used.

  As described above, according to the present embodiment, when the first internal clock with a low frequency (2.08695 MHz clock) does not generate spurious with the reception channel, the first internal clock is used. When the clock generates spurious signals and reception channels, it uses the second internal clock (2.4 MHz clock), which has a high frequency and does not generate spurious signals, thereby suppressing degradation of reception characteristics due to spurious signals. In addition, an increase in power consumption (power consumption of the demodulator) can be suppressed.

  FIG. 7 is a diagram for explaining the operation of the frequency dividing circuit in one embodiment of the digital broadcast demodulating apparatus according to the present invention.

  As apparent from FIG. 7, the frequency dividing circuit 35 receives a 192 MHz signal from the PLL circuit 34 to which the 16 MHz reference clock is input, and, for example, according to the control signal from the frequency dividing ratio selecting circuit 37, for example, 17 When receiving a channel, a 2.086695 MHz clock divided by 80 is output, and when receiving 18 and 19 channels, a 2.4 MHz clock divided by 92 is output. Therefore, spurious is prevented from being generated in the RF unit 2 due to the harmonics of the clock from.

  In FIG. 7, the sampling frequency of the A / D conversion circuit 31, the operation clock frequency of the demodulation processing circuit 32, and the operation clock frequency of the error correction circuit 33 are all the same (2.08695 MHz or 2.4 MHz). However, for example, it is possible to modify the frequency of the clock (operation clock) supplied to the error correction circuit 33 to be twice the frequency of the clock (sampling) supplied to the A / D conversion circuit 31.

  FIG. 8 is a flowchart for explaining an example of the processing of the digital broadcast demodulation method according to the present invention, and is for explaining the selection processing of the internal clock used in the OFDM demodulator 30. For example, in an initial state such as when the power is turned on, the frequency divider 35 outputs a 2.08695 MHz internal clock with low frequency and low power consumption.

  First, at the start of reception, in step ST1, a reception channel is set and the process proceeds to step ST2. In step ST2, it is determined whether or not spurious is generated in the RF unit 2 due to harmonics of the internal clock.

  If it is determined in step ST2 that spurious is generated in the RF unit 2 due to the harmonics of the internal clock, the process proceeds to step ST3, and the frequency division ratio is set so that the internal clock of 2.4 MHz is output from the frequency divider 35. 92 (divided by 92).

  On the other hand, if it is determined in step ST2 that no spurious is generated in the RF unit 2 due to the harmonics of the internal clock, the process proceeds to step ST4 and the frequency divider 35 outputs an internal clock of 2.08695 MHz. Set the ratio to 80 (divide by 80). Then, the above processing is repeatedly executed.

  As a result, when the first internal clock having a low frequency (2.08695 MHz clock) does not generate spurious signals with the reception channel, the first internal clock is used, and the first internal clock generates spurious signals with the receiving channel. In this case, a second internal clock (2.4 MHz clock) that has a high frequency and does not generate spurious signals with all reception channels is used. As a result, it is possible to suppress deterioration of reception characteristics due to spurious and to suppress an increase in power consumption.

  As described above, according to the digital broadcast demodulation method of the present invention, first, in the case of a channel that is affected by spurious mixing in the RF stage by the operation at the initial value of 2.08695 MHz of the clock frequency (internal clock frequency). (When the reception channel generates a 2.08695 MHz clock (first internal clock) and spurious), the clock frequency is changed to 2.4 MHz (second internal clock); otherwise (the reception channel is first If the internal clock and spurious are not generated), the clock frequency is not changed.

  A combination of whether or not spurious is generated by the first and second internal clocks for each channel is stored in the memory 36 in advance, and information on whether or not the spurious is generated is stored in the frequency divider 37. As described above, the clock frequency can be changed by selecting the frequency division ratio.

  Note that the frequencies of the first and second internal clocks are not limited to the above-described 2.08695 MHz and 2.4 MHz, and accordingly, the frequency band and circuit of digital broadcasting to which the frequency dividing ratio is applied. Needless to say, various changes are made according to the design.

  FIG. 9 is a diagram for explaining an example of an information display program to which the present invention is applied and a medium on which the information display program is recorded. In FIG. 9, reference numeral 410 denotes a processing device, 420 denotes a program (data) provider, and 430 denotes a portable recording medium. In FIG. 9, a mobile phone is shown as the processing device (computer). However, as described above, the application of the present invention is not limited to the mobile phone.

  For example, the present invention is given as a program (data) for the processing device 410 as shown in FIG. The processing device 410 includes an arithmetic processing device main body 411 including a processor, and a processing device side memory (for example, a RAM (Random Access Memory) that stores a result of giving or processing a program (data) to the arithmetic processing device main body 411. )) 412 and the like. The program provided to the processing device 410 is loaded and executed on the main memory of the processing device 410.

  The program provider 420 has means (line-destination memory: for example, DASD (Direct Access Storage Device)) 421 for storing the program, and provides the program to the processing device 410 via a line such as the Internet, or The data is provided to the processing device 410 via various portable recording media 430 such as an optical disk or a magnetic disk via a memory card such as a Mini-SD or a Micro-SD, various interfaces, or a computer. Needless to say, the medium on which the information display program according to the present invention is recorded includes the processing device side memory 412, the line destination memory 421, the portable recording medium 430, and the like.

(Appendix 1)
A digital broadcast demodulator that receives a signal from a tuner and demodulates the signal from the tuner using an internal clock synchronized with a reference signal,
Internal clock generating means for generating the internal clock;
An internal clock frequency control means for controlling the frequency of the internal clock to switch to a frequency that does not generate spurious and the reception channel according to the reception channel.

(Appendix 2)
In the digital broadcast demodulating device according to attachment 1, the internal clock frequency control means includes:
Storage means for storing a channel that generates spurious by a first internal clock having a first frequency, and a combination of the channel and a second internal clock having a second frequency that does not generate spurious;
When the first internal clock does not generate spurious with the reception channel according to the output of the storage means, the first internal clock is generated from the internal clock generation means, and the first internal clock is A digital broadcast demodulating device, comprising: clock switching control means for generating the second internal clock from the internal clock generating means when generating spurious with the reception channel.

(Appendix 3)
In the digital broadcast demodulating device according to attachment 2, when the first frequency is lower than the second frequency and the first internal clock does not generate spurious with the reception channel, the first frequency with the lower frequency is added. A digital broadcast demodulator using an internal clock.

(Appendix 4)
The digital broadcast demodulator according to appendix 2 or 3, wherein the second frequency is a frequency that does not generate spurious signals with two or more channels.

(Appendix 5)
In the digital broadcast demodulator according to any one of appendices 2 to 4,
The digital broadcast demodulating device includes an A / D conversion circuit that receives an IF signal from the tuner and performs analog / digital conversion, a demodulation processing circuit that demodulates an output of the A / D conversion circuit, and an output of the demodulation processing circuit An OFDM demodulator of a one-segment broadcasting reception module having an error correction circuit that performs error correction of a signal and outputs a digital signal,
The internal clock generating means
A PLL circuit that receives a reference clock and outputs a synchronization signal;
A frequency dividing circuit that divides the synchronization signal from the PLL circuit and supplies the first internal clock or the second internal clock to the A / D conversion circuit, the demodulation processing circuit, and the error correction circuit; Prepared,
The internal clock frequency control means selects and generates the first internal clock or the second internal clock by controlling a frequency division ratio of the frequency dividing circuit according to an output of the storage means. Digital broadcast demodulator.

(Appendix 6)
A digital broadcast demodulation method for receiving a signal from a tuner and demodulating the signal from the tuner using an internal clock synchronized with a reference signal,
Receiving information of a receiving channel;
And a step of selecting and generating the reception channel and an internal clock having a frequency that does not generate spurious out of at least two internal clocks having different frequencies.

(Appendix 7)
In the digital broadcast demodulation method according to attachment 6,
Selecting and generating the internal clock comprises:
If the first internal clock of the first frequency does not generate spurious with the receiving channel, select and generate the first internal clock; and
When the first internal clock generates spurious with the reception channel, it does not generate spurious with two or more channels, and switches to a second internal clock having a second frequency higher than the first frequency. A method for demodulating a digital broadcast.

  The present invention relates to a one-seg broadcast receiving module for terrestrial digital broadcasting (one-seg broadcasting) for mobile terminals such as mobile phones, and more particularly, a digital broadcast demodulating device (OFDM demodulating unit) for a one-seg broadcasting receiving module. In addition, it can be widely applied as a demodulator of a one-seg broadcast receiving module other than a mobile terminal, and further a receiving module other than one-seg broadcasting.

It is a block diagram which shows roughly an example of the whole structure of the digital broadcast receiver with which a digital broadcast demodulation apparatus is applied. It is a block diagram which shows an example of the conventional digital broadcast demodulation apparatus. 1 is a block diagram showing an embodiment of a digital broadcast demodulator according to the present invention. It is a figure which shows notionally the relationship between the frequency band of the terrestrial digital broadcasting (one-segment broadcasting) for mobile terminals as an example of digital broadcasting, and the clock used in one Example of the digital broadcasting demodulation apparatus of this invention. It is FIG. (1) which shows concretely the relationship between the frequency band used by one-segment broadcasting, and the clock used in one Example of the digital broadcast demodulation apparatus of this invention. It is FIG. (2) which shows concretely the relationship between the frequency band used by one-segment broadcasting, and the clock used in one Example of the digital broadcast demodulation apparatus of this invention. It is a figure for demonstrating operation | movement of the frequency divider circuit in one Example of the digital broadcast demodulator based on this invention. It is a flowchart for demonstrating an example of the process of the digital broadcast demodulation method which concerns on this invention. It is a figure for demonstrating the example of the medium which recorded the digital broadcast demodulation program and digital broadcast demodulation program to which this invention is applied.

Explanation of symbols

1 Antenna 2 Tuner (RF section)
3,300 Digital broadcast demodulator (OFDM demodulator)
4 Digital broadcast receiving module (one-segment broadcasting receiving module)
5 Image / sound processor 6 CPU
7 Display 8 Speaker 31, 301 A / D conversion circuit 32, 302 Demodulation processing circuit 33, 303 Error correction circuit 34, 304 PLL circuit 35, 305 Frequency division circuit 36 Memory 37 Frequency division ratio selection circuit 410 Processing unit 411 Arithmetic processing unit Main body 412 Processing device side memory 420 Program (data) provider 421 Means for storing program (line destination memory)
430 Portable recording medium

Claims (5)

A digital broadcast demodulator that receives a signal from a tuner and demodulates the signal from the tuner using an internal clock synchronized with a reference signal,
Internal clock generating means for generating the internal clock;
An internal clock frequency control means for controlling the frequency of the internal clock to switch to a frequency that does not generate spurious and the reception channel according to the reception channel. 2. The digital broadcast demodulating apparatus according to claim 1, wherein the internal clock frequency control means is
Storage means for storing a channel that generates spurious by a first internal clock having a first frequency, and a combination of the channel and a second internal clock having a second frequency that does not generate spurious;
When the first internal clock does not generate spurious with the reception channel according to the output of the storage means, the first internal clock is generated from the internal clock generation means, and the first internal clock is A digital broadcast demodulating device, comprising: clock switching control means for generating the second internal clock from the internal clock generating means when generating spurious with the reception channel.   3. The digital broadcast demodulating device according to claim 2, wherein the first frequency is lower than the second frequency, and the first internal clock does not generate spurious noise with the reception channel, the low frequency of the first frequency. 1. A digital broadcast demodulator using an internal clock. A digital broadcast demodulation method for receiving a signal from a tuner and demodulating the signal from the tuner using an internal clock synchronized with a reference signal,
Receiving information of a receiving channel;
And a step of selecting and generating the reception channel and an internal clock having a frequency that does not generate spurious out of at least two internal clocks having different frequencies. The digital broadcast demodulation method according to claim 4, wherein
Selecting and generating the internal clock comprises:
If the first internal clock of the first frequency does not generate spurious with the receiving channel, select and generate the first internal clock; and
When the first internal clock generates spurious signals with the reception channel, it does not generate spurious signals with all the channels, but generates it by switching to a second internal clock having a second frequency higher than the first frequency. A method for demodulating digital broadcasting.

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