JP2002171181A - Tuning device and radio receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely prevent any reception failure due to the interference of a noise such as higher harmonics or spurious to be generated from a clock oscillation circuit. SOLUTION: This device is provided with first and second clock oscillation circuits 324 and 325 whose oscillation frequencies are different to be selectively used and a storage part 326 for storing the frequencies of a noise to be generated from the first clock oscillation circuit 324. At the time of switching to preliminarily set reception frequencies, when the switching reception frequencies are made matched with the frequencies of a noise stored in a storage part 326, and the first clock oscillation circuit 324 in which the frequencies of the noise are matched with the switching reception frequencies is used, the first clock oscillation circuit is switched to the second oscillation circuit in which the frequencies of the noise are not matched with the switching reception frequencies.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel selecting device and a radio receiver constituting a super heterodyne type radio receiver.

[0002]

2. Description of the Related Art In recent years, a radio receiver employing a superheterodyne system which is configured to automatically tune by a microcomputer has been frequently used. In such a radio receiver, the S / N ratio deteriorates due to interference due to noise such as harmonics and spurious signals generated from a clock oscillation circuit that operates a microcomputer. As a result, the tuning circuit is locked, and a loud noise is output from the speaker, and normal reception is hindered.

For this reason, in the conventional radio receiver, the oscillation element such as a crystal oscillator is set so that the frequency of noise such as harmonics and spurious generated from the clock oscillation circuit is as far as possible from the frequency of the broadcast radio wave. By changing the fundamental frequency to an appropriate one, moving the noise source away from the high-frequency circuit, or shielding the noise source, normal reception is not hindered. In some cases, normal reception is not hindered by shifting the oscillation frequency of the clock oscillation circuit by, for example, changing the constant of a circuit element.

[0004]

However, the means for changing the fundamental frequency of the oscillating element to an appropriate one is not suitable for a case where a large number of broadcast waves exist over a wide frequency range even if a certain broadcast wave can be handled. Had a problem that it could not cope sufficiently. In addition, measures to keep the noise source away from the high-frequency circuit section or shield the noise source will inevitably increase the size of the radio receiver, so it is sufficient to cope with situations where miniaturization is required. There was a problem that became impossible. Further, the means for shifting the oscillation frequency of the clock oscillation circuit has a problem that the shift amount is so small that it is impossible to sufficiently cope with it.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a channel selecting apparatus and a channel selecting apparatus capable of reliably preventing a reception failure due to interference of noise such as harmonics and spurious signals generated from a clock oscillation circuit. It is intended to provide a radio receiver.

[0006]

In order to achieve the above object, an invention according to claim 1 is to transmit a tuning signal to a PLL circuit for changing the setting of the oscillation frequency of a local oscillation circuit and to set a preset reception frequency. A tuning apparatus for configuring a superheterodyne radio receiver having control means for switching to a plurality of clock oscillation circuits selectively using different oscillation frequencies; Storage means for storing the frequency of the noise generated from the clock oscillation circuit, when switching to a preset reception frequency, the switching reception frequency matches the frequency of the noise stored in the storage means, and In the case where the coincident clock oscillation circuit is used, another clock source whose noise frequency does not coincide with the switching reception frequency is used. It is characterized in that for switching the circuit.

According to this configuration, when switching to a preset receiving frequency, if the switching receiving frequency matches the frequency of noise such as harmonics and spurious generated from the clock oscillation circuit, the matching clock is used. When the oscillation circuit is used, the clock frequency is switched to another clock oscillation circuit whose noise frequency does not match the switching frequency. For this reason, a channel selection device that can surely prevent a reception failure due to interference of noise generated from the clock oscillation circuit is realized, thereby making it possible to configure a highly reliable radio receiver.

[0008] The reception frequency refers to a frequency set for each predetermined step frequency unit in which a broadcast wave may exist. That is, the broadcast wave
It exists only on the frequency set for each step frequency unit. In addition, the case where the preset reception frequency matches the frequency of the noise means not only the case where the reception frequency and the frequency of the noise exactly match, but also the case where the center frequencies are slightly different from each other. This includes all cases where reception interference is caused by noise interference when a broadcast wave exists at the reception frequency.

The invention according to claim 2 is the invention according to claim 1, wherein the control means switches to another clock oscillation circuit before switching to a preset reception frequency. Features.

According to this configuration, the switching to another clock oscillation circuit which is not subject to noise interference is performed before the reception frequency is switched. Therefore, when a broadcast wave exists at the reception frequency scheduled to be switched. Even in this case, the reception frequency can be quickly switched to the reception frequency in a state where no reception failure occurs. For this reason, a channel selection device that can surely prevent a reception failure due to interference of noise generated from the clock oscillation circuit is realized, thereby making it possible to configure a highly reliable radio receiver.

[0011] The invention of claim 3 is the invention according to claim 1 or 2.
Wherein each of the clock oscillation circuits includes an oscillation element and an electronic switch element connected in series to the oscillation element, and the control means switches the clock generation circuit by controlling on / off of each electronic switch element. It is characterized by having been done.

According to this configuration, the clock oscillation circuit in which the electronic switch element is turned on is driven, whereby the frequency of the received broadcast wave matches the frequency of noise such as harmonics and spurious generated from the clock oscillation circuit. That is, the clock oscillation circuit is switched to the non-oscillation circuit. For this reason, a channel selection device that can surely prevent a reception failure due to noise interference can be easily realized, thereby making it possible to configure a highly reliable radio receiver.

According to a fourth aspect of the present invention, there is provided a superheterodyne system comprising a control means for transmitting a tuning signal to a PLL circuit for setting and changing an oscillation frequency of a local oscillation circuit and switching to a preset reception frequency. A radio receiver, wherein the control means includes: a plurality of clock oscillation circuits having different oscillation frequencies selectively used; and storage means for storing a frequency of noise generated from at least one clock oscillation circuit. When switching to the set reception frequency, the reception frequency to be switched matches the frequency of the noise stored in the storage means, and when the clock oscillation circuit that matches the frequency is used, the frequency of the noise is switched to the reception frequency. It is characterized by switching to another clock oscillation circuit that does not match the frequency.

According to this configuration, when switching to the preset receiving frequency, if the switching receiving frequency matches the frequency of noise such as harmonics and spurious generated from the clock oscillation circuit, the matching clock is used. When the oscillation circuit is used, the clock frequency is switched to another clock oscillation circuit whose noise frequency does not match the switching frequency. Therefore, a radio receiver that can reliably prevent a reception failure due to interference of noise generated from the clock oscillation circuit is realized.

[0015] The reception frequency refers to a frequency which is set for each predetermined step frequency unit and in which a broadcast radio wave may exist. That is, the broadcast wave
It exists only on the frequency set for each step frequency unit. In addition, the case where the preset reception frequency matches the frequency of the noise means not only the case where the reception frequency and the frequency of the noise exactly match, but also the case where the center frequencies are slightly different from each other. This includes all cases where reception interference is caused by noise interference when a broadcast wave exists at the reception frequency.

According to a fifth aspect of the present invention, in the fourth aspect, the control means switches to another clock oscillation circuit before switching to a preset reception frequency. Features.

According to this configuration, the switching to another clock oscillation circuit is performed before the switching of the receiving frequency is performed. Is immediately switched to the reception frequency in a state where no error occurs.
Therefore, a radio receiver that can reliably prevent a reception failure due to interference of noise generated from the clock oscillation circuit is realized.

The invention of claim 6 is the invention of claim 4 or 5
Wherein each of the clock oscillation circuits includes an oscillation element and an electronic switch element connected in series to the oscillation element, and the control means switches the clock generation circuit by controlling on / off of each electronic switch element. It is characterized by having been done.

According to this configuration, the clock oscillation circuit in which the electronic switch element is turned on is driven, and the frequency of the received broadcast wave matches the frequency of noise such as harmonics and spurious generated from the clock oscillation circuit. That is, the clock oscillation circuit is switched to the non-oscillation circuit. For this reason, a radio receiver that can reliably prevent a reception failure due to noise interference is easily realized.

[0020]

FIG. 1 is a block diagram showing a basic configuration of a radio receiver to which a tuning apparatus according to an embodiment of the present invention is applied. In this figure, the radio receiver 10
Is for consumer use, and includes an antenna 12 for receiving broadcast radio waves, a high-frequency amplifier circuit 14 for amplifying a reception signal input from the antenna 12, a local oscillation circuit 16 for generating a local oscillation signal, and a local oscillation circuit. PLL (Phase-Locked L) for changing the setting of the frequency of the local oscillation signal generated in step 16
oop) circuit 18 and a mixing circuit 20 for converting the received signal into a predetermined intermediate frequency by using the received signal amplified by the high-frequency amplifier circuit 14 and the local oscillation signal generated by the local oscillation circuit 16.
And Note that the local oscillation circuit 16 and the mixing circuit 20 constitute a frequency conversion circuit.

The radio receiver 10 includes a mixing circuit 20.
Frequency amplification circuit 2 for amplifying the intermediate frequency signal obtained in
2, a demodulation circuit 24 for demodulating the amplified intermediate frequency signal
A mute circuit 26 for muting audio, a low-frequency amplifier 28 for amplifying the demodulated low-frequency signal,
The system includes a speaker 30 that is an audio output unit that outputs the amplified low-frequency signal as audio, and a control unit (system controller) 32 that transmits a tuning signal to the PLL circuit 18. In this embodiment, the radio receiver 10 is configured to be able to receive a broadband broadcast wave such as FM broadcast (FM), short wave broadcast (SW), medium wave broadcast (MW), and long wave broadcast (LW). Things.

The PLL circuit 18 includes, for example, a programmable frequency divider, a phase comparator, and a VCO (Voltage Controller).
lled Oscillator), a known configuration including a low-pass filter, etc., and a voltage output when a tuning signal (frequency data) is supplied from the control unit 32 to the programmable frequency divider is supplied to the local oscillation circuit 16. This is applied to a variable capacitance diode provided, whereby the oscillation frequency of the local oscillation circuit 16 can be varied. Further, other circuits such as the high-frequency amplifier circuit 14 and the mixing circuit 20 also have a known configuration, and thus detailed description thereof will be omitted.

The control unit 32 is constituted by a microcomputer, and executes a predetermined arithmetic processing.
A PU (Central Processing Unit) 321 and a ROM (Read-Only) in which predetermined processing programs and data are recorded
Memory) 322 and a RAM (R) for temporarily recording data
andom Access Memory) 323, a first clock oscillation circuit 324 that generates a clock signal that determines the operation speed of the CPU 321, and a second clock oscillation circuit 325 that generates a clock signal with an oscillation frequency lower than that of the first clock oscillation circuit 324. It has.

The control unit 32 includes a storage unit 326 such as a ROM in which a plurality of noise frequencies such as harmonics and spurious generated from the first clock oscillation circuit 324 are stored. It should be noted that the CP constituting the control
The U321 is connected to an operation switch 34 for performing an operation for switching a broadcast wave (broadcasting station) to be received and a display unit 36 for displaying a reception frequency and the like.

The first clock oscillation circuit 324 has an oscillation frequency set to, for example, 7.200 MHz. The first clock oscillation circuit 324 is connected in series to the first oscillation element 324a composed of a crystal oscillator or the like and connected to the first oscillation element 324a. And a first switch section 324b made of an NPN transistor which is an electronic switch element that is turned on / off by a drive signal supplied from the first switch section 324b. The first switch section 324b is turned on when a predetermined base current is supplied through a base resistor 324c, and thereby the first oscillation element 324a is driven.

The second clock oscillation circuit 325 has an oscillation frequency set to, for example, 4.332 MHz, and is connected in series to a second oscillation element 325a made of a crystal oscillator or the like and to the second oscillation element 325a. , CPU 321
Composed of an NPN-type transistor which is an electronic switch element which is turned on / off by a drive signal supplied from the
And a switch unit 325b. The second switch section 325b is turned on when a predetermined base current is supplied via a base resistor 325c, whereby the second oscillation element 325a is driven.

When the first switch section 324b is on, the second switch section 325b is off, and when the second switch section 325b is on, the first switch section 325b is off. One of the clock oscillation circuits (the first clock oscillation circuit 324 or the second clock oscillation circuit 325) is selectively used. Also, first and second switch units 324b, 325b are provided at one end sides of the first and second oscillation elements 324a, 325a, respectively.
Stabilizing capacitor 327 common to ground through
Is connected to the other end of each of the first and second oscillation elements 324a and 325a.
28 are connected.

The recording of the frequency of noise such as harmonics and spurious generated from the first clock oscillation circuit 324 in the storage unit 326 has been performed through the following confirmation work. That is, in the design stage of the radio receiver 10,
In an environment where no external radio waves exist, such as in a shielded room, the first clock oscillation circuit 324 set to a predetermined oscillation frequency is driven, and noise such as harmonics and spurious noise is generated by the high frequency amplification circuit 14 and the local oscillation circuit. A situation in which the noise is mixed into a high-frequency circuit such as 16 is observed by a spectrum analyzer, and the frequency of each noise is recorded.

Next, the second clock oscillating circuit 3 set to an oscillation frequency lower than that of the first clock oscillating circuit 324
25 is driven to observe the situation in which noise such as harmonics and spurious is mixed in high-frequency circuits such as the high-frequency amplifier circuit 14 and the local oscillation circuit 16 by using a spectrum analyzer, and the frequency of each noise is recorded.

Such observation is performed for each band (FM, S
W, MW, LW, etc.) and the first and second clock oscillation circuits 3
24, 325 are sequentially replaced by ones having different oscillating frequencies, and the operation is repeatedly performed. The second clock oscillating circuit is used for a broadcast wave (broadcasting station) that is interfered by noise such as harmonics and spurious generated from the first clock oscillating circuit 324. 325, until it is not interfered by noise such as harmonics and spurious noise.
The respective oscillation frequencies of the second clock oscillation circuits 324 and 325 are determined.

The first and the first cut and try methods are used.
After the oscillation frequencies of the second clock oscillation circuits 324 and 325 are determined, the frequency of noise such as harmonics and spurious by the first clock oscillation circuit 324 may cause interference with the broadcast wave for each reception band. A certain thing is stored in the storage unit 326. First clock oscillation circuit 32
The oscillation frequency of No. 4 is set to 7.200 MHz as described above. For example, noise that may interfere with broadcast waves in the FM broadcast band in the United States is, for example, 10
Exists.

For the FM broadcast band in the United States, the frequencies of these ten noises are stored in the storage unit 32.
6 is stored. Similarly, for the other reception bands, the frequencies of the noise that may interfere with the broadcast wave are stored in the storage unit 326. The frequencies of these noises have a predetermined width with respect to the peak value, and a frequency having a predetermined width that may interfere with broadcast radio waves is stored in the storage unit 326 (for example, the peak value is 99. 0
98.7-99.2M when MHz noise is present
Frequencies in the range of Hz are stored. ).

In this embodiment, the step frequency that defines the transmission frequency of the broadcast station is taken into account as described above,
Only noise of a frequency that matches or approximates a frequency at which a broadcast wave (broadcasting station) may exist (that is, noise that interferes with the broadcast wave) is stored. That is, since broadcast stations in various countries in the world always exist on the frequency related to the specified step frequency, the channel selection signal to be transmitted to the PLL circuit 18 is set in step frequency units (intervals). This makes it possible to disregard noises other than noises that may interfere with broadcast radio waves, such as harmonics and spurious noises generated from the first and second clock oscillation circuits 324 and 325, and store them. There is no need to store it in the unit 326.

For this reason, the storage section 326 may have a small storage capacity, which can contribute to cost reduction. The ROM 322 can also be used as the storage unit 326. Of course, it is needless to say that all the noises can be stored in the storage unit 326 regardless of the step frequency.

The CPU 321 includes a reception function control section 321a, a first determination section 321b, a second determination section 321c,
It has a function realizing unit as a third determining unit 321d, a fourth determining unit 321e, and a switching control unit 321f. The reception function control unit 321a controls various functions as a radio receiver, such as an automatic tuning function and a mute function, which are executed by operating the operation switch 34. For example, regarding the automatic tuning function,
After setting a predetermined reception band by a setting switch (not shown), selecting an automatic seek channel and turning on the operation switch 34, a channel selection signal set in units of step frequencies is sent to the PLL circuit 18 at a predetermined timing. Are supplied sequentially. As a result, the voltage supplied from the PLL circuit 18 to the local oscillation circuit 16 is varied, so that the oscillation frequency of the local oscillation circuit 16 is sequentially changed from a low value to a high value (or from a high value to a low value). The reception frequency is sequentially switched to the reception frequency set in frequency units.

When switching to the reception frequency set in the unit of step frequency, the first determination unit 321 b determines the frequency of the noise of the first clock oscillation circuit 324 in which the reception frequency to be switched is stored in the storage unit 326. This is to determine whether they match. The coincidence determination between the reception frequency and the noise frequency refers to determining whether the reception frequency is within a frequency range having a predetermined width of the noise. That is, this frequency range is a noise interference area where the reception frequency may be interfered by noise.

The second determining section 321c determines whether the PLL circuit 18 is locked. This determination is based on the fact that the state of the lock bit is "high" (or, after the tuning signal is transmitted from the control unit 32 to the PLL circuit 18).
This is executed by detecting whether or not “low” has been reached.

The third determining section 321d determines whether or not a broadcast wave (broadcasting station) exists at the switched receiving frequency. This determination is made based on the intermediate frequency signal generated by the frequency of the broadcast radio wave and the oscillation frequency of the local oscillation circuit 16 (for example, 10.7 MHz in the case of FM broadcasting).
Is executed by detecting whether or not there is a. That is, when a broadcast wave is present at the reception frequency to be switched, a predetermined intermediate frequency signal is present. When no broadcast wave is present at the reception frequency to be switched, no intermediate frequency signal is present. The determination can be made based on the presence or absence of the signal.

The fourth determination unit 321e determines whether the operation switch 34 has been newly operated and the next channel selection instruction has been performed in the state of receiving broadcast radio waves. This determination is performed by detecting an operation signal transmitted from the operation switch 34 while receiving a broadcast wave.

The switching control unit 321f is used when the reception frequency to be switched matches the noise frequency of the first clock oscillation circuit 324 stored in the storage unit 326, for example.
This is switched to the second clock oscillation circuit 325.
That is, when the reception frequency to be switched matches the frequency of the noise generated from the first clock oscillation circuit 324, the supply of the drive signal to the first switch unit 324b is stopped, while the drive to the second switch unit 325b is stopped. The signal is supplied to drive the second clock oscillation circuit 325.

Thus, even when a broadcast wave is present at the reception frequency to be switched, it is possible to prevent the clock oscillation circuit from receiving interference due to noise.
If the reception frequency to be switched does not match the frequency of the noise generated from the first clock oscillation circuit 324, the supply of the drive signal to the first switch unit 324b is in a continued state.

After switching from the first clock oscillation circuit 324 to the second clock oscillation circuit 325, the switching control section 321f switches the broadcast radio wave to the second clock oscillation circuit 32
When there is a risk of interference by the noise of No. 5, the second clock oscillation circuit 325 is switched to the first clock oscillation circuit 324. In the initial stage of the operation of the radio receiver 10, the first clock oscillation circuit 324 is set to operate.

FIGS. 2 and 3 are flowcharts schematically showing an example of the tuning operation of the control unit 32. Here, the operation in the case where the auto seek tuning is selected in the FM broadcast band in the United States will be described as an example. The control unit 32 is programmed to operate by the first clock oscillation circuit 324 immediately after the power of the radio receiver 10 is turned on. The US FM broadcasting band is 8
The frequency range is set to 7.5 to 107.9 MHz, and broadcast stations can exist at intervals of, for example, 100 KHz (in the case of a step frequency of 100 KHz).

When the operation switch 34 is operated while the power of the radio receiver 10 is turned on, the first clock oscillation circuit 32 stored in the storage unit 326 is operated.
4 is searched, and the next receiving frequency to be switched (for example, 87.5 MHz to 87.6 MHz) is searched.
(switching to z) is within the noise interference area of the first clock oscillation circuit 324 by the first determination unit 321b (step S1).

If the determination in step S1 is denied, a tuning signal for switching to the next receiving frequency (for example, a tuning signal for switching from 87.5 MHz to 87.6 MHz) is received by the receiving function control section 321a. PLL
Sent to the circuit 18 (step S3), and subsequently
Whether the L circuit 18 is locked or not is determined by the second determination unit 321c.
(Step S5). This step S5
If the determination in step (3) is affirmative, the third determination unit 321d determines whether or not a broadcast wave exists at the switched reception frequency (step S7). Step S5
If the determination in step 1 is denied, the process waits until the determination is affirmed.

If the determination in step S7 is affirmative, the broadcast wave at the switched reception frequency is received,
A good reception state in which no reception failure occurs is maintained. During the period in which the tuning operation is continued until the PLL circuit 18 is locked, the reception function control unit 321a
The mute circuit 26 is actuated to mute the audio output, and unnecessary noise and the like are generated by the speaker 3.
0 is not output.

Next, in the state where the broadcast radio wave is being received, the fourth discriminator 32 determines whether or not the operation switch 34 has been operated (ie, whether or not the next tuning operation has been performed).
1e (step S9), and if the determination is negative, the reception state of the broadcast radio wave is continued. Further, when the determination in step S7 is negative,
If the determination at 9 is affirmative, the process moves to step S1 and the subsequent steps are repeatedly executed.

When the process proceeds from step S7 or step S9 to step S1, the next switching reception frequency (for example, switching from 87.6 MHz to 87.7 MHz) in the unit of a preset step frequency is set. The first determination unit 321b determines whether or not the noise is within the noise interference region of the first clock oscillation circuit 324.

On the other hand, if the determination in step S1 is affirmative, the reception frequency to be switched (for example, 87.5 MHz)
(switching from z to 87.6 MHz), there is a possibility that a reception failure may occur when a broadcast radio wave is present. Therefore, regardless of whether or not a broadcast radio wave actually exists, the switching control unit 321f controls the first clock. From the oscillation circuit 324 to the second
Switching to the clock oscillation circuit 325 is performed (step S11). The time required for this switching is, for example, 6 m
This is a short time of about s, and does not affect the operation of the CPU 321.

At substantially the same time as this switching, a tuning signal for switching to the next reception frequency (for example, switching from 87.5 MHz to 87.6 MHz) in the operating state of the second clock oscillation circuit 325 at the clock frequency. Tuning signal) is received by the reception function control unit 321a.
It is transmitted to the circuit 18 (step S13), and subsequently P
The second determination unit 321 determines whether the LL circuit 18 is locked.
It is determined by c (step S15).

If the determination in step S15 is affirmative, the third determination unit 321d determines whether or not a broadcast wave exists at the switched reception frequency (step S17). If the determination in step S15 is negative, the process waits until the determination is positive. And
If the determination in step S17 is affirmative, the broadcast wave at the switched reception frequency is received, and a good reception state in which no reception failure occurs is maintained. As described above, while the tuning operation is continued until the PLL circuit 18 is locked, the reception function control unit 32
The mute circuit 26 is activated by 1a to mute the audio output, so that unnecessary noise and the like are not output from the speaker 30.

Next, in the state where the broadcast radio wave is being received, the fourth discriminating unit 32 determines whether or not the operation switch 34 has been operated (ie, whether or not the next tuning operation has been performed).
1e (step S19), and if this determination is denied, the broadcast radio wave reception state is continued. When the determination in step S17 is denied, and when the determination in step S19 is affirmed, the noise generated from the first clock oscillation circuit 324 stored in the storage unit 326 is searched. The first determination unit 321b determines whether the reception frequency to be switched to is within the noise interference region of the first clock oscillation circuit 324 (step S21).

That is, step S17 or step S17
When the process proceeds from step S19 to step S21, the next switching reception frequency (for example, switching from 87.6 MHz to 87.7 MHz) in the unit of the preset step frequency is changed to the noise of the first clock oscillation circuit 324. The first determination unit 321b determines whether or not it is within the interference area.

If the determination in step S21 is denied, the reception frequency to be switched (for example, 87.6)
(Switching from 8 MHz to 87.7 MHz), a reception failure may occur when a broadcast radio wave is present. Therefore, regardless of whether or not a broadcast radio wave actually exists, the switching control unit 321f operates the second clock. Switching from the oscillating circuit 325 to the first clock oscillating circuit 324 is performed (Step S23), and thereafter, the process proceeds to Step S3 and the subsequent steps are repeatedly executed.

That is, when the determination in step S21 is negative, at least the first clock oscillation circuit 324
Since there is no possibility of receiving noise interference caused by the
From the clock oscillation circuit 325 to the first clock oscillation circuit 32
4 is performed. Of course, depending on the reception frequency, there is a possibility that there is no possibility of receiving the interference of the noise generated by the second clock oscillation circuit 325, but in the present embodiment, the noise generated by the second clock oscillation circuit 325 is stored in the storage unit 326. Therefore, the switching to the first clock oscillation circuit 324 without causing a reception trouble is performed. The time required for the switching in step S23 is, for example, 6 ms.
This is a short time, and does not affect the operation of the CPU 321.

Further, when the process proceeds from step S23 to step S3, in the operation state of the first clock oscillation circuit 324 at the clock frequency, a tuning signal for switching to the next reception frequency is received by the reception function control unit 321a by the PLL.
It will be transmitted to the circuit 18. Step S2
If the determination at 1 is affirmative, the second clock oscillation circuit 32
Since there is no possibility of receiving the interference of noise caused by the step 5, the process directly proceeds to step S13, and the subsequent steps are repeatedly executed.

The present invention is configured as in the above embodiment. When switching to a preset receiving frequency, the receiving frequency to be switched is one of the noise frequency stored in the storage unit 326. In addition, when using the same clock oscillation circuit, the noise frequency is switched to another clock oscillation circuit that does not match the reception frequency to be switched, so that the configuration is simple. First, the reception failure due to noise such as harmonics and spurious generated from the first and second clock oscillation circuits 324 and 325 is surely prevented.

Further, in the above embodiment, before the tuning signal for switching to the next reception frequency is transmitted to the PLL circuit 18, the reception frequency to be switched is determined by the interference of noise from the clock oscillation circuit in use. It is determined whether or not to receive the noise, and if there is a risk of receiving the noise interference, the clock can be switched to another clock oscillation circuit that does not receive the noise interference. As a result, broadcast waves can be reliably received without receiving interference from noise.

It should be noted that the present invention is not limited to the above-described embodiment, but may adopt various modifications as described below.

(1) In the above embodiment, the case where the channel selection operation is an automatic seek channel selection is described. However, a similar channel selection operation can be performed in the case of a preset channel selection or a manual channel selection. For example, in the case of preset tuning,
When the operation switch 34 is operated, a first determination is made as to whether or not the reception frequency to be switched matches the frequency of the noise stored in the storage unit 326 before switching to the preset reception frequency to be selected. The switching control unit 321f may switch to another clock oscillation circuit that does not receive noise interference if the determination is made by the unit 321b and the values match.

(2) In the above embodiment, the radio receiver 1
Although the overall configuration of the radio receiver 10 has been described, the present invention can be used as a channel selection device for configuring the radio receiver 10. In this case, the channel selection device includes at least the local oscillation circuit 1
6, the PLL circuit 18, the mixing circuit 20, and the control unit 32 may be included. Of course, the high-frequency amplifier circuit 1
4, one of the intermediate frequency amplification circuit 22, the demodulation circuit 24, etc.
Alternatively, a plurality of circuits can be included. In short, a superheterodyne radio receiver having a control unit for transmitting a tuning signal to a PLL circuit for changing the oscillation frequency of the local oscillation circuit may be configured.

(3) In the above embodiment, the first clock oscillation circuit 324 and the second clock oscillation circuit 325 are used as clock oscillation circuits for operating the CPU 321.
Although one clock oscillation circuit is provided, the present invention is not limited to this. For example, it is possible to provide three or more clock oscillation circuits. In this case, the switching control section 321f may be configured to switch to one of the three or more clock oscillation circuits that does not receive noise interference.

(4) In the above embodiment, only the noise generated from the first clock oscillation circuit 324 is stored in the storage section 326, but the storage section 326 stores the noise generated by the first clock oscillation circuit 324 and the second clock oscillation circuit 325. The noise generated from both may be stored in association with each clock oscillation circuit. In this case, for example, step S21 in the flowchart shown in FIG.
What is necessary is just to determine whether or not it is within the noise interference region of the clock oscillation circuit.

(5) In the above embodiment, before switching to the preset receiving frequency, the receiving frequency to be switched matches the frequency of the noise stored in the storage unit 326 and the corresponding clock oscillation When a circuit is used, the frequency of the noise is switched to another clock oscillation circuit that does not match the reception frequency to be switched, but the present invention is not limited to this. For example, after switching to a preset reception frequency, if the switched reception frequency matches the frequency of the noise stored in the storage unit 326 and the coincident clock oscillation circuit is used, the frequency of the noise It is also possible to switch to another clock oscillation circuit that does not match the switched reception frequency. In this case, the mute circuit 26 may be operated until the switching to another clock oscillation circuit is completed.

[0065]

As described above, according to the channel selecting apparatus of the first to third aspects, the control means comprises a plurality of clock oscillating circuits selectively used having different oscillation frequencies, and at least one clock oscillating circuit. Storage means for storing the frequency of noise generated from the memory, and when switching to a preset reception frequency, the reception frequency to be switched matches the frequency of the noise stored in the storage means, and the matching clock When using an oscillation circuit, the clock frequency is switched to another clock oscillation circuit that does not match the reception frequency at which the noise frequency is switched. Therefore, reception interference due to interference of noise such as harmonics and spurious noise generated from the clock oscillation circuit is reduced. A channel selection device that can surely be blocked is realized.

Further, according to the radio receiver of the present invention, the control means comprises a plurality of clock oscillation circuits selectively used having different oscillation frequencies, and a frequency of noise generated from at least one clock oscillation circuit. And a storage means for storing the same. When switching to a preset reception frequency, the reception frequency to be switched matches the frequency of the noise stored in the storage means, and the matching clock oscillation circuit is used. In such a case, the clock frequency is switched to another clock oscillation circuit that does not match the reception frequency at which the noise is switched, so that it is possible to reliably prevent reception interference due to interference of noise such as harmonics and spurs generated from the clock oscillation circuit. A possible radio receiver is realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a basic configuration of a radio receiver to which a channel selection device according to an embodiment of the present invention is applied.

FIG. 2 is a flowchart for explaining a tuning operation of a control unit in the embodiment of the radio receiver shown in FIG. 1;

FIG. 3 is a flowchart for explaining a tuning operation of a control unit in the embodiment of the radio receiver shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Radio receiver 14 High frequency amplifier circuit 16 Local oscillation circuit 18 PLL circuit 20 Mixing circuit 22 Intermediate frequency amplifier circuit 24 Demodulation circuit 26 Mute circuit 28 Low frequency amplifier circuit 30 Speaker 32 Control means 324 First clock oscillation circuit 325 Second clock oscillation Circuit 326 Storage unit (storage unit) 321a Reception function control unit (reception function control unit) 321b First determination unit (first determination unit) 321c Second determination unit (second determination unit) 321d Third determination unit (third determination) Means) 321e Fourth discriminator (fourth discriminator) 321f Switching controller (switcher controller) 324a First oscillator (oscillator) 325a Second oscillator (oscillator) 324b First switch (electronic switch) 325b 2nd switch part (electronic switch element)

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Cheng Jun Chang Hong Kong Coulomb Hung Hom First Hochen Street Herba Center North Wig Tower 1 Room 1108 Shivatec Co., Ltd. F-term (reference) 5J103 CB02 CB04 DA05 DA41 DA44 FA03 JA04 5K020 DD05 GG01 KK08 NN10 5K052 AA02 BB04 DD16 FF26 GG24 GG57 5K061 AA10 BB01 CC16 CC45 JJ06 JJ07

Claims (6)

[Claims] 1. A superheterodyne radio receiver comprising control means for transmitting a tuning signal to a PLL circuit for setting and changing an oscillation frequency of a local oscillation circuit and switching to a preset reception frequency. Wherein the control means comprises: a plurality of clock oscillation circuits selectively using different oscillation frequencies;
Storage means for storing the frequency of noise generated from the clock oscillation circuit of, when switching to a preset reception frequency, the received frequency to be switched matches the frequency of the noise stored in the storage means, And a switching device that switches to another clock oscillation circuit whose noise frequency does not match the reception frequency to be switched when the matching clock oscillation circuit is used. 2. The channel selection apparatus according to claim 1, wherein said control means switches to another clock oscillation circuit before switching to a preset reception frequency. 3. Each of the clock oscillation circuits includes an oscillation element and an electronic switch element connected in series to the oscillation element, and the control means switches the clock generation circuit by controlling on / off of each electronic switch element. The tuning device according to claim 1 or 2, wherein the tuning is performed. 4. A superheterodyne radio receiver comprising a control means for transmitting a tuning signal to a PLL circuit for setting and changing an oscillation frequency of a local oscillation circuit and switching to a preset reception frequency, The control unit includes a plurality of clock oscillation circuits having different oscillation frequencies that are selectively used, and a storage unit that stores a frequency of noise generated from at least one clock oscillation circuit.
When switching to a preset reception frequency, the reception frequency to be switched matches the noise frequency stored in the storage means, and the noise frequency switches when the matching clock oscillation circuit is used. A radio receiver for switching to another clock oscillation circuit that does not match the reception frequency. 5. The radio receiver according to claim 4, wherein said control means switches to another clock oscillation circuit before switching to a preset reception frequency. 6. Each of the clock oscillation circuits includes an oscillation element and an electronic switch element connected in series to the oscillation element, and the control means switches the clock transmission circuit by controlling on / off of each electronic switch element. The radio receiver according to claim 4 or 5, wherein