JP2009009979A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2009009979A
JP2009009979A JP2007167264A JP2007167264A JP2009009979A JP 2009009979 A JP2009009979 A JP 2009009979A JP 2007167264 A JP2007167264 A JP 2007167264A JP 2007167264 A JP2007167264 A JP 2007167264A JP 2009009979 A JP2009009979 A JP 2009009979A
Authority
JP
Japan
Prior art keywords
unit circuit
circuit board
semiconductor device
sip
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007167264A
Other languages
Japanese (ja)
Inventor
Akio Segami
昭夫 瀬上
真 ▲鶴▼野
Makoto Tsuruno
Shinichiro Hattori
慎一郎 服部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Isahaya Electronics Corp
Original Assignee
Isahaya Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Isahaya Electronics Corp filed Critical Isahaya Electronics Corp
Priority to JP2007167264A priority Critical patent/JP2009009979A/en
Publication of JP2009009979A publication Critical patent/JP2009009979A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Combinations Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve quake resistance and size reduction of a circuit board, such as, a SIP (single in-line package) structure. <P>SOLUTION: A SIP-type unit circuit board (10) has a structure such that electrical connection made of one or more conductive substances (5) having circuit functions and that circuits (10) are fixed facing each other to improve quake resistance. In addition, a semiconductor device capable both of being downsized and improving heat dissipation is obtained, by using a substance with superior thermal conductivity and employing a connection method having unit boards so that they face each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、メインボード上に搭載する、縦型の半導体装置に関するものである。 The present invention relates to a vertical semiconductor device mounted on a main board.

図４は従来技術に係わるメインボード上（２０）に縦型のＳＩＰ（シングルインラインパッケージ）構造のサブ基板（２１）が搭載されている斜視図を示したものである。 FIG. 4 shows a perspective view in which a sub-substrate (21) having a vertical SIP (single in-line package) structure is mounted on a main board (20) according to the prior art.

半導体装置のメインボード（２０）上において、電子回路の実装面積の拡大を目的として、例えば電源回路部分を縦型のＳＩＰ構造のサブ基板（２１）に実装し、前記メインボード（２０）上に搭載している。 On the main board (20) of the semiconductor device, for the purpose of increasing the mounting area of the electronic circuit, for example, a power circuit portion is mounted on a sub-substrate (21) having a vertical SIP structure, and is mounted on the main board (20). It is installed.

ＳＩＰ構造のサブ基板（２１）は、縦型の構造であり、メインボード（２０）にサブ基板（２１）を固定するリード（３５）が一列のみ並んでいるため、耐震性が悪く、耐震性を向上させるために、リード（３５）や周辺の回路部品（４０）に絶縁性樹脂（３０）を塗布し、固定している。 The sub-board (21) having the SIP structure has a vertical structure, and only one row of leads (35) for fixing the sub-board (21) is arranged on the main board (20). In order to improve this, an insulating resin (30) is applied and fixed to the lead (35) and the peripheral circuit component (40).

また、ＳＩＰ構造のサブ基板（２１）に例えば発熱が大きいパワー素子（７）が実装されている場合は、放熱性を向上させるため、サブ基板（２１）の面積を大きくする必要があり、さらに耐震性が悪く、耐震性を向上させるために、リード（３５）や周辺の回路部品（４０）に絶縁性樹脂（３０）を塗布し、固定している。
特開平２００６−２４７４６号公報 For example, when the power element (7) generating a large amount of heat is mounted on the sub-board (21) having the SIP structure, it is necessary to increase the area of the sub-board (21) in order to improve heat dissipation. Insulation resin (30) is applied and fixed to the lead (35) and the peripheral circuit component (40) in order to improve the earthquake resistance due to poor earthquake resistance.
Japanese Patent Laid-Open No. 2006-24746

メインボード（２０）上に、ＳＩＰ構造のサブ基板（２１）を搭載した場合、前記ＳＩＰ構造のサブ基板（２１）は縦型の構造であり、１列のリードによる固定となり、振動に弱いという課題を有している。 When the SIP structure sub-board (21) is mounted on the main board (20), the SIP structure sub-board (21) has a vertical structure and is fixed by one row of leads, and is vulnerable to vibration. Has a problem.

また、耐震性を持たせるため、リード（３５）や周辺部品に絶縁性樹脂（３０）を塗布し、固定する必要があるため、前記固定用の絶縁性樹脂（３０）を塗布する工数が増えるという課題を有している。 In addition, in order to provide seismic resistance, it is necessary to apply and fix the insulating resin (30) to the lead (35) and the peripheral parts, so that the number of steps for applying the fixing insulating resin (30) increases. It has a problem.

請求項１において、２つの単位回路基板（１０）を１個または複数個の導電性物質（５）にて、回路の機能を有するように電気的接続を施し、前記単位回路基板（１０）を対向させるように固定することにより、基板を支えるリード（３５）が二列に増え、耐震性を向上させる作用を有する。 2. The unit circuit board (10) according to claim 1, wherein two unit circuit boards (10) are electrically connected to each other by one or a plurality of conductive substances (5) so as to have a circuit function. By fixing so as to face each other, the leads (35) for supporting the substrate are increased in two rows, and the effect of improving the earthquake resistance is obtained.

対向とは一方の単位回路基板に対し、接続される他の単位回路基板が平行もしくは角度を持った状態のことである。 The term “opposite” means that one unit circuit board is connected to another unit circuit board in parallel or at an angle.

請求項２において、請求項１記載の単位回路基板が複数個あり、１個または複数個の導電性物質（５）にて、回路の機能を有するように電気的接続を施し、互いに対向させるように固定することにより、基板を支えるリード（３５）が複数列となり、耐震性を向上させる作用を有する。 In claim 2, there are a plurality of unit circuit boards according to claim 1, and one or a plurality of conductive substances (5) are electrically connected so as to have a circuit function and are made to face each other. By fixing to the lead, the leads (35) supporting the substrate are arranged in a plurality of rows and have an effect of improving the earthquake resistance.

請求項３において、請求項１から２に記載の導電性物質（５）に熱伝導性に優れている物質を用いることで、発熱が大きいパワー素子などを搭載した単位回路基板（１１）の熱を、熱伝導性に優れている導電性物質（９）を介し、発熱が小さい制御素子などを搭載した単位回路基板（１２）へと放熱することで、単位回路基板の面積を小さくすることができ、耐震性を向上させる作用を有する。 The heat of the unit circuit board (11) mounted with a power element or the like that generates a large amount of heat by using a material having excellent thermal conductivity as the conductive material (5) according to claims 1 to 2. Can be radiated to the unit circuit board (12) equipped with a control element or the like that generates a small amount of heat through a conductive material (9) having excellent thermal conductivity, thereby reducing the area of the unit circuit board. And has the effect of improving earthquake resistance.

本発明により、縦型のＳＩＰ構造において、基板を支えるリード（３５）を複数列にすることで、絶縁樹脂を塗布する工数を減らすことができ、耐震性を向上させることができる。 According to the present invention, in the vertical SIP structure, by arranging the leads (35) supporting the substrate in a plurality of rows, the number of steps for applying the insulating resin can be reduced, and the earthquake resistance can be improved.

以下、図面に基づいて本発明の実施例を説明する。
図では、チップ抵抗やコンデンサなどの実回路上必要な実装部品、配線パターンなどは省略している。なお、この実施例によってこの発明が限定されるものではない。
＜実施例１＞ Embodiments of the present invention will be described below with reference to the drawings.
In the figure, mounting components and wiring patterns necessary for an actual circuit such as a chip resistor and a capacitor are omitted. The present invention is not limited to the embodiments.
<Example 1>

図１は、本発明の実施例１において、ＳＩＰ構造の単位回路基板（１０）が対向し固定されている斜視図を示すものである。 FIG. 1 shows a perspective view of a unit circuit board (10) having a SIP structure facing and fixed in Example 1 of the present invention.

具体的には、２つの前記ＳＩＰ構造の単位回路基板（１０）が互いに対向しており、前記単位回路基板（１０）の間には、導電性物質（５）、例えば導電性スペーサーを挟め、回路の機能を有するように電気的接続を施し、ネジ（６）にて固定している。 Specifically, two unit circuit boards (10) having the SIP structure face each other, and a conductive substance (5), for example, a conductive spacer, is sandwiched between the unit circuit boards (10). Electrical connection is made so as to have the function of a circuit, and it is fixed with screws (6).

基板を支えるリード（３５）が２列になることで、縦型のＳＩＰ構造においても、絶縁樹脂を塗布する工数を減らすことができ、耐震性を向上させることができる。
＜実施例２＞ Since the leads (35) supporting the substrate are arranged in two rows, the man-hour for applying the insulating resin can be reduced even in the vertical SIP structure, and the earthquake resistance can be improved.
<Example 2>

図２は、本発明の実施例２において、ＳＩＰ構造の単位回路基板（１０）が複数個あり、互いに対向し固定されている斜視図を示すものである。 FIG. 2 is a perspective view showing a plurality of unit circuit boards (10) having a SIP structure and facing each other and being fixed in the second embodiment of the present invention.

具体的には、複数の前記ＳＩＰ構造の単位回路基板（１０）が互いに対向しており、前記単位回路基板（１０）の間には、導電性物質（５）、例えば導電性スペーサーを挟め、回路の機能を有するように電気的接続を施し、ネジ（６）にて固定している。 Specifically, a plurality of unit circuit boards (10) having the SIP structure are opposed to each other, and a conductive substance (5), for example, a conductive spacer, is sandwiched between the unit circuit boards (10). Electrical connection is made so as to have the function of a circuit, and it is fixed with a screw (6).

基板を支えるリード（３５）が複数列になることで、縦型のＳＩＰ構造においても、絶縁樹脂を塗布する工数を減らすことができ、耐震性を向上させることができる。
＜実施例３＞ Since the leads (35) supporting the substrate are arranged in a plurality of rows, the man-hour for applying the insulating resin can be reduced even in the vertical SIP structure, and the earthquake resistance can be improved.
<Example 3>

図３は、本発明の実施例３において、ＳＩＰ構造の単位回路基板（１１）と単位回路基板（１２）が対向し固定されている斜視図を示すものである。 FIG. 3 shows a perspective view in which the unit circuit board (11) having the SIP structure and the unit circuit board (12) are fixed to face each other in the third embodiment of the present invention.

具体的には、電源回路におけるパワー素子を実装した単位回路基板（１１）と制御素子を実装した単位回路基板（１２）が互いに対向している。 Specifically, the unit circuit board (11) on which the power elements in the power supply circuit are mounted and the unit circuit board (12) on which the control elements are mounted face each other.

前記単位回路基板（１１）には、例えばパワーＭＯＳＦＥＴやコイルなど回路動作上発熱が大きくなるパワー素子（７）を搭載しており、前記単位回路基板（１２）は制御ＩＣや保護回路など制御素子（８）を搭載している。前記単位回路基板（１１）と単位回路基板（１２）の間には、熱伝導性に優れている導電性物質（９）、例えば金属性スペーサーを挟め、回路の機能を有するように電気的接続を施し、ネジ（６）にて固定している。 The unit circuit board (11) is equipped with a power element (7) that generates a large amount of heat during circuit operation, such as a power MOSFET or a coil, and the unit circuit board (12) is a control element such as a control IC or a protection circuit. (8) is installed. Between the unit circuit board (11) and the unit circuit board (12), an electrically conductive substance (9) excellent in thermal conductivity, for example, a metallic spacer is sandwiched, and electrical connection is made so as to have a circuit function. And fixed with screws (6).

発熱が大きいパワー素子などを搭載した前記単位回路基板（１１）の熱を、前記熱伝導性に優れている導電性物質（９）を介し、発熱が小さい制御素子などを搭載した前記単位回路基板（１２）へと放熱することで、単位回路基板の面積を小さくすることができる。 The unit circuit board on which the control element or the like with low heat generation is mounted via the conductive material (9) having excellent thermal conductivity, the heat of the unit circuit board (11) on which the power element or the like with high heat generation is mounted. By radiating heat to (12), the area of the unit circuit board can be reduced.

基板の面積が小さくなることにより耐震性が向上させることができ、また、基板を支えるリード（３５）が２列になることで、縦型のＳＩＰ構造においても、絶縁樹脂を塗布する工数を減らすことができ、耐震性を向上させることができる。
By reducing the area of the substrate, the earthquake resistance can be improved, and the leads (35) supporting the substrate are arranged in two rows, thereby reducing the number of steps for applying the insulating resin even in the vertical SIP structure. Can improve earthquake resistance.

以上のように、本発明の構造の半導体装置によれば、半導体装置の耐震性を向上させることが可能である。 As described above, according to the semiconductor device having the structure of the present invention, it is possible to improve the earthquake resistance of the semiconductor device.

本発明の第１の実施例を示す概略斜視図1 is a schematic perspective view showing a first embodiment of the present invention. 本発明の第２の実施例を示す概略斜視図Schematic perspective view showing a second embodiment of the present invention. 本発明の第３の実施例を示す概略斜視図Schematic perspective view showing a third embodiment of the present invention 従来の縦型のＳＩＰ構造のサブ基板を、メインボードに搭載した概略斜視図Schematic perspective view of conventional vertical SIP structure sub-board mounted on main board

符号の説明Explanation of symbols

５ 導電性物質
６ ネジ
７ パワー素子
８ 制御素子
９ 熱伝導性に優れている導電性物質
１０ 単位回路基板
１１ パワー素子を搭載した単位回路基板
１２ 制御素子を搭載した単位回路基板
２０ メインボード
２１ ＳＩＰ構造のサブ基板
３０ 絶縁性樹脂
３５ リード
４０ 回路部品














5 Conductive substance 6 Screw 7 Power element 8 Control element 9 Conductive substance excellent in thermal conductivity 10 Unit circuit board 11 Unit circuit board 12 equipped with power element Unit circuit board 20 equipped with control element Main board 21 SIP Sub-board 30 of structure Insulating resin 35 Lead 40 Circuit component














Claims (3)

単位回路基板（１０）を、１個または複数個の導電性物質（５）にて、回路の機能を有するように電気的接続を施し、前記単位回路基板（１０）は対向させるように固定し、耐震性を向上させる構造を特徴とする半導体装置。 The unit circuit board (10) is electrically connected with one or a plurality of conductive substances (5) so as to have a circuit function, and the unit circuit board (10) is fixed so as to face each other. A semiconductor device characterized by a structure that improves earthquake resistance. 前記単位回路基板（１０）は、複数個あり、耐震性を向上させる構造を特徴とする請求項１の半導体装置。 2. The semiconductor device according to claim 1, wherein there are a plurality of the unit circuit boards (10), and the structure improves the earthquake resistance. 前記導電性物質（５）は、熱伝導性に優れている物質を利用した接続方法による請求項１から２のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the conductive substance (5) is a connection method using a substance having excellent thermal conductivity.
JP2007167264A 2007-06-26 2007-06-26 Semiconductor device Pending JP2009009979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007167264A JP2009009979A (en) 2007-06-26 2007-06-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007167264A JP2009009979A (en) 2007-06-26 2007-06-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2009009979A true JP2009009979A (en) 2009-01-15

Family

ID=40324822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007167264A Pending JP2009009979A (en) 2007-06-26 2007-06-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2009009979A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5636178U (en) * 1979-08-29 1981-04-07
JPS6433168U (en) * 1987-08-25 1989-03-01
JPH04134874U (en) * 1991-06-10 1992-12-15 太陽誘電株式会社 Surface mount hybrid integrated circuit module
JPH06132445A (en) * 1992-10-19 1994-05-13 Nippon Avionics Co Ltd Package of electronic component
JPH0846354A (en) * 1994-07-29 1996-02-16 Omron Corp Circuit board and board support
JP2001352140A (en) * 2000-06-09 2001-12-21 Keihin Corp Substrate holder and substrate-mounting method using it

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5636178U (en) * 1979-08-29 1981-04-07
JPS6433168U (en) * 1987-08-25 1989-03-01
JPH04134874U (en) * 1991-06-10 1992-12-15 太陽誘電株式会社 Surface mount hybrid integrated circuit module
JPH06132445A (en) * 1992-10-19 1994-05-13 Nippon Avionics Co Ltd Package of electronic component
JPH0846354A (en) * 1994-07-29 1996-02-16 Omron Corp Circuit board and board support
JP2001352140A (en) * 2000-06-09 2001-12-21 Keihin Corp Substrate holder and substrate-mounting method using it

Similar Documents

Publication Publication Date Title
JP2009123859A (en) Semiconductor device
JPH09116057A (en) Apparatus for improvement of power diffusion of semiconductor device
JP2011108924A (en) Heat conducting substrate and method for mounting electronic component on the same
US10440811B2 (en) Active heatsink lid
JP2016115810A (en) Electronic apparatus
KR20050073571A (en) Thermal-conductive substrate package
JP2005142189A (en) Semiconductor device
JP2002171087A (en) Electronic equipment
JP6652144B2 (en) Electronic parts, manufacturing method of electronic parts, mechanical parts
JP6961902B2 (en) Component mounts and electronic devices
JP5318304B1 (en) Semiconductor module and semiconductor device
JP2009009979A (en) Semiconductor device
JP2019169638A (en) Heating component mounting structure
JP3104749B2 (en) Circuit device and method of manufacturing the same
JP2007035843A (en) Electronic circuit device
JP5072522B2 (en) Connection structure
JP2006019660A (en) Circuit board for surface mounting of power element
JP2004179313A (en) Circuit wiring board
JP2005039118A (en) Semiconductor device
JP5088939B2 (en) Laminated board
JP2010040569A (en) Electronic component module
JP2001237368A (en) Power module
KR20080004734A (en) Radiating structure in exothermic element
WO2021059914A1 (en) Electronic circuit device
JP2013038119A (en) Attachment structure of module

Legal Events

Date Code Title Description
A621 Written request for application examination

Effective date: 20100514

Free format text: JAPANESE INTERMEDIATE CODE: A621

A977 Report on retrieval

Effective date: 20120113

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120124

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20121120