JP2009009680A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of efficiently supplying a power source voltage without being affected by an operation limit voltage of a sense amplifier. <P>SOLUTION: The semiconductor device is provided with a first memory 2, and the first memory 2 includes a memory cell, a word-line driving circuit, the sense amplifier SA and a voltage developing circuit 5. The memory cell is connected to the word-line and a bit-line. The word-line driving circuit drives the word-line. The sense amplifier SA reads information of the memory cell through the bit-line. The voltage developing circuit 5 receives a first voltage GND, a second voltage VDD having potential higher than that of the first voltage GND, and a third voltage VPP having potential higher than the second voltage VDD from the outside. The voltage developing circuit 5 includes a first voltage adjustment circuit 10 to step down the third voltage VPP at a predetermined mode to generate a fourth voltage VSA having potential higher than that of the second voltage VDD and supply the fourth voltage to the sense amplifier SA. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a plurality of power supply voltages.

  A semiconductor device that operates using a plurality of types of internal power supply voltages is known. In the semiconductor device, the plurality of internal power supply voltages are selectively used according to the type of internal circuit. FIG. 1 is a block diagram showing an example of the configuration of the conventional semiconductor device. The semiconductor device 101 is supplied with a power supply voltage VDD (example: 1.5V) and a ground voltage GND (example: 0V) from the outside. A memory macro 102, a step-down circuit 111, a step-down circuit 112, a reference power supply 113, a negative pump (N pump) 114, and a positive pump (P pump) 115 are provided.

  The memory macro 102 is a DRAM core, and includes a cell array core 103 that stores data and a peripheral circuit 104 that controls the cell array core 103. The cell array core 103 includes a plurality of cells arranged in a matrix, a plurality of sense amplifiers, a word line driving circuit, a bit line precharge circuit, and a sense amplifier driving circuit. The peripheral circuit 104 includes a decoder and a controller.

  The step-down circuit 111 steps down the power supply voltage VDD to generate a high-side power supply voltage VPD (eg, 1.2 V) of the bit line precharge transistor, and outputs it to the cell array core 103. The step-down circuit 112 steps down the power supply voltage VDD to generate a power supply voltage VSA (eg, 1.0 V) for the sense amplifier SA and outputs it to the cell array core 103. The reference power supply 113 steps down the power supply voltage VSA for the sense amplifier SA to generate a reference voltage HVDD (for example, 0.5 V) and outputs it to the cell array core 103. The N pump 114 steps down and inverts the power supply voltage VDD, and drives the low-side voltage VKK (example: −0.4 V) when driving the word line, and the substrate potential VBB (example: −0.4 V) of the selection transistor. ) And output to the cell array core 103. The P pump 115 boosts the power supply voltage VDD, generates a high-side power supply voltage VPP (for example, 2.5 V) when driving the word line, and outputs the generated power supply voltage VPP to the cell array core 103.

  Conventionally, the power supply voltage VDD supplied to the entire circuit of the semiconductor device 101 is equal to or higher than the power supply voltage VSA supplied to the sense amplifier SA. Therefore, the power supply voltage VSA is generated directly from the power supply voltage VDD or by stepping down from VDD. Here, in the general-purpose DRAM, since the bit line division is small and the load capacitance is large, the operating current Isa of the sense amplifier SA is large. Therefore, compared to the word line current Iword, there is a relationship of Iword <Isa, and it is essential to generate the operating current Isa from a VDD power supply having sufficient current supply capability. Other voltage generations tend to do so. Recently, when the power supply voltage VPP for driving the word line is generated from the power supply voltage VDD, the current efficiency is poor, and therefore, the power supply voltage VPP is sometimes supplied from the outside.

  As an example of a semiconductor device that operates using a plurality of types of power supply voltages, a semiconductor memory device is disclosed in Japanese Patent Laid-Open No. 11-213667. The semiconductor memory device includes an input circuit and a peripheral circuit, a memory array unit, a first internal voltage down converter, and a second internal voltage down circuit. The memory array portion includes memory cells arranged in a matrix. The first internal voltage step-down circuit steps down the power supply voltage supplied from the output circuit and the external terminal to form a first internal voltage. The second internal voltage down converter steps down the power supply voltage supplied from the external terminal and forms a second internal voltage having a voltage value that is larger in absolute value than the first internal voltage. When the semiconductor memory device operates as the first power supply version in which the power supply voltage supplied from the external terminal is set to a voltage value that is larger in absolute value than the second internal voltage, the memory array section includes the first power supply version. The first internal voltage formed by one internal voltage down converter is supplied, the second internal voltage formed by the second internal voltage down circuit is supplied to the input circuit and the peripheral circuit, and the output circuit Supply power supply voltage. On the other hand, when the power supply voltage supplied from the external terminal is operated as a second power supply version set to a voltage value equal to the second internal voltage, the memory array portion is formed by the first internal voltage down converter. The first internal voltage is supplied, the output of the second internal step-down circuit is disconnected from the input circuit and the peripheral circuit, and the power supply voltage is supplied to the input circuit, the peripheral circuit and the output circuit.

Japanese Patent Laid-Open No. 11-213667

  In recent years, gate oxide films of logic circuit transistors have been made thinner for high-speed operation / low current. In that case, in the example of FIG. 1, the power supply voltage VDD of the logic circuit is lowered to 1.0 V or less. On the other hand, the power supply voltage VSA for the sense amplifier SA needs to be about 1.0 V from the operation limit voltage of the sense amplifier. Here, in general, the power supply voltage VDD is allowed to vary by ± 10%. If the power supply voltage VSA is to be generated from the power supply voltage VDD in which voltage reduction is significant, when the power supply voltage VDD decreases due to voltage fluctuation, a situation occurs in which the power supply voltage VSA must be generated by boosting. When the power supply voltage VSA is generated by boosting from such a power supply voltage VDD, the efficiency of voltage generation is greatly reduced. On the other hand, if the power supply voltage VSA is used without boosting, the operation speed of the sense amplifier is reduced. There is a demand for a technology that can efficiently supply a power supply voltage without reducing the operation speed of the sense amplifier and without being affected by the operation limit voltage.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the best mode for carrying out the invention. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of the claims and the best mode for carrying out the invention. However, these numbers and symbols should not be used for interpreting the technical scope of the invention described in the claims.

In order to solve the above problems, a semiconductor device of the present invention includes a first memory (2) and a voltage generation circuit (5). The first memory (2) includes a memory cell (26), a word line driving circuit (21), and a sense amplifier (24). Memory cell (26) is coupled to a word line (WL) and a bit line (Bit). The word line drive circuit (21) drives the word line (WL). The sense amplifier (24) amplifies the information in the memory cell (26) via the bit line (Bit). The voltage generation circuit (5) is externally supplied with a first voltage (GND), a second voltage (VDD) higher than the first voltage (GND), and a second voltage (VDD). A high potential third voltage (VPPorVPDorVSA) is supplied. The voltage generating circuit (5) steps down or boosts the third voltage (VPPPVPVPorVSA) in a predetermined mode to generate a fourth voltage (VSAorVPP) having a higher potential than the second voltage (VDD), and senses it. A first voltage adjusting circuit (10) for supplying to the amplifier (24) or the word line driving circuit (21) is provided.
In the present invention, the fourth voltage is reduced or boosted not from the second voltage (VDD) to be lowered, but from the third voltage (VPPorpPDorVSA) having a higher potential than the second voltage (VDD). (VSAorVPP) is generated. Thereby, even if the second voltage (VDD) fluctuates to the low voltage side, it is possible to realize a high-speed operation of the sense amplifier (24) without being affected by it.

The semiconductor device of the present invention includes a logic circuit (30) and a memory unit (20). The logic circuit (30) is supplied with a first voltage (GND) and a second voltage (VDD) higher than the first voltage (GND). The memory unit (20) is supplied with a first voltage (GND), a second voltage (VDD), and a third voltage (VPPoVPPDorVSA) higher than the second voltage (VDD). The memory unit (20) includes a first memory (2), a voltage generation circuit (5), and a refresh control circuit (40). The first memory (2) includes a peripheral circuit (4) to which a first voltage (GND) and a second voltage (VDD) are supplied, a first voltage (GND), and a third voltage (VPPPVPVPorVSA). And a cell array core (3) to be supplied. The voltage generation circuit (5) is supplied with the first voltage (GND) and the third voltage (VPPorVPDorVSA), and steps down or boosts the third voltage (VPPorVPDorVSA) in a predetermined mode to generate the second voltage. A fourth voltage (VPPorVPDorVSA) and a fifth voltage (VPPPVPorVSA) that are higher than (VDD) are generated and output to the cell array core (3). At this time, any one of the third voltage (VPPPVPVPorVSA), the fourth voltage (VPPoRPVPorVSA), and the fifth voltage (VPPPVPorVSA) is supplied to the sense amplifier (53) of the cell array core (3). One is supplied to each word line driving circuit. Furthermore, any one of the third voltage (VPPorVPDorVSA), the fourth voltage (VPPPVPVPorVSA) and the fifth voltage (VPPPVPVPorVSA) is supplied to the refresh control circuit (40). The refresh control circuit (40) performs a refresh operation of the cell array core (3) when the supply of the second power supply (VDD) is stopped.
In the present invention, the cell array core (3) and the refresh control circuit (40) are provided with the first voltage (GND) and the third voltage (VPPorpVPorVSA) supplied externally and other fourth voltages generated using them. The refresh operation is performed using the voltage (VPPorVPDorVSA) and the fifth voltage (VPPorVPDorVSA). That is, the second voltage (VDD) is not necessary for the refresh operation of the memory cell core (3). Therefore, the refresh operation of the memory cell core 3 can be continued even when the supply of the second voltage (VDD) is stopped. As a result, even if the second voltage (VDD) is stopped while the operation of the logic circuit (30) is temporarily stopped, such as in the sleep mode or the standby mode, other data stored in the memory 20 is not lost. By stopping the second voltage (VDD), power consumption associated with leakage current in the logic circuit (30) and the peripheral circuit (4) can be reduced in the semiconductor device.

  According to the present invention, the power supply voltage can be efficiently supplied without being affected by the operation limit voltage of the sense amplifier.

  Hereinafter, embodiments of a semiconductor device of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
FIG. 2 is a block diagram showing the configuration of the semiconductor device according to the first embodiment of the present invention. The semiconductor device 1 includes a memory using a plurality of power supply voltages, and is exemplified by a memory-embedded LSI (Large Scale Integration). The semiconductor device 1 includes a memory 20 and a logic circuit 30. The semiconductor device 1 is supplied with a power supply voltage VPP, a power supply voltage VDD, and a ground voltage GND from the outside. The memory 20 operates using the power supply voltage VPP, the power supply voltage VDD, and the ground voltage GND. The logic circuit operates using the power supply voltage VDD and the ground voltage GND.

  FIG. 3 is a block diagram showing a configuration of the semiconductor device according to the first embodiment of the present invention. In this figure, the memory 20 is particularly shown in detail. The semiconductor device 1 supplies a power supply voltage VPP (example: 2.5 V) for boosting a word line WL, a power supply voltage VDD (example: 0.9 V) for a logic circuit, and a ground voltage GND (example: 0 V) from the outside. Has been. The semiconductor device 1 (the memory 20 thereof) includes a memory macro 2 and a voltage adjustment unit 5.

  The voltage adjusting unit 5 generates a plurality of power supply voltages using a power supply voltage VPP, a power supply voltage VDD, and a ground voltage GND supplied from the outside. The plurality of power supply voltages are supplied to the memory macro 2 respectively. The voltage adjustment unit 5 includes a step-down circuit 11, a step-down circuit 12, a reference power supply 13, and a negative pump (N pump) 14. However, the step-down circuit 11 and the step-down circuit 12 are also collectively referred to as a first voltage adjustment circuit 10. The step-down circuit 11 is also called a second voltage adjustment circuit, and the step-down circuit 12 is also called a third voltage adjustment circuit. The voltage adjustment unit 5 can also be considered as a voltage generation circuit.

  The step-down circuit 11 steps down the power supply voltage VPP to generate a high-side power supply voltage VPD (for example, 1.2 V) of the bit line precharge transistor, and outputs it to the cell array core 3. The step-down circuit 12 steps down the power supply voltage VPP to generate a power supply voltage VSA (for example, 1.0 V) for the sense amplifier SA and outputs it to the cell array core 3. The reference power supply 13 steps down the power supply voltage VSA for the sense amplifier SA to generate a reference voltage HVDD (for example, 0.5 V) and outputs it to the cell array core 3. The N pump 14 steps down and inverts the power supply voltage VPP, and drives the low-side voltage VKK (example: −0.4 V) when driving the word line, and the substrate potential VBB (example: −0.4 V) of the selection transistor. ) And output to the cell array core 3.

  The memory macro 2 is a memory circuit exemplified as a DRAM core. The memory macro 2 includes a cell array core 3 that stores data and a peripheral circuit 4 that controls the cell array core 3. The cell array core 3 operates using the power supply voltages VPP and VDD, the power supply voltages VPD, VSA, HVDD, VKK, and VBB generated by the voltage adjusting unit 5 and the ground voltage GND. A plurality of cells arranged in a matrix, a plurality of sense amplifiers, a word line drive circuit 21, a bit line precharge circuit 22, and a sense amplifier drive circuit 23 are included. Furthermore, a row decoder (not shown) is included. The word line driving circuit 21, the bit line precharge circuit 22, and the row decoder are included in the word line driving unit WD. The peripheral circuit 4 includes a decoder and a controller used for the operation of the cell array core 3. Circuits other than the cell array core 3 including the peripheral circuit 4 in the memory macro 2 operate using the power supply voltage VDD and the ground voltage GND.

  FIG. 4 is a schematic diagram showing the configuration of the cell array core 3 in the first embodiment of the semiconductor device of the present invention. The cell array core 3 includes bit lines Bit (T), Bit (N), word lines WL, memory cells 26, precharge lines PDL, sense amplifier control lines SAP, SAN, memory cells 26, word line drive circuits 21, and bit lines. A precharge drive circuit 22, a sense amplifier drive circuit 23, a sense amplifier 24, and a precharge circuit 27 are provided.

Bit lines Bit (T) and Bit (N) extend in the Y direction. Bit lines Bit (T) and Bit (N) are selected by a column decoder (not shown) of the peripheral circuit 4.
The word line WL extends in the X direction perpendicular to the Y direction and is connected to the word line driving circuit 21. The word line WL is selected by a row decoder (not shown) of the word line driver WD.
The memory cell 26 is provided corresponding to the intersection of the bit lines Bit (T), Bit (N) and the word line WL. Memory cell 26 includes a select transistor Qc and a cell capacitance Cs. The cell capacitor Cs stores electric charge, one is connected to a wiring for supplying the reference voltage HVDD, and the other is connected to the selection transistor Qc. The selection transistor Qc is exemplified as an NMOS transistor, and has a gate connected to the word line WL, one of the source / drain connected to the bit line Bit (T), and the other connected to the cell capacitor Cs. The substrate potential of the selection transistor Qc is VBB (example: -0.4V).

  The word line driving circuit 21 supplies a voltage (signal) for driving the selection transistor Qc of the memory cell 26. That is, the word line driving circuit 21 supplies the word line WL with the power supply voltage VPP (for example, 2.5 V) for setting the gate of the selection transistor Qc in the high state and the VKK for setting the low state in the read operation or the write operation. (Example: -0.4V) is supplied. In this VKK, in order to suppress the leakage of the non-selected transistor Qc, a negative gate potential is applied to the non-selected cell to create a stronger non-selected (off) state.

The sense amplifier control lines SAP and SAN extend in the X direction and are connected to the sense amplifier drive circuit 23 and the sense amplifier 24, respectively.
The sense amplifier drive circuit 23 supplies a voltage (signal) for driving the sense amplifier 24. That is, during the read operation, the sense amplifier drive circuit 23 sends a high-side power supply voltage VSA (for example, 1.0 V) and a low-side ground voltage GND (through the sense amplifier control lines SAP and SAN to the sense amplifier 24. Example: 0V) is supplied.
The sense amplifier 24 is provided between each pair of bit lines Bit (T) and Bit (N). The sense amplifier control lines SAP and SAN are connected to the bit lines Bit (T) and Bit (N). The sense amplifier 24 detects and amplifies a voltage difference between a pair of bit lines Bit (T) and Bit (N) during a read operation of the memory cell 26. Based on the amplified potential difference, data in the memory cell 26 is read.

  FIG. 10 is a circuit diagram illustrating an example of a sense amplifier. The sense amplifier 24 includes transistors Tr11 to Tr16. A high-side power supply voltage VSA (example: 1.0 V) is supplied to the source of Tr16 (example: PMOS transistor) via the sense amplifier control line SAP. In addition, the low-side ground voltage GND (example: 0 V) is supplied to the source of Tr15 (example: NMOS transistor) via the sense amplifier control line SAN. Signals φs and / φs for controlling the operation of the sense amplifier 24 are supplied to the gates of the transistors Tr16 and Tr15 from the sense amplifier drive circuit 23 or another control circuit. The transistors Tr11 (example: NMOS transistor) and Tr12 (example: PMOS transistor) are connected in series, and the gate is connected to Bit (N) and the connection point between the transistors Tr13 (example: NMOS transistor) and 14 (example: PMOS transistor). The source of Tr11 is connected to the drain of the transistor Tr15, and the source of Tr12 is connected to the drain of the transistor Tr16. The transistors Tr13 and Tr14 are connected in series, with the gate connected to the connection point of Bit (T) and the transistors Tr11 and Tr12, the source of Tr13 connected to the drain of the transistor Tr15, and the source of Tr14 connected to the drain of the transistor Tr16. .

  If the power supply voltage VDD, which has been lowered due to the thinning of the gate oxide film corresponding to the speeding up of the logic circuit, is used as it is for the power supply voltage VSA of the sense amplifier 24, the read speed of the sense amplifier 24 is lowered. That is, if the power supply voltage VDD with a reduced voltage is used, the operation speed is lowered. In the present invention, separately from the power supply voltage VDD, the power supply voltage VSA set in the voltage adjustment unit 5 to be equal to or higher than the operation limit voltage of the sense amplifier 24 is used. Thereby, a sufficient power supply voltage VSA can be obtained without imposing a burden on the power supply voltage VDD, and a high-speed read operation can be realized.

Referring to FIG. 4, precharge line PDL extends in the X direction and is connected to bit line precharge drive circuit 22 and precharge circuit 27, respectively.
The precharge circuit 27 is provided between each pair of bit lines Bit (T) and Bit (N). Transistors Tr1 to Tr3 (example: NMOS transistors) are provided. Tr1 and Tr2 are connected in series, the gate is connected to the precharge line PDL, the source / drain of Tr1 is set to the bit line Bit (T), the source / drain of Tr2 is set to Bit (N), and the transistors Tr1, Tr2 The connection point of Tr2 is connected to the wiring sharing the reference voltage HVDD (example: 0.5V). The transistor Tr3 has a gate connected to the precharge line PDL and a source / drain connected to the bit lines Bit (T) and Bit (N). The precharge circuit 27 precharges the pair of bit lines Bit (T) and Bit (N) to the reference voltage HVDD when the memory cell 26 is on standby. The reference voltage HVDD is set to ½ of the power supply voltage VSA. Each transistor of the precharge circuit 27 is relatively miniaturized and the gate oxide film is also thin, and a power supply voltage VPD that is relatively low with respect to the power supply voltage VPP for boosting the word line is set in the High state. Can be used.
The bit line precharge drive circuit 22 supplies a voltage (signal) for driving the precharge circuit 27. That is, the power supply voltage VPD (example: 1.2 V) that sets the transistors Tr1 to Tr3 of the precharge circuit 27 to the high state and the ground voltage GND (example: 0 V) that sets the low state are supplied to the precharge line PDL, respectively. To do. Since the transistors Tr1 and Tr2 of the precharge circuit 27 are supplied with the reference voltage HVDD to the source / drain, the threshold voltage (eg 0.7V) of the transistors Tr1 and Tr2 is connected to the gate connected to the precharge line PDL. This is because the power supply voltage VPD that is higher than the reference voltage HVDD is required.

  FIG. 5 is a graph showing the relationship between the power supply voltages VPP, VDD, VPD, and VSA in the first embodiment of the semiconductor device of the present invention. The horizontal axis indicates the magnitude of the power supply voltage VDD, and the vertical axis indicates the magnitude of each of the power supply voltages VPP, VDD, VPD, and VSA. For each power supply voltage, the relative relationship is as described above, but the numerical value is an example. As a recent trend, in order to increase the speed of the peripheral circuit (logic circuit), the gate oxide film of the transistor in the peripheral circuit is becoming thinner. Along with this, the power supply voltage VDD for the peripheral circuit decreases to about 1.0V. However, since the sense amplifier has an operation limit voltage necessary for high-speed operation, it is not preferable to use the power supply voltage below a predetermined voltage. Here, the case where the power supply voltage VDD is 1.0 V and the power supply voltage VSA is 1.0 V is shown.

  Generally, the operating voltage of a semiconductor device is allowed to vary by ± 10%. Therefore, when the power supply voltage VDD is 1.0 V, the fluctuation range is 0.9 V or more and 1.1 V. The supplied power supply voltage VPP (2.5 V) is constant in this fluctuation range. The power supply voltage VSA (1.0 V) generated based on the power supply voltage VPP is also basically constant, and is constant until the power supply voltage VDD is 1.0 V (VSA> VDDmin). However, when the power supply voltage VDD is 1.0 V or higher, it rises equally to the power supply voltage VDD. This is for the withstand voltage and current countermeasure at the time of high VDD. Within the fluctuation range of the power supply voltage VDD, the power supply voltage VSA can be obtained by step-down. Similarly, the voltage VPD (1.2 V) generated based on the power supply voltage VPP is also constant within this fluctuation range.

The semiconductor device 1 of the present invention generates a low-voltage power supply voltage VSA for the sense amplifier 24 by stepping down a high-voltage power supply voltage VPP supplied from the outside for boosting the word line WL.
If the power supply voltage VSA is to be generated from the power supply voltage VDD as in the conventional case, for example, in the example of FIG. 5, when the power supply voltage VDD fluctuates to 0.9V, it is necessary to boost the voltage by 0.1V or more. It is. Further, when boosting is not performed, the power supply voltage VSA becomes lower than the operation limit voltage, and the operation speed of the sense amplifier 24 is reduced. In the present invention, the power supply voltage VSA is generated by stepping down from the high-voltage power supply voltage VPP, not from the power-supply voltage VDD that is lowered as the logic circuit speeds up (thinning the gate oxide film). Even if the voltage VDD fluctuates to the low voltage side, the high speed operation of the sense amplifier 24 can be realized.

  As described above, there is a product in which the power supply voltage VPP for boosting the word line WL is relatively high and the word line current Iword approaches the operating current Isa of the sense amplifier 24. In particular, depending on the type of memory macro 2 (example: eDRAM), the word line direction (X direction in FIG. 4) tends to be long and the bit line direction (Y direction in FIG. 4) tends to be short. Therefore, there are products in which Iword catches up with Isa or overtakes it. That is, since the ratio of Iword in the total current consumption is increased, it is very effective for the memory cell to supply the power supply voltage VPP from the outside.

Next, the operation of the semiconductor device 1 of the present invention will be described.
In addition to the power supply voltage VDD and the ground voltage GND, the semiconductor device 1 is supplied with a third voltage (here, the power supply voltage VPP) from the outside. The voltage adjustment unit 5 generates the power supply voltages VPD, VKK / VBB, VSA, and HVDD based on the power supply voltage VDD, the ground voltage GND, and the power supply voltage VPP, and outputs them to the cell array core 3. The cell array core 3 operates based on the power supply voltages VPP, VPD, VKK / VBB, VSA, HVDD, and GND. The peripheral circuit 4 operates based on the power supply voltages VDD and GND.

  According to the present invention, the power supply voltage VPP for boosting the word line WL is supplied from the outside, and the power supply voltage VSA for the sense amplifier is generated by stepping down the power supply voltage without being affected by fluctuations in the power supply voltage VDD. The voltage VSA can be generated. As a result, the power supply voltage VSA can be efficiently supplied, and a stable and high-speed operation can be performed.

(Second Embodiment)
FIG. 2 is a block diagram showing the configuration of the semiconductor device according to the second embodiment of the present invention. Since this figure is the same as that of the first embodiment except that the memory 20 is replaced with the memory 20b, description thereof will be omitted. FIG. 6 is a block diagram showing another configuration of the semiconductor device according to the second embodiment of the present invention. In this figure, the memory 20b is particularly shown in detail. This embodiment is different from the first embodiment in that the power supply voltage VPD is supplied from the outside instead of the power supply voltage VPP. That is, the semiconductor device 1b includes a high-side power supply voltage VPD (example: 1.2 V), a logic circuit power supply voltage VDD (example: 0.9 V), and a ground voltage GND (example: bit line precharge transistor). 0V) is supplied from the outside. The semiconductor device 1b (the memory 20b) includes a memory macro 2 and a voltage adjustment unit 5b.

  The voltage adjustment unit 5b generates a plurality of power supply voltages using the power supply voltage VPD, the power supply voltage VDD, and the ground voltage GND supplied from the outside. The plurality of power supply voltages are supplied to the memory macro 2 respectively. The voltage adjustment unit 5b includes a booster circuit 11a, a step-down circuit 12, a reference power supply 13, and a negative pump (N pump) 14. However, the step-up circuit 11a and the step-down circuit 12 are also collectively referred to as a first voltage adjustment circuit 10b. The step-up circuit 11a is also called a second voltage adjustment circuit, and the step-down circuit 12 is also called a third voltage adjustment circuit. The voltage adjustment unit 5b can also be considered as a voltage generation circuit.

  The booster circuit 11 a boosts the power supply voltage VPD to generate a power supply voltage VPP (for example, 2.5 V) for boosting the word line WL, and outputs it to the cell array core 3. The step-down circuit 12 steps down the power supply voltage VPD to generate a power supply voltage VSA (eg, 1.0 V) for the sense amplifier SA and outputs it to the cell array core 3. The reference power supply 13 steps down the power supply voltage VSA for the sense amplifier SA to generate a reference voltage HVDD (for example, 0.5 V) and outputs it to the cell array core 3. The N pump 14 steps down and inverts the power supply voltage VPD, and drives the low-side voltage VKK (example: −0.4 V) when driving the word line and the substrate potential VBB (example: −0.4 V) of the selection transistor. ) And output to the cell array core 3.

  Others are the same as those in the first embodiment with respect to FIG. 3 except that other power supply voltages are generated from the power supply voltage VPD instead of the power supply voltage VPP, and thus the description thereof is omitted.

Next, the operation of the semiconductor device 1b of the present invention will be described.
In addition to the power supply voltage VDD and the ground voltage GND, the semiconductor device 1 is supplied with a third voltage (here, the power supply voltage VPD) from the outside. The voltage adjustment unit 5 b generates the power supply voltages VPP, VKK / VBB, VSA, and HVDD based on the power supply voltage VDD, the ground voltage GND, and the power supply voltage VPD, and outputs them to the cell array core 3. The cell array core 3 operates based on the power supply voltages VPP, VPD, VKK / VBB, VSA, HVDD, and GND. The peripheral circuit 4 operates based on the power supply voltages VDD and GND.

  According to the present invention, the power supply voltage VPD for precharging the bit line is supplied from the outside, and the power supply voltage VSA for the sense amplifier is generated by stepping down the power supply voltage VSD without affecting the fluctuation of the power supply voltage VDD. VSA can be generated. As a result, the power supply voltage VSA can be efficiently supplied, and a stable and high-speed operation can be performed.

(Third embodiment)
FIG. 2 is a block diagram showing a configuration of the semiconductor device according to the third embodiment of the present invention. Since this figure is the same as that of the first embodiment except that the memory 20 is replaced with the memory 20c, the description thereof is omitted. FIG. 7 is a block diagram showing still another configuration of the third embodiment of the semiconductor device of the present invention. In this figure, the memory 20c is particularly shown in detail. This embodiment is different from the first embodiment in that the power supply voltage VSA is supplied from the outside instead of the power supply voltage VPP. That is, the semiconductor device 1c receives the power supply voltage VSA (example: 1.0V) for the sense amplifier SA, the power supply voltage VDD (example: 0.9V) for the logic circuit, and the ground voltage GND (example: 0V) from the outside. Have been supplied. The semiconductor device 1c (the memory 20c thereof) includes a memory macro 2 and a voltage adjustment unit 5c.

  The voltage adjustment unit 5c generates a plurality of power supply voltages using the power supply voltage VSA, the power supply voltage VDD, and the ground voltage GND supplied from the outside. The plurality of power supply voltages are supplied to the memory macro 2 respectively. The voltage adjustment unit 5c includes a booster circuit 11a, a booster circuit 12a, a reference power supply 13, and a negative pump (N pump) 14. However, the booster circuit 11a and the booster circuit 12a are also collectively referred to as a first voltage adjustment circuit 10c. The booster circuit 11a is also called a second voltage adjustment circuit, and the booster circuit 12a is also called a third voltage adjustment circuit. The voltage adjustment unit 5c can also be considered as a voltage generation circuit.

  The booster circuit 11a boosts the power supply voltage VSA to generate a high-side power supply voltage VPD (for example, 1.2 V) of the bit line precharge transistor, and outputs it to the cell array core 3. The booster circuit 12 a boosts the power supply voltage VSA to generate a power supply voltage VPP (for example, 2.5 V) for boosting the word line WL, and outputs it to the cell array core 3. The reference power supply 13 steps down the power supply voltage VSA to generate a reference voltage HVDD (example: 0.5 V) and outputs it to the cell array core 3. The N pump 14 steps down and inverts the power supply voltage VSA, and drives the low-side voltage VKK (example: −0.4 V) when driving the word line, and the substrate potential VBB (example: −0.4 V) of the selection transistor. ) And output to the cell array core 3.

  Others are the same as those in the first embodiment with respect to FIG. 3 except that other power supply voltages are generated from the power supply voltage VSA instead of the power supply voltage VPP, and the description thereof is omitted.

Next, the operation of the semiconductor device 1c of the present invention will be described.
In addition to the power supply voltage VDD and the ground voltage GND, the semiconductor device 1 is supplied with a third voltage (here, the power supply voltage VSA) from the outside. The voltage adjustment unit 5 c generates power supply voltages VPP, VPD, VKK / VBB, and HVDD based on the power supply voltage VDD, the ground voltage GND, and the power supply voltage VSA, and outputs them to the cell array core 3. The cell array core 3 operates based on the power supply voltages VPP, VPD, VKK / VBB, VSA, HVDD, and GND. The peripheral circuit 4 operates based on the power supply voltages VDD and GND.

  According to the present invention, the power supply voltage VSA for the sense amplifier SA is supplied and used from the outside, so that the power supply voltage VSA can be used without being affected by fluctuations in the power supply voltage VDD. As a result, the power supply voltage VSA can be efficiently supplied, and a stable and high-speed operation can be performed.

(Fourth embodiment)
FIG. 2 is a block diagram showing the configuration of the fourth embodiment of the semiconductor device of the present invention. Since this figure is the same as that of the first embodiment except that the memory 20 is replaced with the memory 20a, a description thereof will be omitted. FIG. 8 is a block diagram showing the configuration of the fourth embodiment of the semiconductor device of the present invention. In this figure, the memory 20a is particularly shown in detail. The semiconductor device 1a supplies a power supply voltage VPP (example: 2.5V) for boosting a word line WL, a power supply voltage VDD (example: 0.9V) for a logic circuit, and a ground voltage GND (example: 0V) from the outside. Has been. The semiconductor device 1 includes a DRAM macro 2a, an SRAM macro 6, and a voltage adjustment unit 5.

  Since the DRAM macro 2a (including the DRAM cell array core 3a) and the voltage adjustment unit 5 are the same as the memory macro 2 (including the cell array core 3) and the voltage adjustment unit 5 of the first embodiment, description thereof will be given. Is omitted.

The SRAM macro 6 is a memory circuit having a plurality of SRAM cells. The SRAM macro 6 includes an SRAM cell array core 7 that stores data and a peripheral circuit 8 that controls the SRAM cell array core 7. The peripheral circuit 8 operates with the power supply voltage VDD and the ground voltage GND. The peripheral circuit 8 includes a decoder, a controller, etc. used for the operation of the SRAM cell array core 7. The SRAM cell array core 7 operates using the power supply voltage VDD, the same power supply voltage V _SRAM as the power supply voltage VSA generated by the voltage adjustment unit 5, and the ground voltage VDD. It includes a plurality of SRAM cells, a plurality of bit lines, a plurality of word lines and the like arranged in a matrix.
In the fourth embodiment, since the power supply voltage VPP is supplied from the outside, VSA and VSRAM are supplied to the SRAM cell array core through the voltage adjustment unit 5. However, when the power supply voltage VSA is supplied from the outside as in the third embodiment, the input power supply voltage VSA is directly input to the SRAM cell array core as VSRAM without going through the voltage adjustment unit 5. You can enter it.

FIG. 11 is a circuit diagram showing an example of an SRAM cell. This SRAM cell includes transistors Tr21 to Tr24 (example: NMOS transistor) and transistors Tr25 to Tr26 (example: PMOS transistor). The transistors Tr25 to Tr26 are supplied with the power supply voltage V _SRAM at their sources. The drain of the transistor Tr25 is connected to one of the source / drain of the transistor Tr21, the gate of the transistor Tr24, and the drain of the transistor Tr23. The gate of the transistor Tr25 is connected to the gate of the transistor Tr24. The drain of the transistor Tr26 is connected to one of the source / drain of the transistor Tr22, the gate of the transistor Tr23, and the drain of the transistor Tr24. The gate of the transistor Tr26 is connected to the gate of the transistor Tr23. The transistors Tr23 to Tr24 are supplied with the ground potential GND at their sources. The gate of the transistor Tr21 is connected to the word line WL, and the other of the source / drain is connected to the bit line Bit (T). The gate of the transistor Tr22 is connected to the word line WL, and the other of the source / drain is connected to the bit line Bit (N).

The SRAM cell and the sense amplifier 24 of the DRAM of FIG. 10 have substantially the same circuit configuration (FF circuit). Therefore, in the same manner that the operation limit due to the lower voltage occurs in the sense amplifier 24 of the DRAM cell array core 3a, the power supply voltage VDD accompanying the thinning of the gate oxide film corresponding to the higher speed of the logic circuit is applied to the SRAM cell. Influenced by low voltage. That is, when the power supply voltage VDD with a reduced voltage is used, there arises a problem that the operation speed is lowered. Also for the SRAM cell, separately from the power supply voltage VDD, the power supply voltage VSA set by the voltage adjusting unit 5 to be equal to or higher than the operation limit voltage of the sense amplifier 24 is supplied as the power supply voltage V _SRAM for driving the SRAM cell. That is, in the case of FIG. 4, VSA = V _SRAM = 1.0 V with respect to VDD = 0.9 V). By doing so, it is possible to eliminate the influence on the operation speed of the SRAM cell with respect to the lowering of the power supply voltage VDD.

Since the power supply voltage VSA supplied to the sense amplifier 24 of the DRAM cell array core 3a can be supplied as the power supply voltage V _SRAM for driving the SRAM cell, the second embodiment to the third embodiment described above. Any of them is applicable to the fourth embodiment.

  According to the present invention, the effects of the first to third embodiments can be obtained, and the SRAM cell is stable against the reduction of the power supply voltage VDD due to the miniaturization of the logic circuit. High-speed operation can be performed.

  FIG. 9 is a table summarizing the first to third embodiments. This shows how VPP, VPD, and VSA are generated internally when the external input power supply is VPP, VPD, and VSA, respectively. For example, when the external input power supply is VPP (first embodiment), VPP is supplied from the outside, VPD is generated internally by the step-down of the external VPP, and VSA is generated by the step-down of the external VPP. . When the external input power source is VPD (second embodiment), VPD is supplied from the outside, VPP is generated by boosting the external VPP, and VSA is generated by stepping down the external VPD. When the external input power source is VSA (third embodiment), VSA is supplied from the outside, VPP is generated by boosting the external VSA, and VPD is generated by boosting the external VSA. Note that all of the first to third embodiments also correspond to the fourth embodiment.

(Fifth embodiment)
FIG. 2 is a block diagram showing a configuration of the semiconductor device according to the fifth embodiment of the present invention. Since this figure is the same as that of the first embodiment except that the memory 20 is replaced with the memory 20d, the description thereof is omitted. FIG. 12 is a block diagram showing the configuration of the semiconductor device according to the fifth embodiment of the present invention. In this figure, the memory 20d is particularly shown in detail. In the present embodiment, one of the power supply voltages supplied from the outside is not a specific power supply voltage (for example, VPP) set in advance, but is determined after manufacture. This is different from the embodiment. That is, the semiconductor device 1d is supplied with the power supply voltage V0 for the cell array core 3, the power supply voltage VDD for logic circuit (example: 0.9V), and the ground voltage GND (example: 0V) from the outside. Here, the power supply voltage V0 includes the power supply voltage VPP for boosting the word line WL (example: 2.5V), the power supply voltage VPD on the high side of the bit line precharging transistor (example: 1.2V), and the sense amplifier SA. Power supply voltage VSA (example: 1.0 V). The value of the power supply voltage V0 is set by a predetermined method after manufacture. Corresponding to the setting, step-up or step-down of the power supply voltage V0 is selected. The semiconductor device 1d (the memory 20d thereof) includes a memory macro 2 and a voltage adjustment unit 5d.

  FIG. 13 is a block diagram showing the configuration of the voltage adjusting unit in the fifth embodiment of the semiconductor device of the present invention. The voltage adjustment unit 5d includes a first voltage selection unit 16, a booster circuit 12a, a booster circuit 11a, a step-down circuit 11, a step-down circuit 12, a second voltage selection unit 17, an N pump 14, and a reference power supply 13.

The first voltage selection unit 16 selects any two of the booster circuit 12a, the booster circuit 11a, the step-down circuit 12, and the step-down circuit 11. Then, the supplied power supply voltage V0 is supplied to the two selected circuits.
Specifically, the first voltage selection unit 16 first sets the power supply voltage V0 to the power supply voltage VPP (example: 2.5V), the power supply voltage VPD (example: 1.2V), and the power supply voltage VSA (example: 1.0V). ). As a determination method, for example, a method in which two reference voltages Vref1 and Vref2 (VSA <Vref1 <VPD <Vref2 <VPP) are set in advance and compared with the power supply voltage V0 can be considered. Alternatively, for example, a method of putting a signal indicating the type of power supply voltage into the control signal S0 input from the outside to the memory 20d can be considered.
Next, the first voltage selection unit 16 outputs the power supply voltage V0 based on the above determination as follows. When the power supply voltage V0 is the power supply voltage VPP, the power supply voltage V0 is output to the step-down circuit 11 and the step-down circuit 12 as in the first embodiment. When the power supply voltage V0 is the power supply voltage VPD, the power supply voltage V0 is output to the step-up circuit 11a and the step-down circuit 12 as in the second embodiment. When the power supply voltage V0 is the power supply voltage VSA, the power supply voltage V0 is output to the booster circuit 11a and the booster circuit 12a as in the third embodiment. The first voltage selection unit 16 further directly outputs the power supply voltage V0 to the second voltage selection unit 17.

  The booster circuit 12 a and the booster circuit 11 a boost the supplied power supply voltage V 0 and output it to the second voltage selection unit 17. Further, the step-down circuit 12 and the step-down circuit 11 step down the supplied power supply voltage V0 and output it to the second voltage selection unit 17. These operations are as described in the first to third embodiments.

  The second voltage selection unit 17 uses the two voltages output from the two selected circuits and the power supply voltage V0 directly output from the first voltage selection unit 16 as the power supply voltages VPP, VPD, and VSA in descending order. Output to 3. As a method of determining the order of increasing, for example, a method of comparing with the reference voltage as described above, or a method of determining based on a signal indicating the type of power supply voltage included in the control signal S0 can be considered.

  Note that the first voltage selection unit 16 and the second voltage selection unit 17 may be set (fixed) to output destinations of those voltages by the control signal S0 after the semiconductor device 1d is manufactured. Further, it may be set to be changeable by the subsequent input of the control signal S0. As a setting method that cannot be changed, for example, a method of programming a setting in a fuse or a non-rewritable storage element can be considered. As a setting method that can be changed, a method of programming the setting in a rewritable storage element can be considered.

  The N pump 14 steps down and inverts the power supply voltage VPP, and drives the low-side voltage VKK (example: −0.4 V) when driving the word line, and the substrate potential VBB (example: −0.4 V) of the selection transistor. Are generated and output to the cell array core 3. However, the power supply voltages VPD and VSA may be input. The reference power supply 13 steps down the power supply voltage VSA to generate a reference voltage HVDD (for example, 0.5 V) and outputs it to the cell array core 3.

  Others are the same as those in the first embodiment related to FIG. 3 except that other power supply voltages are generated from the power supply voltage V0 instead of the power supply voltage VPP, and thus the description thereof is omitted.

Next, the operation of the semiconductor device 1d of the present invention will be described.
The semiconductor device 1 is supplied with a third voltage (here, the power supply voltage V0) from the outside in addition to the power supply voltage VDD and the ground voltage GND. The voltage adjustment unit 5d refers to the type and magnitude of the power supply voltage V0, and determines the power supply voltages VPP, VPD, VKK / VBB, VSA, and HVDD based on the power supply voltage VDD, the ground voltage GND, and the power supply voltage V0. Generate. Specifically, the first voltage selection unit 16 selects the step-up / step-down of the power supply voltage V0 with reference to the type and magnitude of the power supply voltage V0. Based on the selection, the power supply voltage V0 is output to any two of the step-up circuits 12a and 11a and the step-down circuits 12 and 11. When the power supply voltage V0 is supplied, the booster circuits 12a and 11a boost the power supply voltage V0. The step-down circuits 12 and 11 step down the power supply voltage V0 when the power supply voltage V0 is supplied. The second voltage selection unit 17 receives the power supply voltage V0 that has been stepped up / down from the two selected circuits, and directly receives the power supply voltage V0 from the first voltage selection unit 16. Then, referring to those sizes and the like, the maximum voltage is output to the cell array core 3 as the power supply voltage VPP, the middle voltage as the power supply voltage VPD, and the minimum voltage as the power supply voltage VSA. The power supply voltage VPP (VPD or VSA is acceptable) via the N pump 14 is output to the cell array core 3 as VKK / VBB. The power supply voltage VSA via the reference power supply 13 is output to the cell array core 3 as HVDD. The cell array core 3 operates based on the power supply voltages VPP, VPD, VKK / VBB, VSA, HVDD, and GND. The peripheral circuit 4 operates based on the power supply voltages VDD and GND.

  According to the present invention, the same effects as those of the first to third embodiments can be obtained. In addition, according to the present invention, the type of the power supply voltage V0 to be supplied can be determined after the semiconductor device is manufactured. Thereby, the freedom degree of use of a semiconductor device can be raised.

(Sixth embodiment)
FIG. 2 is a block diagram showing a configuration of the semiconductor device according to the sixth embodiment of the present invention. Since this figure is the same as that of the first embodiment except that the memory 20 is replaced with the memory 20e, the description thereof is omitted.

  FIG. 14 is a block diagram showing the configuration of the sixth embodiment of the semiconductor device of the present invention. In this figure, the memory 20e is particularly shown in detail. The semiconductor device 1e supplies the power supply voltage VPP (example: 2.5V) for boosting the word line WL, the power supply voltage VDD (example: 0.9V) for the logic circuit, and the ground voltage GND (example: 0V) from the outside. Has been. The semiconductor device 1e (the memory 20e thereof) includes a memory macro 2, a voltage adjustment unit 5, a step-down circuit 9, and a refresh control circuit 40.

  In recent years, power supply voltage VDD in logic circuits and memories has been reduced due to the demand for low power consumption. This is because when the power supply voltage VDD is lowered, a current (active current) that flows during the operation of the transistor is reduced, so that power consumption can be reduced. However, when the power supply voltage VDD is lowered, the performance of the transistor (decrease in operating speed) may occur. In order to prevent performance degradation, it is effective to lower the threshold voltage of the transistor. However, when the threshold voltage is lowered, an increase in leakage current may occur, resulting in an increase in power consumption. In order to suppress an increase in leakage current, it is conceivable to temporarily stop the supply of the power supply voltage VDD when the logic circuit is not operating. However, in the case where a DRAM is used as the memory, if the supply of the power supply voltage VDD is merely temporarily stopped, the refresh operation cannot be performed and the stored data is lost.

  In the present embodiment, the refresh operation (Self-Refresh operation) in the cell array core 3 can be continuously performed and the power supply voltage VDD can be temporarily stopped. Thereby, power consumption due to leakage current in the transistors of the logic circuit 30 and the peripheral circuit 4 can be reduced by temporarily stopping the power supply voltage VDD while preventing the data stored in the memory 20e from being erased by the refresh operation.

Hereinafter, the semiconductor device 1e (memory 20e) will be described in detail.
The step-down circuit 9 steps down the power supply voltage VPP for boosting the word line WL to generate the power supply voltage Vx for the voltage adjustment unit 5. The voltage adjustment unit 5 operates with the power supply voltage Vx instead of the power supply voltage VDD. However, the supply of the power supply voltage Vx may be performed only when the supply of the power supply voltage VDD is stopped (described later). In that case, the power supply voltage VDD is supplied in the normal operation of the voltage adjusting unit 5.

  The voltage adjustment unit 5 is the same as that of the first embodiment except that it operates with the power supply voltage Vx. That is, a plurality of power supply voltages are generated using a power supply voltage VPP, a power supply voltage Vx, and a ground voltage GND supplied from the outside. The plurality of power supply voltages are supplied to the memory macro 2 respectively. Details thereof are omitted.

  The memory macro 2 is a memory circuit exemplified as a DRAM core. The memory macro 2 includes a cell array core 3 that stores data and a peripheral circuit 4 that controls the cell array core 3.

  The cell array core 3 operates using the power supply voltage VPP, the power supply voltages VPD, VSA, HVDD, VKK, and VBB generated by the voltage adjusting unit 5 and the ground voltage GND. The cell array core 3 includes a cell array (Cell) 51, a word line driving unit (WD) 52, and a sense amplifier unit (SA) 53. The cell array 51 includes a plurality of cells 26 arranged in a matrix corresponding to the intersections of a plurality of word lines WL, a plurality of bit lines BL, and a plurality of word lines WL and a plurality of bit lines BL (Bit). Have. The word line drive unit 52 includes a word line drive circuit 21, a bit line precharge circuit 22, and a row decoder (not shown). The sense amplifier unit 53 includes a plurality of sense amplifiers and a sense amplifier drive circuit 23.

  The peripheral circuit 4 includes a controller 61 used for the operation of the cell array core 3, a column decoder 62, and an I / O unit 63. Circuits other than the cell array core 3 including the peripheral circuit 4 in the memory macro 2 operate using the power supply voltage VDD and the ground voltage GND.

  The configuration of the cell array core 3 in FIG. 4, the relationship between the power supply voltages VPP, VDD, VPD, and VSA in FIG. 5 and the configuration of an example of the sense amplifier in FIG. 10 are the same as those in the first embodiment and will be described. Is omitted.

  The refresh control circuit 40 performs a refresh operation of the cell array core 3 when the supply of the power supply voltage VDD is stopped. The refresh control circuit 40 operates using the power supply voltage VSA generated by the voltage adjustment unit 5. However, it may be operated with the power supply voltage VPD generated by the voltage adjusting unit 5 as indicated by a broken line in the drawing, or may be operated with the power supply voltage VPP. In this case, for example, the characteristics of the elements constituting the refresh control circuit 40 are made to correspond to the power supply voltage used. The refresh control circuit 40 includes a timer 41, an address counter 42, and a register 43.

  The timer 41 outputs a signal requesting a refresh operation to the word line driving unit 52 at a predetermined cycle. The address counter 42 outputs a row address for executing the refresh operation to the word line driving unit 52. The word line driving unit 52 performs a refresh operation for the row corresponding to the row address from the address counter 42 in response to a signal from the timer 41 output at a predetermined cycle. When the refresh operation for one row is completed, the address counter 42 outputs the next row address to the word line driver 52 in preparation for the next refresh.

  The register 43 stores information indicating a range in the cell array 51 where a refresh operation is performed. That is, the register 43 stores information indicating a range of row addresses (for example, xx row to yy row) in which a refresh operation is performed. The address counter 42 outputs a row address within a range of row addresses (example: xx row to yy row) indicated in the information of the register 43 in the refresh operation. As a result, when the row address range for performing the refresh operation is, for example, 100% / 50% / 25% of the entire row, the refresh operation is performed for the 100% / 50% / 25% range of the cell array 51. If the refresh operation is always performed in the range of 100%, the register 43 may be omitted.

  In the present embodiment, voltage adjustment unit 5 operates using power supply voltage VPP and ground voltage GND supplied from the outside. Therefore, the voltage adjustment unit 5 can generate other power supply voltages VPD, VKK / VBB, VSA, and HVDD necessary for the refresh operation without using the power supply voltage VDD. Therefore, the power supply voltage VDD is not required for supplying the power supply voltages VPP, VPD, VKK / VBB, VSA, and HVDD necessary for the refresh operation of the memory cell core 3. In addition, the refresh control circuit 40 also operates using the power supply voltage VPP supplied from the outside or the power supply voltage generated by the voltage adjusting unit 5 and the ground voltage GND. Therefore, the power supply voltage VDD is not necessary for the refresh operation of the refresh control circuit 40. As described above, in the present embodiment, the refresh operation of the memory cell core 3 can be performed in association with the supply of the power supply voltage VDD being stopped. As a result, when a situation where the power supply voltage VDD is unnecessary such as the operation of the logic circuit 30 being temporarily stopped, such as the sleep mode and the standby mode, the data stored in the memory 20 is not lost, and the power supply The voltage VDD can be stopped. By stopping the power supply voltage VDD, in the semiconductor device 1d, it is possible to reduce power consumption due to leakage current in the logic circuit 30 and the peripheral circuit 4.

  Further, by using the register 43, the refresh operation target can be executed not on the entire cell array 51 but on the portion of the cell array 51. By constraining the refresh operation to only the portion of the cell array 51, power consumption related to the refresh operation can be suppressed. That is, the power consumption of the semiconductor device 1d can be further reduced.

Next, the operation of the semiconductor device 1e of the present invention will be described.
The semiconductor device 1e stops supplying the power supply voltage VDD when the logic circuit 30 is not used, such as in the sleep mode or the standby mode. The logic circuit 30 and the peripheral circuit 4 that operate at the power supply voltage VDD stop operating. Leakage current does not flow through these transistors, reducing power consumption. On the other hand, the voltage adjustment unit 5 is supplied with the power supply voltage VPP, the ground voltage GND, and the power supply voltage Vx from the step-down circuit 9. The voltage adjustment unit 5 generates the power supply voltages VPD, VKK / VBB, VSA, and HVDD based on the power supply voltage VPP, the ground voltage GND, and the power supply voltage Vx. Each power supply voltage VPP, VPD, VKK / VBB, VSA, HVDD and ground voltage GND are output to the cell array core 3. The cell array core 3 can operate with these power supply voltages. The refresh control circuit 40 is supplied with any one of the power supply voltages VPP, VPD, and VSA. The refresh control circuit 40 can operate with its power supply voltage. The cell array core 3 performs a refresh operation on the memory cell 26 on the word line WL indicated by the row address from the address counter 42 at the timing of the signal from the timer 41.

According to the present invention, the same effects as those of the first embodiment can be obtained.
In addition, power consumption due to leakage current in the logic circuit and peripheral circuit transistors can be reduced by temporarily stopping the power supply voltage VDD while preventing the data stored in the memory from being erased by the refresh operation.

  In the semiconductor device 1e shown in FIG. 14, VPP is supplied from the outside as a power supply voltage, as in the first embodiment. However, as in the second embodiment, VPD may be supplied from the outside as a power supply voltage. This is shown in FIG. FIG. 15 is a block diagram showing another configuration of the sixth embodiment of the semiconductor device of the present invention. The overall view is FIG. 2 in which the memory 20 is replaced with the memory 20f. In this semiconductor device 1f (including the memory 20f), the power supply voltage supplied from the outside is VPD, the voltage adjustment unit is the same voltage adjustment unit 5b as in the second embodiment, and the step-down circuit 9a Except that the power supply voltage Vx is generated from the power supply voltage VPD, it is the same as in the case of FIG. In this case, the same effect as in FIG. 14 can be obtained.

  In the semiconductor device 1e shown in FIG. 14, VPP is supplied from the outside as a power supply voltage, as in the first embodiment. However, as in the third embodiment, VSA may be supplied from the outside as a power supply voltage. This is shown in FIG. FIG. 16 is a block diagram showing still another configuration of the sixth embodiment of the semiconductor device of the present invention. The overall view is FIG. 2 in which the memory 20 is replaced with the memory 20g. In this semiconductor device 1g (including the memory 20g), the power supply voltage supplied from the outside is VSA, the voltage adjustment unit is the same voltage adjustment unit 5c as in the third embodiment, and the step-down circuit 9b Except that the power supply voltage Vx is generated from the power supply voltage VSA, it is the same as in the case of FIG. In this case, the same effect as in FIG. 14 can be obtained.

  The present invention is not limited to the embodiments described above, and it is obvious that the embodiments can be appropriately modified or changed within the scope of the technical idea of the present invention.

FIG. 1 is a block diagram showing an example of the configuration of the conventional semiconductor device. FIG. 2 is a block diagram showing the configuration of the embodiment of the semiconductor device of the present invention. FIG. 3 is a block diagram showing a configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a schematic diagram showing the configuration of the cell array core 3 in the first embodiment of the semiconductor device of the present invention. FIG. 5 is a graph showing the relationship between the power supply voltages VPP, VDD, VPD, and VSA in the first embodiment of the semiconductor device of the present invention. FIG. 6 is a block diagram showing another configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 7 is a block diagram showing still another configuration of the third embodiment of the semiconductor device of the present invention. FIG. 8 is a block diagram showing the configuration of the fourth embodiment of the semiconductor device of the present invention. FIG. 9 is a table summarizing the first to third embodiments. FIG. 10 is a circuit diagram illustrating an example of a sense amplifier. FIG. 11 is a circuit diagram showing an example of an SRAM cell. FIG. 12 is a block diagram showing the configuration of the semiconductor device according to the fifth embodiment of the present invention. FIG. 13 is a block diagram showing the configuration of the voltage adjusting unit in the fifth embodiment of the semiconductor device of the present invention. FIG. 14 is a block diagram showing the configuration of the sixth embodiment of the semiconductor device of the present invention. FIG. 15 is a block diagram showing another configuration of the sixth embodiment of the semiconductor device of the present invention. FIG. 16 is a block diagram showing still another configuration of the sixth embodiment of the semiconductor device of the present invention.

Explanation of symbols

1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 101 Semiconductor device 2, 102 Memory macro 2a DRAM macro 3, 103 Cell array core 3a DRAM cell array core 4, 104 Peripheral circuit 5, 5b, 5c, 5d Voltage adjustment Part 6 SRAM macro 7 SRAM cell array core 8 Peripheral circuit 9, 9a, 9b Step-down circuit 11, 12, 111, 112 Step-down circuit 11a, 12a Step-up circuit 13, 113 Reference power supply 14, 114 Negative pump (N pump)
16 First voltage selection unit 17 Second voltage selection unit 20, 20a, 20b, 20c, 20d, 20e, 20f, 20g Memory 30 Logic circuit 51 Cell array 52 Word line drive unit 53 Sense amplifier unit 61 Controller 62 Column decoder 63 I / O part 115 positive pump (P pump)

Claims (11)

A first memory;
A voltage generation circuit to which a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage are supplied;
The first memory is
A memory cell coupled to the word line and the bit line;
A word line driving circuit for driving the word line;
A sense amplifier that amplifies the information of the memory cell via the bit line;
The voltage generation circuit includes:
The third voltage is stepped down or boosted in a predetermined mode to generate a fourth voltage having a higher potential than the second voltage, and supplied to the sense amplifier or the word line driving circuit. A semiconductor device provided with a circuit. The semiconductor device according to claim 1,
The first memory is a DRAM semiconductor device. The semiconductor device according to claim 1,
The first voltage adjustment circuit includes:
A second voltage adjusting circuit that steps down the third voltage, generates a fifth voltage between the third voltage and the fourth voltage, and supplies the fifth voltage to the precharge circuit;
A third voltage adjusting circuit that steps down the third voltage, generates the fourth voltage, and supplies the fourth voltage to the sense amplifier. The semiconductor device according to claim 1,
The first voltage adjustment circuit includes:
A third voltage adjusting circuit that steps down the third voltage, generates a fifth voltage between the third voltage and the second voltage, and supplies the fifth voltage to the sense amplifier;
And a second voltage adjusting circuit that boosts the third voltage, generates the fourth voltage, and supplies the fourth voltage to the word line driving circuit. The semiconductor device according to claim 1,
The first voltage adjustment circuit includes:
A second voltage adjusting circuit that boosts the third voltage, generates a fifth voltage between the third voltage and the fourth voltage, and supplies the fifth voltage to the precharge circuit;
And a third voltage adjusting circuit that boosts the third voltage, generates the fourth voltage, and supplies the fourth voltage to the word line driving circuit. The semiconductor device according to any one of claims 1 to 5,
An SRAM as a second memory;
The first voltage adjustment circuit further supplies the fourth voltage to a sense amplifier of the SRAM. A word line input to a memory cell in the memory chip;
A word line driving circuit for driving the word line;
A bit line to which the memory cell is connected;
A sense amplifier for reading information of the memory cell;
A voltage generation circuit,
The voltage generation circuit includes:
A first voltage;
A second voltage having a higher potential than the first voltage;
A third voltage higher than the second voltage, and
The third voltage is stepped up or stepped down in a predetermined mode to generate a fourth voltage and a fifth voltage, and each is supplied to either the sense amplifier or the word line driving circuit. Semiconductor device. The semiconductor device according to claim 3, wherein:
The voltage generation circuit includes:
A semiconductor device comprising: a selection unit that selects whether the third voltage is stepped up or stepped down to generate the fourth voltage and the fifth voltage based on the third voltage or the control signal. apparatus. The semiconductor device according to any one of claims 1 to 8,
A logic circuit;
The first voltage and the second voltage are used as at least a power supply voltage of the logic circuit. A logic circuit supplied with a first voltage and a second voltage higher than the first voltage;
A memory unit to which the first voltage, the second voltage, and a third voltage higher than the second voltage are supplied;
The memory unit is
A first memory;
A voltage generation circuit;
A refresh control circuit,
The first memory is
A peripheral circuit supplied with the first voltage and the second voltage;
A cell array core to which the first voltage and the third voltage are supplied;
The voltage generation circuit includes:
The first voltage and the third voltage are supplied, and the third voltage is stepped down or boosted in a predetermined mode, and a fourth voltage and a fifth voltage that are higher than the second voltage. Generate voltage and output to cell array core,
Any one of the third voltage, the fourth voltage, and the fifth voltage is supplied to a sense amplifier of the cell array, and the other is supplied to a word line driving circuit.
Any one of the third voltage, the fourth voltage, and the fifth voltage is supplied to the refresh control circuit,
The refresh control circuit includes:
A semiconductor device that performs a refresh operation of the cell array core when the supply of the second power is stopped. The semiconductor device according to claim 10.
The refresh control circuit performs the refresh operation only on a predetermined portion of the cell array core.

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