KR20190054812A - Method of operating memory device and memory device performing the same - Google Patents

Abstract

In a driving method of a memory apparatus, the memory apparatus operates in one mode among a normal mode, a first self-refresh mode in which time required for performing a self-refresh operation for saving data stored in memory cells without an external command and returning to the normal mode is shorter than a reference time, and a second self-refresh mode in which the time required for performing the self-refresh operation and returning to the normal mode is longer than the reference time. In the normal mode, a first driving voltage having a first level is generated and provided to the memory cells. When entering the second self-refresh mode, the level of the first driving voltage is changed to a second level, which is lower than the first level, and is provided to the memory cells.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a memory device,

The present invention relates to a semiconductor memory device, and more particularly, to a method of driving a memory device and a memory device performing the driving method.

The semiconductor memory device may be divided into a volatile memory device and a nonvolatile memory device depending on whether the stored data is lost when the power supply is interrupted. Among semiconductor memory devices, a volatile memory device such as a dynamic random access memory (DRAM) may perform a refresh operation to maintain stored data. In recent years, volatile memory devices have been applied to various types of mobile systems. In mobile systems, it is important to reduce power consumption, and various techniques for reducing power consumption of volatile memory devices have been studied.

It is an object of the present invention to provide a method of driving a memory device capable of reducing power consumption in a refresh mode.

It is another object of the present invention to provide a memory device capable of reducing power consumption in a refresh mode.

In order to achieve the above object, in a method of driving a memory device according to embodiments of the present invention, the memory device performs a self refresh operation to save data stored in memory cells in a normal mode and without an external command A first self-refresh mode in which the time required for returning to the normal mode is shorter than a reference time, and a second self-refresh mode in which the time required for returning to the normal mode is longer than the reference time do. In the normal mode, a first driving voltage having a first level is generated and provided to the memory cells. Refresh mode, the level of the first driving voltage is changed to a second level lower than the first level and provided to the memory cells.

In order to achieve the above object, in a method of driving a memory device according to embodiments of the present invention, the memory device performs a self refresh operation to save data stored in memory cells in a normal mode and without an external command A first self-refresh mode in which the time required for returning to the normal mode is shorter than a reference time, and a second self-refresh mode in which the time required for returning to the normal mode is longer than the reference time do. In the normal mode, a first driving voltage having a first variable level that varies depending on the operating temperature of the memory device is generated and provided to the memory cells. When the first self-refresh mode is entered, the level of the first driving voltage is changed to a first fixed level that is constant regardless of the operating temperature, and is provided to the memory cells. When the memory cell enters the second self-refresh mode, changes the level of the first driving voltage to a second fixed level lower than the first variable level and the first fixed level and constant regardless of the operating temperature, .

According to another aspect of the present invention, there is provided a memory device including a memory cell array, a first voltage controller, and a first voltage generator. The memory cell array includes a plurality of memory cells that operate based on a first driving voltage. The first voltage controller generates a first voltage control signal for adjusting a level of the first driving voltage based on a first control signal and a second control signal. Wherein the first voltage generator generates the first drive voltage based on a power supply voltage and the first voltage control signal, sets the level of the first drive voltage to a first level in a normal mode, A self refresh operation for saving data stored in cells and setting a level of the first driving voltage to a second level in a first self refresh mode in which a time required for returning to the normal mode is shorter than a reference time, Refreshing mode in which the time required for performing the self-refresh operation and returning to the normal mode is longer than the reference time, the level of the first driving voltage is lower than the first level and the third level lower than the second level in the second self- .

In the second self-refresh mode in which the time required for returning to the normal mode is relatively long and the self-refresh operation is performed, the driving voltage supplied to the memory cells Can be changed to a level different from that in the normal mode. For example, in the second self-refresh mode, the level of the first drive voltage higher than the power supply voltage can be reduced, and the level of the second drive voltage lower than the ground voltage can be increased. Further, the execution time of the self-refresh operation and / or the cycle of the self-refresh operation can be adaptively adjusted. Therefore, in the second self-refresh mode, the self-refresh current can be reduced while ensuring the characteristics of the self-refresh operation, and the power consumption of the memory device can be reduced.

1 is a flowchart showing a method of driving a memory device according to embodiments of the present invention.
2 is a diagram for explaining an operation mode of a memory device according to embodiments of the present invention.
3 is a block diagram illustrating a memory device in accordance with embodiments of the present invention.
4 is a circuit diagram showing an example of a voltage controller included in the memory device of FIG.
5 is a timing chart for explaining the operation of the voltage controller of FIG.
6A and 6B are graphs for explaining an example of a level change of the driving voltage according to the embodiments of the present invention.
FIG. 7 is a graph for explaining an example of characteristic compensation of the self-refresh operation according to the embodiments of the present invention.
8A, 8B and 8C are graphs for explaining another example for the characteristic compensation of the self-refresh operation according to the embodiments of the present invention.
9 is a graph for explaining another example of the level change of the driving voltage according to the embodiments of the present invention.
10 is a flowchart showing a method of driving a memory device according to embodiments of the present invention.
11 is a block diagram illustrating a memory device in accordance with embodiments of the present invention.
12A, 12B and 13 are graphs for explaining still another example of the level change of the driving voltage according to the embodiments of the present invention.
14 is a block diagram illustrating a memory system including a memory device in accordance with embodiments of the present invention.
15 is a block diagram illustrating a computing system including a memory device in accordance with embodiments of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a flowchart showing a method of driving a memory device according to embodiments of the present invention. 2 is a diagram for explaining an operation mode of a memory device according to embodiments of the present invention.

Referring to FIGS. 1 and 2, in the method of driving a memory device according to embodiments of the present invention, the memory device performs a refresh operation to store or maintain stored data, And performs a self refresh operation for storing or maintaining data.

The memory device operates in a normal mode and two or more self-refresh modes. The normal mode represents a general operation mode in which a data write operation, a data read operation, and the like are performed. The first self-refresh mode represents an operation mode in which the self-refresh operation is performed, and the time (ie, the exit time) required to return from the first self-refresh mode to the normal mode is shorter than the reference time. The second self-refresh mode also indicates the operation mode in which the self-refresh operation is performed, but the time required to return from the second self-refresh mode to the normal mode is longer than the reference time.

For example, as shown in FIG. 2, the operation modes of the memory device include a normal mode NM, a self refresh mode SR, a self refresh with power down mode mode (SRPD) and a deep sleep mode (DSM). The self-refresh operation can be performed in both the regular self-refresh mode SR, the self-refresh power-down mode SRPD, and the deep sleep mode DSM. While the self-refresh operation is not being performed, the memory device may be in an idle state in a regular self-refresh mode (SR), a power-down state in a self-refresh power down mode (SRPD) (DSM) may be in a deep sleep state.

The memory device may enter one of the regular self-refresh mode SR, the self-refresh power-down mode SRPD and the deep sleep mode DSM in the normal mode NM, Can enter one of power down mode (SRPD) and deep sleep mode (DSM), and can enter deep sleep mode (DSM) in self-refresh power down mode (SRPD).

When the regular self-refresh mode SR is ended, the memory device can immediately enter the normal mode NM. However, when the self-refresh power down mode (SRPD) or the deep sleep mode (DSM) is terminated, the memory device can not immediately enter the normal mode (NM) and the self refresh power down mode (SRPD) The user can enter the normal mode NM via the regular self refresh mode SR and the self refresh power down mode SRPD and the regular self refresh mode SR when the deep sleep mode DSM is ended It is possible to enter the normal mode (NM). Therefore, it takes a comparatively short time to terminate the regular self-refresh mode (SR), but it may take a relatively long time to terminate the self-refresh power down mode (SRPD) or the deep sleep mode (DSM).

In this specification, the normal self-refresh mode SR of FIG. 2 may correspond to the first self-refresh mode, and the deep sleep mode DSM of FIG. 2 may correspond to the second self-refresh mode. Alternatively, the self-refresh power down mode SRPD of FIG. 2 may correspond to the second self-refresh mode, depending on the embodiment.

Hereinafter, embodiments of the present invention will be described in detail based on the case where the deep sleep mode (DSM) of FIG. 2 is the second self-refresh mode.

In the normal mode NM, a driving voltage is generated and provided to a plurality of memory cells included in the memory device (step S100). The data is stored in the plurality of memory cells, and the plurality of memory cells can operate based on the driving voltage.

In the first self-refresh mode SR, the level of the driving voltage can be maintained and provided to the plurality of memory cells (step S200). In other words, the memory device can perform the self-refresh operation based on the drive voltage that has not been level-changed in the first self-refresh mode (SR).

When entering the second self-refresh mode (DSM), the level of the driving voltage is changed and provided to the plurality of memory cells (step S300). In other words, the memory device may perform the self-refresh operation based on the drive voltage level-changed in the second self-refresh mode (DSM). At this time, the level of the driving voltage may be changed to reduce the power consumption of the memory device.

In one embodiment, the driving voltage may include at least one of a boost voltage having a level higher than the power supply voltage and a negative voltage having a level lower than the ground voltage. For example, in step S300, the above-described level changing operation may be performed in the direction of decreasing the level of the boosted voltage, and the level changing operation described above may be performed in the direction of increasing the level of the negative voltage have.

When the second self refresh mode (DSM) ends, the level of the driving voltage can be restored (step S400). As described above, since it takes a longer time than the reference time to return to the normal mode NM after the second self-refresh mode DSM, the level of the driving voltage is set to the original level (That is, the level in the normal mode NM). For example, in step S400, the above-described level restoration operation may be performed in the direction of increasing the level for the boosted voltage, and the level restoration operation described above may be performed in the direction of decreasing the level for the negative voltage have.

Thus, in the normal mode NM after the end of the second self-refresh mode DSM, the level-regulated drive voltage can be provided to the plurality of memory cells.

3 is a block diagram illustrating a memory device in accordance with embodiments of the present invention.

3, the memory device 200 includes a control logic 210, a refresh control circuit 215, an address register 220, a bank control logic 230, a row address multiplexer 240, a column address latch 250 A data input / output buffer 295, a first voltage controller 310, a first voltage generator 320, a second voltage controller 342, (330) and a second voltage generator (340).

In one embodiment, the memory device 200 may be a volatile memory device that requires the above-described refresh operation, particularly the self-refresh operation. For example, the memory device 200 may be any volatile memory device such as a dynamic random access memory (DRAM), a mobile DRAM, a dual data rate (DDR) DRAM, a low power DDR (DRAM) Lt; / RTI >

The memory cell array includes a plurality of memory cells, and may include first through fourth bank arrays 280a, 280b, 280c, and 280d. The row decoder includes first to fourth bank row decoders 260a, 260b, 260c and 260d connected to the first to fourth bank arrays 280a, 280b, 280c and 280d, The decoder includes first to fourth bank column decoders 270a, 270b, 270c and 270d connected to the first to fourth bank arrays 280a, 280b, 280c and 280d, respectively, The first to fourth bank sense amplifiers 285a, 285b, 285c, and 285d connected to the fourth bank arrays 280a, 280b, 280c, and 280d, respectively. The first to fourth bank arrays 280a to 280d and the first to fourth bank sense amplifiers 285a to 285d and the first to fourth bank row decoders 260a and 260b , 260c and 260d and the first to fourth bank column decoders 270a, 270b, 270c and 270d may constitute first to fourth banks, respectively. Although an example of a memory device 200 including four banks is shown in Figure 3, depending on the embodiment, the memory device 200 may include any number of banks.

The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDR from a memory controller (for example, 100 in FIG. 14). The address register 220 provides the received bank address BANK_ADDR to the bank control logic 230 and provides the received row address ROW_ADDR to the row address multiplexer 240 and stores the received column address COLADDR To the column address latch 250.

The bank control logic 230 may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, a bank row decoder corresponding to the bank address (BANK_ADDR) of the first to fourth bank row decoders 260a, 260b, 260c and 260d is activated, and the first to fourth bank columns A bank column decoder corresponding to the bank address BANK_ADDR of the decoders 270a, 270b, 270c, and 270d may be activated.

The refresh control circuit 215 can generate the refresh address REF_ADDR when the refresh command is received or when the self-refresh mode is entered. For example, the refresh control circuit 215 may include a refresh counter that sequentially changes the refresh address REF_ADDR from the first address to the last address of the memory cell array.

The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and receive the refresh address REF_ADDR from the refresh control circuit 215. [ The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh address REF_ADDR. The row address output from the row address multiplexer 240 may be applied to the first through fourth bank row decoders 260a, 260b, 260c, and 260d, respectively.

The bank row decoder activated by the bank control logic 230 among the first to fourth bank row decoders 260a, 260b, 260c and 260d decodes the row address output from the row address multiplexer 240, Lt; RTI ID = 0.0 > wordline < / RTI > For example, the activated bank row decoder may apply a word line drive voltage to a word line corresponding to a row address.

The column address latch 250 may receive the column address COL_ADDR from the address register 220 and temporarily store the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored column address COL_ADDR to the first to fourth bank column decoders 270a, 270b, 270c, and 270d, respectively.

The bank column decoder activated by the bank control logic 230 among the first to fourth bank column decoders 270a to 270d outputs the bank address BANK_ADDR and the column address COL_ADDR) can be activated.

The input / output gating circuit 290 includes circuits for gating the input / output data, and includes input data mask logic, a read data latch for storing data output from the first to fourth bank arrays 280a, 280b, 280c, And write drivers for writing data to the first to fourth bank arrays 280a, 280b, 280c, and 280d.

Data DAT read out from one of the bank arrays 280a, 280b, 280c and 280d is sensed by a sense amplifier corresponding to the one bank array, and the read data latches Lt; / RTI > The data (DAT) stored in the read data latches may be provided to the memory controller via the data input / output buffer 295. Data DAT to be written to one bank array of the first to fourth bank arrays 280a, 280b, 280c and 280d may be provided to the data input / output buffer 295 from the memory controller. The data DAT provided to the data input / output buffer 295 may be written to the one bank array through the write drivers.

The control logic 210 may control the operation of the memory device 200. For example, control logic 210 may generate control signals such that memory device 200 performs a write or read operation. The control logic 210 may include a command decoder 211 for decoding the command CMD received from the memory controller and a mode register 212 for setting the operation mode of the memory device 200. [ For example, the command decoder 211 decodes the write enable signal / WE, the row address strobe signal / RAS, the column address strobe signal / CAS, the chip select signal / CS, (CMD). ≪ / RTI > In addition, the control logic 210 may further receive a clock signal CLK and a clock enable signal / CKE for driving the memory device 200 in a synchronous manner.

The first voltage controller 310 may generate the first voltage control signal VC1 for adjusting the level of the first driving voltage VPP based on the first control signal NS and the second control signal DS have. The second voltage controller 330 may generate the second voltage control signal VC2 for adjusting the level of the second driving voltage VBB based on the first control signal NS and the second control signal DS have.

The first voltage generator 320 may generate the first driving voltage VPP based on the power supply voltage VDD and the first voltage control signal VC1. For example, as described above with reference to FIG. 1, the first voltage generator 320 may adjust the level of the first driving voltage VPP according to the operation mode based on the first voltage control signal VC1. The first driving voltage VPP may be a boosted voltage having a level higher than the power supply voltage VDD.

The second voltage generator 340 may generate the second driving voltage VBB based on the power supply voltage VDD and the second voltage control signal VC2. For example, as described above with reference to FIG. 1, the second voltage generator 340 may adjust the level of the second driving voltage VBB according to the operation mode based on the second voltage control signal VC2. The second driving voltage VBB may be a negative voltage having a level lower than the ground voltage.

In one embodiment, the first voltage generator 320 and the second voltage generator 340 may each be implemented with a charge pump.

The plurality of memory cells included in the memory cell array may operate based on the first driving voltage VPP and the second driving voltage VBB. Although not shown, the first driving voltage VPP may be provided to the row decoder.

Although the level changing and restoring operations described above with reference to FIG. 1 are performed for both the first driving voltage VPP and the second driving voltage VBB in FIG. 3, the first driving voltage VPP and the second driving voltage VBB The present invention may be applied to only one of the second driving voltages VBB. For example, the level change and restoration operations described above may be performed only for the first drive voltage VPP, in which case the second voltage controller 330 of FIG. 3 may be omitted. In another example, the level change and restoration operations described above may be performed only for the second drive voltage VBB, in which case the first voltage controller 310 of FIG. 3 may be omitted.

Although only one step-up voltage (i.e., VPP) and one negative voltage (i.e., VBB) are shown in FIG. 3, two or more step-up voltages and / or two or more negative voltages may be provided in the memory cell array . For example, a first negative voltage (e.g., VBB1) and a second negative voltage (e.g., VBB2) higher than the first negative voltage may be provided to the memory cell array, 200 may include a voltage controller and a voltage generator for each of the first and second negative voltages.

4 is a circuit diagram showing an example of a voltage controller included in the memory device of FIG.

Referring to FIGS. 3 and 4, the first voltage controller 310 included in the memory device 200 may include a first circuit portion 312 and a second circuit portion 314.

The first circuit portion 312 may be connected to the first node N1, which receives the reference voltage VREF, and the second node N2. The first circuit portion 312 may include transistors MP1, MP2, MN1, MN2, MN3.

The transistor MP1 may include a gate electrode connected between the power supply voltage VDD and the third node N3 and connected to the third node N3. The transistor MP2 is connected between the power supply voltage VDD and the fourth node N4 and may include a gate electrode. The gate electrodes of the transistors MP1 and MP2 may be connected to each other. The transistor MN1 may include a gate electrode connected between the third node N3 and the fifth node N5 and connected to the first node N1. The transistor MN2 may include a gate electrode connected between the fourth node N4 and the fifth node N5 and connected to the second node N2. The transistor MN3 may be connected between the fifth node N5 and the ground voltage VSS and may include a gate electrode receiving the voltage VA.

The second circuit portion 314 is connected to a second node N2 and an output node NO which outputs a first voltage control signal VC1 and outputs a first control signal NS and a second control signal DS, Lt; / RTI > The second circuit portion 314 may include resistors R1, R2, R3, R4 and transistors MN4, MN5.

The resistor R1 may be connected between the output node NO and the second node N2. The resistor R3 may be connected in parallel with the resistor R1 between the output node NO and the second node N2. The resistor R2 and the transistor MN4 may be connected in series between the second node N2 and the ground voltage VSS. That is, the resistor R2 may be connected to the second node N2. The transistor MN4 may be connected between the resistor R2 and the ground voltage VSS and may include a gate electrode receiving the first control signal NS. The resistor R4 and the transistor MN5 may be connected in series between the second node N2 and the ground voltage VSS and may be connected in parallel with the resistor R2 and the transistor MN4. That is, the resistor R4 may be connected to the second node N2. The transistor MN5 may be connected between the resistor R4 and the ground voltage VSS and may include a gate electrode for receiving the second control signal DS.

In one embodiment, the resistance value of the resistors R1, R2, R3, and R4 may be set according to the target level of the first driving voltage VPP to be changed, which will be described later.

4, the transistors MP1 and MP2 are PMOS (p-type metal oxide semiconductor) transistors and the transistors MN1, MN2, MN3, MN4, and MN5 are NMOS oxide semiconductor transistor. In other embodiments, although not shown, the types of transistors MP1, MP2, MN1, MN2, MN3, MN4, MN5 may be varied.

Although not shown, the second voltage controller 330 may have substantially the same structure as that of the first voltage controller 310. However, according to the target level of the second driving voltage VBB, The resistance value of the resistors included in the controller 330 may be different from the resistance value of the resistors R1, R2, R3, and R4 included in the first voltage controller 310. [

5 is a timing chart for explaining the operation of the voltage controller of FIG.

2, 3, 4 and 5, when the operating state ST of the memory device 200, that is, when the operation mode is the normal mode NM, the first control signal NS has a logic high level The second control signal DS has a logic low level. The transistor MN4 is turned on and the transistor MN5 is turned off so that the first voltage control signal VC1 is generated based on the resistors R1 and R2.

At time t DSME, the memory device 200 enters a second self-refresh mode (DSM), wherein the first control signal NS transitions from the logic high level to the logic low level, Is transited from the logic low level to the logic high level. In the second self-refresh mode DSM, the transistor MN4 is turned off, the transistor MN5 is turned on, and the first voltage control signal VC1 is generated based on the resistors R3 and R4. Therefore, when compared with the normal mode NM, the levels of the driving voltages VPP and VBB are changed.

At a time t DSMX, the second self-refresh mode DSM is terminated and the first control signal NS transitions from the logic low level to the logic high level and the second control signal DS is at the logic high level And transitions to the logic low level. In other words, the second control signal DS is activated only in the second self-refresh mode DSM, and the first control signal NS that is complementarily operated is deactivated only in the second self-refresh mode DSM.

However, as described above with reference to FIG. 2, when the second self-refresh mode DSM ends, the memory device 200 can not immediately enter the normal mode NM and the self-refresh power down mode SRPD ) And the first self-refresh mode (SR), and enters the normal mode (NM). For example, at time tDSMX, the second self-refresh mode DSM is terminated and the memory device 200 enters the self-refresh power down mode SRPD and the self-refresh power down mode SRPD is terminated at time tPDX The memory device 200 enters the first self-refresh mode SR and the first self-refresh mode SR is terminated at time tSRX and the memory device 200 enters the normal mode NM. The time period from the time t DSMX to the time t SRX may be the time required to return from the second self-refresh mode DSM to the normal mode NM, for example, it may be longer than about 200 us. The levels of the driving voltages VPP and VBB are restored in the period from the time tDSMX to the time tSRX.

6A and 6B are graphs for explaining an example of a level change of the driving voltage according to the embodiments of the present invention.

1, 2, 3, 4 and 6a, the memory device 200 generates and supplies a first driving voltage VPP having a first level VPNL1 in the normal mode NM to the memory cells (Step S100), the level of the first driving voltage VPP is maintained at the first level (VPNL1) in the first self-refresh mode SR and provided to the memory cells (step S200), and the second self- DSM), the level of the first driving voltage VPP is changed to a second level (VPDL1) lower than the first level (VPNL1) based on the first voltage control signal (VC1) and supplied to the memory cells (Step S300). When the second self-refresh mode DSM ends, the level of the first driving voltage VPP may be restored to the first level VPNL1 before entering the normal mode NM Step S400). For example, the first level (VPNL1) may be about 3.4V, and the second level (VPDL1) may be about 3.0V. The first level VPNL1 and the second level VPDL1 may be at a fixed level regardless of the operating temperature TEMP of the memory device 200. [

In one embodiment, to generate a first voltage control signal VC1 for decreasing the level of the first driving voltage VPP in the second self-refresh mode DSM as shown in Figure 6A, The resistance value of the second resistor R2 is smaller than the resistance value of the third resistor R3 (i.e., R1> R3), and the resistance value of the second resistor R2 is less than the resistance value of the fourth resistor R4 The value obtained by dividing the resistance value of the second resistor R2 by the resistance value of the first resistor R1 is a value obtained by dividing the resistance value of the fourth resistor R4 by the resistance value of the third resistor R3 (I.e., R2 / R1 < R4 / R3).

Referring to FIGS. 2, 6A and 6B, the self refresh current IDD6 is a normal refresh mode in which the first drive voltage VPP is in the normal mode NM having the first level VPNL1 and in the first self refresh mode SR, The first driving voltage VPP may have a value INL1 and a second value IDL1 lower than the first value INL1 in the second self refresh mode DSM having the second level VPDL1 . Since the self refresh current IDD6 is reduced in the second self refresh mode DSM, the power consumption of the memory device 200 can be reduced.

FIG. 7 is a graph for explaining an example of characteristic compensation of the self-refresh operation according to the embodiments of the present invention.

7, WL and BL denote the voltage changes of the word line and bit line connected to the memory cell in the self-refresh operation, respectively, and the solid and dotted lines indicate the first self-refresh mode SR and the second self- DSM represent voltage changes of the word line and the bit line according to the self-refresh operation, respectively.

1, 2, 3, 6A and 7, when the self-refresh operation is started in the first self-refresh mode SR, the first drive voltage VPP is applied to the word line WL, The voltage of the word line WL increases to the first level (VPNL1) as shown by the dotted line. At this time, the bit line BL is precharged and a charge sharing operation is started at a time tCSS. At the time tCSE1, the sense amplifier section is activated, the charge sharing operation is ended as shown by a dotted line, and an amplifying operation for preserving data of the memory cell is performed. At a time tRAS1 when a sufficient time has elapsed from the time tCSE1, the sense amplifier section is deactivated and the bit line BL is precharged again as shown by the dotted line.

In the method of driving the memory device 200 according to the embodiments of the present invention, in order to guarantee or compensate the characteristics of the self-refresh operation in the second self-refresh mode (DSM), the level of the first drive voltage VPP The execution time of the self-refresh operation can be adaptively adjusted according to the self-refresh operation.

In one embodiment, by changing the ending time of the charge sharing operation performed on the bit line (BL) during the self refresh operation in the second self refresh mode (DSM), the execution time of the self refresh operation Can be adaptively adjusted. 7, the ending point of the charge-sharing operation in the first self-refresh mode SR is the time tCSE1, but the charge in the second self-refresh mode (DSM) The ending point of the sharing operation may be time tCSE2, which is later than time tCSE1. In other words, in the second self-refresh mode (DSM), the execution time of the charge-sharing operation for performing the self-refresh operation may increase, and when the sense amplifier section is activated to perform the self- Can be delayed.

In another embodiment, by changing the start point of the precharge operation performed on the bit line (BL) after the self refresh operation is performed in the second self refresh mode (DSM), the execution of the self refresh operation Time can be adjusted adaptively. 7, the start time of the pre-charge operation in the first self-refresh mode SR is time tRAS1, but the start time of the pre-charge operation in the second self-refresh mode (DSM) The start time of the charge operation may be time tRAS2 later than time tRAS1. In other words, in the second self-refresh mode (DSM), the time at which the sense amplifier unit is activated to perform the self-refresh operation, that is, the driving time of the sense amplifier unit may increase. To terminate the self- The time point at which the sense amplifier section is inactivated may be delayed.

In summary, when the self-refresh operation is started in the second self-refresh mode (DSM), the first reduced level drive voltage VPP is applied to the word line WL, WL increases to the second level VPDL1. At this time, the bit line BL is precharged, and the charge sharing operation is started at time tCSS. At a time tCSE2 later than the time tCSE1, the sense amplifier section is activated, the charge sharing operation is ended as shown by a solid line, and an amplifying operation for preserving data of the memory cell is performed. At a time tRAS2 later than the time tRAS1, the sense amplifier section is deactivated and the bit line BL is precharged again as shown by the solid line.

In FIG. 7, in order to guarantee or compensate the characteristics of the self-refresh operation, the end point of the charge-sharing operation and the start point of the pre-charge operation are all changed in the second self-refresh mode (DSM) It is possible to change only the end point of the charge sharing operation in the second self refresh mode (DSM) or only the start point of the precharge operation according to the embodiment.

8A, 8B and 8C are graphs for explaining another example for the characteristic compensation of the self-refresh operation according to the embodiments of the present invention.

8A, 8B and 8C, a logic high level indicates a period during which the self refresh operation is performed, and a logic low level indicates a period during which the self refresh operation is not performed.

Referring to FIGS. 1, 2, 3 and 8a, the memory device 200 may repeatedly perform the self-refresh operation in every second period PSR1 in the second self-refresh mode DSM. The first period PSR1 may be substantially the same as the period of the self-refresh operation in the first self-refresh mode SR.

Referring to Figures 1, 2, 3, 8b and 8c, the memory device 200 has a first drive voltage VPP to guarantee or compensate for the characteristics of the self-refresh operation in the second self-refresh mode DSM. The cycle of the self-refresh operation can be adaptively adjusted according to the level change.

In one embodiment, as shown in FIG. 8B, the memory device 200 repeatedly performs the self-refresh operation every second period (PSR2) shorter than the first period (PSR1) in the second self-refresh mode (DSM) can do. In other words, in the second self-refresh mode (DSM), the period of the self-refresh operation can be reduced.

8C, the memory device 200 repeatedly performs the self-refresh operation every third period (PSR3) longer than the first period (PSR1) in the second self-refresh mode (DSM) can do. In other words, in the second self-refresh mode (DSM), the period of the self-refresh operation can be increased.

In another embodiment, although not shown, the cycle of the self-refresh operation may be adaptively adjusted within the same second self-refresh mode (DSM).

9 is a graph for explaining another example of the level change of the driving voltage according to the embodiments of the present invention.

1, 2, 3 and 9, the memory device 200 generates and supplies a second driving voltage VBB having a third level VBNL1 in the normal mode NM to the memory cells The second level of the second driving voltage VBB is maintained at the third level VBNL1 in the first self-refresh mode SR to provide the level of the second driving voltage VBB to the memory cells in the second self- The level of the second driving voltage VBB is changed to a fourth level VBDL1 higher than the third level VBNL1 and is provided to the memory cells in step S300. In the second self refresh mode DSM The level of the second driving voltage VBB may be restored to the third level VBNL1 before the normal mode NM is entered (step S400). The third level VBNL1 and the fourth level VBDL1 may be a constant fixed level regardless of the operating temperature TEMP of the memory device 200. [ According to the above-described level change of the second driving voltage VBB, the self refresh current IDD6 can be reduced in the second self-refresh mode DSM as described above with reference to Fig. 6B.

In one embodiment, to generate the second voltage control signal VC2 for increasing the level of the second driving voltage VBB in the second self-refresh mode DSM as shown in Fig. 9, The resistance value of the resistors included in the first voltage controller 330 may be set different from the resistance values of the resistors R1, R2, R3, and R4 included in the first voltage controller 310. [

10 is a flowchart showing a method of driving a memory device according to embodiments of the present invention.

Referring to FIGS. 2 and 10, in a method of driving a memory device according to embodiments of the present invention, in a normal mode NM, a driving voltage is generated and provided to a plurality of memory cells included in the memory device S1100). At this time, the driving voltage has a variable level that varies depending on the operating temperature of the memory device.

In the case of entering the first self-refresh mode SR, the level of the driving voltage is changed and provided to the plurality of memory cells (step S1200). At this time, unlike in the normal mode NM, the driving voltage has a first fixed level which is constant regardless of the operating temperature. In addition, the level of the driving voltage may be changed in a direction to reduce power consumption of the memory device.

When entering the second self-refresh mode (DSM), the level of the driving voltage is changed and provided to the plurality of memory cells (step S300). At this time, the driving voltage has a second fixed level that is constant regardless of the operating temperature, and the second fixed level is different from the first fixed level. Further, the level of the driving voltage may be changed in a direction further reducing the power consumption of the memory device.

In the case where the first self-refresh mode SR or the second self-refresh mode DSM is terminated, the level of the driving voltage may be restored (step S1400). For example, when the first self-refresh mode SR is terminated, the level of the drive voltage can be immediately restored to the variable level. Since it takes a longer time than the reference time to return to the normal mode NM after the second self refresh mode DSM is completed, the level of the driving voltage is set to the original level Mode (level in NM)).

Thus, in the normal mode (NM) after the first self-refresh mode (SR) or the second self-refresh mode (DSM) is terminated, the level-regulated drive voltage can be provided to the plurality of memory cells.

11 is a block diagram illustrating a memory device in accordance with embodiments of the present invention.

11, the memory device 200a includes a control logic 210, a refresh control circuit 215, an address register 220, a bank control logic 230, a row address multiplexer 240, a column address latch 250 A data input / output buffer 295, a first voltage controller 310, a first voltage generator 320a, a second voltage controller 320a, and a second voltage controller 330b. (330) and a second voltage generator (340a).

The memory device 200a of Figure 11 is similar to the memory device of Figure 3 except that the first and second voltage generators 320a and 340a each include NTCTs 322 and 342, May be substantially the same as the memory device 200, and duplicate descriptions are omitted.

The first voltage generator 320a activates the NTC element 322 in the normal mode NM to generate a first driving voltage VPP whose level changes according to the operating temperature, and the first and second self- It is possible to inactivate the NTC element 322 in the sustain period SR and DSM to generate the first drive voltage VPP having a constant level irrespective of the operation temperature. The first voltage generator 320a may generate the first driving voltage VPP so as to have different levels in the first and second self-refresh modes SR and DSM based on the first voltage control signal VC1. You can adjust the level.

The second voltage generator 340a activates the NTC element 342 in the normal mode NM to generate a second driving voltage VBB whose level changes according to the operating temperature, and the first and second self- The second driving voltage VBB having a constant level regardless of the operating temperature can be generated by inactivating the NTC device 342 in the first and second switching devices SR and DSM. Also, the second voltage generator 340a generates the second driving voltage VBB so as to have different levels in the first and second self-refresh modes SR and DSM based on the second voltage control signal VC2. You can adjust the level.

12A, 12B and 13 are graphs for explaining still another example of the level change of the driving voltage according to the embodiments of the present invention.

10, 11 and 12A, the memory device 200a activates the NTC element 322 in the normal mode NM to generate the first driving voltage VPP having the first variable level VPNL2, (Step S1100). In the case of entering the first self-refresh mode SR, the NTC element 322 is deactivated so that the level of the first driving voltage VPP is lower than the first variable level VPNL2 (Step S1200). In the case of entering the second self-refresh mode (DSM), the NTC element 322 is deactivated and the first voltage control signal (VPSL2) (VPL) to a second fixed level (VPDL2) lower than the first variable level (VPNL2) and the first fixed level (VPSL2) to the memory cells S1300), and when the first self-refresh mode SR or the second self-refresh mode DSM is terminated, The level of the voltage VPP can be restored (step S1400).

In one embodiment, when the first self-refresh mode SR ends, the NTC element 322 can be activated to immediately restore the level of the first drive voltage VPP to the first variable level VPNL2 . When the second self refresh mode DSM is terminated, before the NTC element 322 is activated and enters the normal mode NM based on the first voltage control signal VC1, Level to the first variable level (VPNL2).

As shown in Fig. 12A, the first variable level VPNL2 may decrease as the operating temperature increases. For example, if the operating temperature is about 25 degrees Celsius, the first variable level VPNL2 may be about 3.4V, the first fixed level VPSL2 may be about 3.2V, VPDL2) may be about 3.0V.

On the other hand, in order to ensure the characteristics of the self-refresh operation in the second self-refresh mode (DSM) when the level of the first drive voltage VPP is changed as shown in FIG. 12A, The operation of adaptively adjusting the execution time of the self-refresh operation and / or the operation of adaptively adjusting the period of the self-refresh operation described above with reference to FIGS. 8A, 8B and 8C may be additionally performed.

Referring to FIGS. 2, 12A and 12B, the self refresh current IDD6 has a first value INL2 in the normal mode NM in which the first driving voltage VPP has the first variable level VPNL2, 1 drive voltage VPP has a second value ISL2 that is lower than or equal to the first value INL2 in the first self refresh mode SR having the first fixed level VPSL2 and the first drive voltage VPP May have a third value IDL2 lower than the second value ISL2 in the second self-refresh mode DSM having the second fixed level VPDL2. The power consumption of the memory device 200a can be reduced since the self-refresh current IDD6 is reduced in the first self-refresh mode SR and the second self-refresh mode DSM.

10, 11 and 13, the memory device 200a activates the NTC element 342 in the normal mode NM to generate the second driving voltage VBB having the second variable level VBNL2, (Step S1100), and inactivates the NTC element 342 in the case of entering the second self-refresh mode (DSM) and applies the second driving voltage VBB to the memory cells based on the second voltage control signal VC2 Level to a third fixed level VBDL2 higher than the second variable level VBNL2 and provides the same to the memory cells in step S1300. When the second self-refresh mode DSM ends, VBB (step S1400). For example, in the case where the second self refresh mode DSM is terminated, before activating the NTC element 342 and entering the normal mode NM based on the second voltage control signal VC2, (VBB) to the second variable level (VBNL2). According to the above-described level change of the second driving voltage VBB, the self refresh current IDD6 can be reduced in the second self-refresh mode DSM as described above with reference to Fig. 12B.

12A, in the case of entering the first self-refresh mode SR, the NTC element 342 is deactivated so that the level of the second driving voltage VBB is lower than the second variable level VBNL2 The memory cell may be changed to a fourth fixed level, which is higher than or equal to the first fixed level, to be provided to the memory cells (step S1200). At this time, the fourth fixed level may be lower than the third fixed level VBDL2.

Steps S100, S200, S300, and S400 of FIG. 1 and steps S1100, S1200, S1300, and S1400 of FIG. 10 may be performed only for the first drive voltage VPP and may be performed for the second drive voltage VBB Or may be performed for both the first and second driving voltages VPP and VBB and may be performed for two or more step-up voltages and / or two or more negative voltages.

In the memory devices 200 and 200a and the driving method thereof according to the embodiments of the present invention, in the second self-refresh mode DSM in which the time required for returning to the normal mode NM is relatively long and self- , The level of the driving voltage provided to the memory cells can be changed to be different from that in the normal mode NM. For example, in the second self-refresh mode DSM, the level of the first driving voltage VPP higher than the power source voltage VDD can be reduced and the second driving voltage VBB lower than the ground voltage VSS, Can be increased. Further, the execution time of the self-refresh operation and / or the cycle of the self-refresh operation can be adaptively adjusted. Therefore, the self refresh current IDD6 can be reduced while the characteristics of the self refresh operation in the second self refresh mode (DSM) are ensured, and the power consumption of the memory devices 200 and 200a can be reduced.

On the other hand, the driving method according to the embodiments of the present invention may be implemented in the form of a product including computer readable program code stored in a computer-readable medium. The computer readable program code may be provided to a processor of various computers or other data processing apparatuses. The computer-readable medium may be a computer-readable signal medium or a computer-readable recording medium. The computer-readable recording medium may be any type of medium that can store or contain a program in or in communication with the instruction execution system, equipment, or device.

14 is a block diagram illustrating a memory system including a memory device in accordance with embodiments of the present invention.

Referring to FIG. 14, memory system 500 includes memory controller 100 and memory device 200.

The memory device 200 is controlled and accessed by the memory controller 100. For example, the memory controller 100 may write data to the memory device 200 or read data from the memory device 200 at the request of a host (not shown).

The memory controller 100 transmits the command CMD and the address ADDR to the memory device 200 via the control line and exchanges data DAT with the memory device 200 through the data input / Some or all of the control line and the data input / output line may be referred to as a channel.

Although not shown, the memory controller 100 controls the data strobe signal DQS, the chip enable signal / CE, the write enable signal / WE, the read enable signal / RE through the control line, A command latch enable signal CLE and an address latch enable signal ALE may be further transferred to the memory device 200 and the power supply voltage may be further supplied to the memory device 200 through the power supply line .

The memory device 200 may be a memory device according to embodiments of the present invention. The memory device 200 may perform a refresh operation to save the stored data based on the command CMD and perform a self refresh operation to save the stored data without an external command. Further, by changing the level of the driving voltage provided to the memory cells in the second self refresh mode (DSM) differently from that in the normal mode (NM), the power consumption can be reduced.

15 is a block diagram illustrating a computing system including a memory device in accordance with embodiments of the present invention.

15, a computing system 1300 includes a processor 1310, a system controller 1320, and a memory system 1330. The computing system 1300 may further include an input device 1350, an output device 1360, and a storage device 1370.

Memory system 1330 includes a plurality of memory devices 1334 and a memory controller 1332 for controlling memory devices 1334. The memory controller 1332 may be included in the system controller 1320. Memory devices 1334, memory controller 1332, and memory system 1330 may operate in accordance with embodiments of the present invention.

Processor 1310 may execute certain calculations or tasks. Processor 1310 may be coupled to system controller 1320 via a processor bus. The system controller 1320 may be coupled to the input device 1350, the output device 1360, and the storage device 1370 via an expansion bus. Accordingly, the processor 1310 can control the input device 1350, the output device 1360, or the storage device 1370 through the system controller 1320.

The present invention can be applied to semiconductor memory devices and various devices and systems including the same. For example, the present invention may be applied to a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer such as a television, a set-top box, a music player, a portable game console, a navigation system, a smart card, a printer, a wearable system, an Internet of things (IOT) system, a virtual reality (VR) system and an augmented reality Lt; / RTI &gt;

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. It will be understood.

Claims (10)

A first self refresh mode for performing a self refresh operation for saving data stored in memory cells without a normal mode and an external command and a time required for returning to the normal mode is shorter than a reference time, And a second self-refresh mode in which a time required to return to the normal mode is longer than the reference time,
Generating, in the normal mode, a first drive voltage having a first level and providing the first drive voltage to the memory cells; And
And changing the level of the first driving voltage to a second level lower than the first level in the case of entering the second self-refresh mode, to the memory cells. The method according to claim 1,
Restoring the level of the first driving voltage to the first level before entering the normal mode when the second self-refresh mode is ended; And
And providing the first drive voltage having the first level to the memory cells in the normal mode after the second self-refresh mode. The method according to claim 1,
Wherein the first driving voltage is a boost voltage generated based on a power supply voltage and having a level higher than the power supply voltage. The method according to claim 1,
And adjusting the execution time of the self-refresh operation in accordance with the level change of the first driving voltage in the second self-refresh mode. 5. The method of claim 4, wherein adaptively adjusting the execution time of the self-
And changing an end timing of a charge sharing operation performed on bit lines connected to the memory cells during the self refresh operation in the second self refresh mode. A method of driving a device. 5. The method of claim 4, wherein adaptively adjusting the execution time of the self-
And changing a start time of a precharge operation performed on bit lines connected to the memory cells after the self refresh operation is performed in the second self refresh mode. A method of driving a device. The method according to claim 1,
And adjusting the period of the self-refresh operation adaptively according to a level change of the first driving voltage in the second self-refresh mode. The method according to claim 1,
In the normal mode, generating and providing a second driving voltage having a third level to the memory cells; And
Further comprising changing the level of the second driving voltage to a fourth level higher than the third level and providing the second driving voltage to the memory cells when entering the second self refresh mode Driving method. A first self refresh mode for performing a self refresh operation for saving data stored in memory cells without a normal mode and an external command and a time required for returning to the normal mode is shorter than a reference time, And a second self-refresh mode in which a time required to return to the normal mode is longer than the reference time,
Generating and supplying to the memory cells a first driving voltage having a first variable level that varies according to an operating temperature of the memory device in the normal mode;
Changing the level of the first driving voltage to a first fixed level that is constant regardless of the operating temperature and providing the level of the first driving voltage to the memory cells when entering the first self-refresh mode; And
When the memory cell enters the second self-refresh mode, changes the level of the first driving voltage to a second fixed level lower than the first variable level and the first fixed level and constant regardless of the operating temperature, To the memory device. A memory cell array including a plurality of memory cells operating based on a first driving voltage;
A first voltage controller for generating a first voltage control signal for adjusting a level of the first driving voltage based on a first control signal and a second control signal; And
Wherein the control circuit generates the first driving voltage based on the power supply voltage and the first voltage control signal, sets the level of the first driving voltage to a first level in a normal mode, and stores data stored in the memory cells without an external command Refreshing operation in which the time required for returning to the normal mode is shorter than the reference time, the level of the first driving voltage is set to the second level in the first self-refresh mode, and the self- Refresh mode in which the time required for returning to the normal mode is longer than the reference time, and a first voltage that sets the level of the first driving voltage to a third level lower than the first level and the second level in a second self- Lt; / RTI &gt;

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