JP2009009664A - Circuit for optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of detecting a DC component of a reproduced signal in areas having different characteristics in a medium even if phases of the reproduced signal and a reproduced clock are different from each other during reproduction of a DVD-RAM disk or the like in the circuit of the optical disk device. <P>SOLUTION: The circuit (LSI100) of the optical disk device for reproducing a disk 1 is provided with an A/D converter 9 for performing A/D conversion by a predetermined reproduced clock, first and second DC detection circuits 17a and 17b for detecting the DC component (DC) of an A/D converted (and waveform-equalized) reproduced signal, first and second DC elimination circuits 13a and 13b for eliminating the detected DC, and switches 12a to 12d for switching control. The circuit detects and eliminates, through switching control, the DC of the reproduced signal even if the phase relation of the reproduced signal and the reproduced clock varies. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a circuit used in an optical disc apparatus for optically reproducing or recording / reproducing a signal from a disc (recording medium), and more particularly to removal of a DC component of a reproduced signal.

  An optical disc apparatus has a technique for removing a direct current component (referred to as DC) of a reproduction signal, in particular, a technique for detecting a ratio of asymmetry (a fluctuation ratio from a center level).

For example, in Japanese Patent Laid-Open No. 2005-190618 (Patent Document 1), “optimizing signal processing by using a signal reproduced from a disk and detecting a ratio of asymmetry from a reproduction signal processing system, An information reproducing apparatus that can easily estimate the asymmetry ratio and can reproduce a disk having a large asymmetry even when the adaptive equalization process and the maximum likelihood decoding method are used is described.
JP 2005-190618 A

  In the technique such as Patent Document 1, the fluctuation ratio (asymmetry) from the center level is determined by the relationship between the phase error integration output of the PLL and the phase error threshold or the relationship between the adaptive equalization error integration output and the equalization error threshold. ), And a means for eliminating the fluctuation of the sampling timing from the center level of the readout signal. However, with such means, it is necessary to read the recorded information on the medium for a certain period.

  For example, the DVD-RAM disk 50 (partial cross section) and its format shown in FIGS. 7A and 7B have the following problems. The DVD-RAM disk 50 has a recording field 51 made of a phase change recording film and a header field 52 made of an emboss pit 54 in which a physical ID is embedded (preformatted). And a mirror area (Mirror (MIRR) field) 53 are mixed. Further, in this header area 52, the emboss pits 54 are arranged slightly shifted in the track direction in order to give addresses to both areas called a land 55 and a groove 56. As in the format shown in FIG. 7B, in the DVD-RAM, one sector is 2697 bytes, the recording area 51 is 2567 bytes, the header area 52 is 128 bytes, and the mirror area 53 is 2 bytes. As can be seen, the header area 52 is about 20 times shorter than the recording area 51.

  When reproducing media such as those described above, fluctuations from the center level in the header area with a short area (length) (DC component of the reproduction signal) are removed, especially due to the influence of each area with different characteristics. There was a problem that it was not possible. Also, if the follow-up speed of the adaptive equalization means is increased in order to detect fluctuations in the short header area, sudden fluctuations are detected in the recording area, and the fluctuation ratio from the center level can be correctly determined. There was a problem that it was not possible.

  Conventionally, since there is only one DC detection circuit, there is a problem that it is not possible to cope with a phase shift between a reproduction signal and a reproduction clock due to, for example, waveform equalization in the apparatus or a configuration such as a PLL.

  The present invention has been made in view of the above problems. A first object of the present invention is to provide an optical disk device such as a DVD-RAM disk having a plurality of characteristics such as a recording area and a header area. When reproducing a recording medium having different areas), the variation from the center level of the independent read signals for the areas having different characteristics (recording area, header area) on the medium (DC component of the reproduction signal) ) Can be detected in the respective regions even if the phases of the reproduced signal and the reproduced clock are different. Further, the second object is that the DC component of the reproduction signal can be removed in each area without being affected by each of the above areas. For example, the reproduction performance of the recording area and the ID area acquisition rate ( It is to provide a technique capable of improving the reading rate.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. In order to achieve the above-mentioned object, the present invention comprises an optical disk apparatus and a circuit (IC) for optically reproducing or recording / reproducing information on / from a disk, which includes a pickup (optical pickup) for focusing a laser beam on the disk. Etc.) and has the following structure.

  This circuit is obtained by means of analog-to-digital (A / D conversion) conversion of analog input signals read from a disk through a pickup through a predetermined clock (reproduced clock) (A / D conversion means) and A / D conversion. Means (phase synchronization means) for synchronizing the data signal (reproduction signal) and the A / D conversion sampling clock (reproduction clock) from the received signal (digital reproduction signal), and the signal obtained by A / D conversion Means for equalizing the waveform (waveform equalizing means), and one or more means (DC removing means) for removing the DC component (DC) of the signal obtained by A / D conversion (the signal obtained by equalizing the waveform) ) And the first switching means (switch) for switching the DC removal means when there are two or more, and the DC component (D of the signal obtained by equalizing the waveform) obtained by A / D conversion (D 2) (first and second) or more means (DC detection means) for detecting), second switching means (switch) for switching between two or more DC detection means, and DC removal means removed DC component Means for maximum likelihood decoding of a signal (maximum likelihood decoding means), and the phase relationship between the signal (reproduction signal, input of phase synchronization means) and the clock (reproduction clock, output of phase synchronization means) is different Even in such a case, the DC component of the reproduction signal is appropriately detected and removed with an appropriate time constant by switching control (selection of a circuit to be used) according to the phase relationship.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. According to the present invention, a first effect is that when a circuit in an optical disc apparatus reproduces an optical disc such as a DVD-RAM disc (a recording medium having a plurality of areas having different characteristics such as a recording area and a header area). In addition, fluctuations (DC component of the reproduction signal) from the center level of independent read signals for areas having different characteristics (recording area, header area) on the medium are different in phase between the reproduction signal and the reproduction clock. Even if it is, it can detect in each area | region. Further, the second effect is that the direct current component of the reproduction signal can be removed in each area without being affected by each of the above areas. For example, the reproduction performance of the recording area and the ID area acquisition rate ( Reading rate).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  The optical disk device and its circuit (LSI 100) according to the embodiment of the present invention will be described with reference to FIGS. In the present embodiment, two DC detection circuits (17a, 17b) corresponding to two DC removal circuits (13a, 13b) with appropriate different time constants are provided, and a reproduction signal from the PLL circuit 10 is controlled by switching control. Even when the phase relationship of the recovered clock is different, the DC component (DC) of the recovered signal is detected and removed with an appropriate time constant (FIG. 1, etc.).

<Optical disk device>
FIG. 1 shows the configuration of the optical disc apparatus. This apparatus performs information / data reproduction or recording / reproduction with respect to a set disc (optical disc) 1. The apparatus includes a clamper 2a, a turntable 2b, an objective lens 3, a pickup (optical pickup) 4, a thread motor 5, a spindle motor 6, a signal processing circuit 7, and an LSI 100. The range of the LSI 100 is an example of mounting.

  The LSI 100 includes a servo circuit 8, an A / D converter 9, a phase synchronization circuit (PLL (Phase-Looked loop) circuit) 10, a waveform equalization circuit 11, switches (switches a to d) 12a, 12b, 12c, 12d, first direct current component (DC) removal circuit (# 1) 13a, second direct current component (DC) removal circuit (# 2) 13b, maximum likelihood decoding circuit 15, demodulation / error correction circuit 16, first It has a DC component (DC) detection circuit (# 1) 17a and a second DC component (DC) detection circuit (# 2) 17b.

  The time constant 14a and the time constant 14b are set for the corresponding DC removal circuit (# 1) 13a and DC removal circuit (# 2) 13b. The switching signal # 1 is supplied to the switches 12a and 12b. The switching signal # 2 is supplied to the switch 12d. The ON / OFF signal is supplied to the switch 12c. The switching signals # 1 and # 2 and the ON / OFF signal are controlled and supplied from, for example, an upper microcomputer for the LSI 100 (or may be supplied from another circuit).

  The disc 1 to be reproduced includes a DVD-RAM disc 50 as shown in FIG. 7, for example. The DC removal circuit (13a, 13b) and the DC detection circuit (17a, 17b) have a configuration corresponding to the disk 1.

<Overview of operation>
The outline of the operation of this apparatus is as follows. The disc 1 set on the turntable 2b is fixed to the turntable 2b by a clamper 2a. As the spindle motor 6 rotates, the disk 1 rotates. The disk 4 is irradiated with laser light from the pickup 4 and the light reflected by the disk 1 is detected by the pickup 4. From the detected signal (analog input signal), in the signal processing circuit 7, position information regarding the position where the objective lens 3 is moving in the focus direction (perpendicular to the disc 1) and tracking direction (parallel to the disc 1 and radial direction). A signal is generated and supplied to the servo circuit 8. The servo circuit 8 performs feedback control using a delay compensator, a lead compensator, etc., and generates a control signal for moving the objective lens 3 in the focus direction and the tracking direction. By this control signal, the objective lens 3 is controlled in the focus direction, the feedback loop focus control is realized, and the state of being always in focus is maintained. In addition, the objective lens 3 is also controlled in the tracking direction by this control signal, and tracking control of the feedback loop is realized, and the on-track state always on the pit on the recording surface of the disk 1 is maintained.

  The servo circuit 8 performs feedback control using a delay compensator or a lead compensator from the tracking control state, and generates a control signal for controlling the sled motor 5 in accordance with the shift of the objective lens 3 in the tracking direction. Then, the sled motor 5 is operated to move the pickup 4 itself. Further, the signal processing circuit 7 performs feedback control using the rotation cycle information read from the disk 1 and generates a signal for controlling the spindle motor 6 by the servo circuit 8 based on the rotation cycle information, and the spindle motor. 6 is operated. The above is the playback state in which the objective lens 3 is in the in-focus position and in the on-track position and the focus, tracking, spindle, and thread are controlled in the steady state. A signal from the signal read by the pickup 4 to a signal output from the demodulation / error correction circuit 16 is referred to as a reproduction signal.

  At this time, the pickup 4 irradiates the disk 1 with laser light, detects the amount of reflected light or deflection thereof, and reads information on the disk 1. The reproduction signal read by the pickup 4 is supplied to the signal processing circuit 7. The signal processing circuit 7 adjusts and outputs the amplitude level and frequency characteristics of the supplied reproduction signal. The adjusted reproduction signal is supplied to the A / D converter 9, and the A / D converter 9 converts the analog signal into a digital signal. The A / D converted playback signal is input to the PLL circuit 10. Then, the phase of the reproduction clock (A / D conversion sampling clock) generated and output in the PLL circuit 10 is synchronized with the inputted reproduction signal.

<PLL circuit>
FIG. 2 shows an example of the PLL circuit 10. The PLL circuit 10 includes a phase error detection circuit 20, a loop filter 21, and a voltage controlled oscillator 22 (Voltage Controlled Oscillator: VCO). The phase error detection circuit 20 receives a reproduction signal, detects a difference between signal values before and after the zero cross point between the reproduction clock generated by the VCO 22 and the inputted reproduction signal as a phase error, and supplies it to the loop filter 21. The loop filter 21 adjusts the gain of the input phase error signal and supplies the phase error signal with the adjusted gain to the VCO 22. The VCO 22 oscillates a clock corresponding to the value of the phase error signal, and generates and outputs it as a recovered clock. With the configuration of the PLL circuit 10 described above, the phase of the recovered clock can be synchronized with the input recovered signal.

  The recovered clock output from the PLL circuit 10 is supplied to the waveform equalization circuit 11, the maximum likelihood decoding circuit 15, the DC removal circuits (13a, 13b), the DC detection circuits (17a, 17b), and the like.

<DC detection and DC removal, etc.>
On the other hand, the A / D converted reproduction signal is supplied to a waveform equalization circuit 11, which adjusts the amplitude level and frequency characteristics to equalize the waveform of the reproduction signal. The waveform-equalized signal is supplied to the switch 12c before the maximum likelihood decoding circuit 15, and is also supplied to the first DC removal circuit (# 1) 13a and the second DC removal circuit (# 2) 13b. Is done. On the other hand, the waveform equalized signal is also supplied to the first DC detection circuit (# 1) 17a and the second DC detection circuit (# 2) 17b. The first and second DC detection circuits 17a and 17b each detect a direct current component (DC) of the supplied signal. The DC component signals detected by the first and second DC detection circuits 17a and 17b are supplied to the switch 12d. One of the DC signals supplied to the switch 12d is selected by the switching signal # 2 and supplied to the next switch 12a. In the switch 12d, for example, when the switching signal # 2 is “LOW”, the H side (lower second DC detection side) is selected, and when it is “HIGH”, the G side (upper first DC detection side). ) Is selected.

  One of the signals (DC signal) supplied to the switch 12a before the DC removal circuit (13a, 13b) is selected by the switching signal # 1, and the first DC removal circuit (# 1) 13a or second signal is selected. To the DC removal circuit (# 2) 13b. In the switch 12a, for example, when the switching signal # 1 is “LOW”, the A side (upper first DC removal side) is selected, and when it is “HIGH”, the B side (lower second DC removal side). ) Is selected.

  The first and second DC removal circuits 13a and 13b remove the detected direct current component (DC) from the supplied waveform equalized signal (reproduced signal), and each signal is sent to the next switch 12b. Supplied. Each of the signals supplied to the switch 12b is selected and output by the switching signal # 1. In the switch 12b, for example, when the switching signal # 1 is “LOW”, the C side (upper first DC removal side) is selected, and when it is “HIGH”, the D side (lower second DC removal side). ) Is selected.

  The signal output from the switch 12b is supplied to the switch 12c. One of the output signal (E side terminal) and the output signal (F side terminal) from the waveform equalization circuit 11 supplied to the switch 12c is selected and output by the ON / OFF signal. . In the switch 12c, for example, when the ON / OFF signal is “LOW”, the DC removal function is “OFF”, the E side (the output signal from the upper waveform equalization circuit 11) is selected, and “HIGH”. The DC removal function is turned “ON”, and the F side (the output signal from the lower switch 12b) is selected. The signal output from the switch 12c is supplied to the maximum likelihood decoding circuit 15, and the reproduction signal is decoded by the maximum likelihood decoding circuit 15. The decoded reproduction signal is supplied to the demodulation / error correction circuit 16, and the demodulation / error correction circuit 16 performs demodulation and error correction processing of the reproduction signal. The processed reproduction signal (binarized signal) is output to a host (such as a microcomputer).

<DC removal circuit>
FIG. 3 shows an example of the configuration of the first DC removal circuit (# 1) 13a and the second DC removal circuit (# 2) 13b. The DC removal circuit 13 includes subtractors 31a and 31b, multipliers 32a and 32b, an adder 33, and a delay register (D) 34. The operation will be described below. The reproduction signal output from the waveform equalization circuit 11 is supplied to the subtractor 31b. Further, the direct current component (DC) signal output from the first DC detection circuit (# 1) 17a or the second DC detection circuit (# 2) 17b is supplied to the subtractor 31a. On the other hand, the output signal from the delay register 34 is input to the subtractor 31a. The subtractor 31a supplies a result obtained by subtracting the output value of the delay register 34 from the input DC signal to the first multiplier 32a. A time constant 14 (corresponding to 14a and 14b in FIG. 1) is set in advance in the first multiplier 32a, and the result obtained by multiplying the time constant 14 by the output value from the subtractor 31a is added. Supply to the vessel 33. On the other hand, the output from the second multiplier 32 b is supplied to the adder 33. The adder 33 adds the output of the first multiplier 32 a and the output of the second multiplier 32 b and supplies the result to the delay register 34.

  The output of the adder 33 supplied to the delay register 34 is in a state where the reproduction signal output from the waveform equalization circuit 11 next in the first or second DC detection circuit (17a, 17b) crosses a certain slice level. The phase difference from the reproduction clock at that time is held until the amplitude information of the reproduction signal waveform is detected as a DC component. The output of the delay register 34 is supplied to the second multiplier 32b. A time constant 14 (corresponding to 14a and 14b in FIG. 1) is set in advance in the second multiplier 32b, and the result of multiplying the time constant 14 by the output value from the delay register 34 is This is supplied to the adder 33.

  The first multiplier 32a, the adder 33, the delay register 34, and the second multiplier 32b constitute a digital filter. With the time constant 14 set in the first multiplier 32a and the second multiplier 32b, A low-pass filter (low-pass filter) is realized. By passing the DC detected by the first or second DC detection circuit (17a, 17b) through a low-pass filter, only a steady DC is detected without detecting a wide-range noise component or a sudden DC. Can be detected. The detected steady DC is the output of the delay register 34, and this output is supplied to the second subtractor 31b.

  On the other hand, the input reproduction signal is supplied to the second subtractor 31b. The second subtractor 31b supplied with the output from the delay register 34 and the input reproduction signal subtracts the output from the delay register 34 from the input reproduction signal and outputs the result. This output signal is a signal obtained by constantly subtracting DC from the input signal, that is, a reproduction signal obtained by removing stationary DC from the input reproduction signal.

<Example of DC detection>
4 and FIG. 5, in the first DC detection circuit (# 1) 17a and the second DC detection circuit (# 2) 17b, there is a slice level at which a signal output from the waveform equalization circuit 11 is present. An example of detecting the difference in phase between the state straddling and the recovered clock at that time as the amplitude information of the signal waveform as a direct current component (DC) will be described.

  For example, the case of FIG. 4 is used in the first DC detection circuit 17a. FIG. 4 shows an input reproduction signal and a reproduction clock generated by the PLL circuit 10. This is a case where a point that crosses the slice level of the input reproduction signal (zero cross point) and a point at which the reproduction signal is sampled by the reproduction clock generated by the PLL circuit 10 (sampling point) are the same point.

  As in the case of FIG. 4A, the state where there is no phase difference between the zero cross point and the sampling point of the reproduction signal is a state where there is no DC in the reproduction signal. In the case of FIG. 4B, there is a phase difference between the zero cross point and the sampling point of the reproduction signal, that is, a state where DC remains in the reproduction signal. The difference between the amplitude value of the reproduction signal and the slice level at the sampling point after the zero cross point of the reproduction signal becomes the DC of the reproduction signal as it is.

  On the other hand, for example, the case of FIG. 5 is used in the second DC detection circuit 17b. FIG. 5 shows a case where the zero cross point of the input reproduction signal and the sampling point generated by the PLL circuit 10 are shifted by 180 degrees. Since there are no sampling points at the zero cross points (points C and F) of the reproduction signal as in FIG. 5A, the amplitude value and slice level of the reproduction signal at the sampling point as in FIG. The difference between the two is not directly the DC of the reproduction signal. In this case, processing for obtaining the values of the points C and F from the sampling points before and after the zero cross point (points C and F) of the reproduction signal (the points A and D before, the points B and E behind). is necessary. For example, when the amplitude value at the sampling point at point A and the amplitude value at the sampling point at point B are added and divided by 2, the amplitude value at point C at the zero cross point can be obtained. Similarly, when the amplitude value at the sampling point at the D point and the amplitude value at the sampling point at the E point are added and divided by 2, the amplitude value at the F point at the zero cross point is obtained. The obtained amplitude value at the point C or F is the difference between the amplitude value of the reproduction signal at the zero cross point and the slice level, that is, the DC of the reproduction signal.

  In the case of FIG. 5A, the reproduction signal has no DC, and the amplitude value at point C is zero. In the case of FIG. 5B, similarly, the values of the I point and the L point are obtained from the sampling points before and after the zero cross point of the reproduction signal (G point and J point before, H point and K point after). is required. For example, when the amplitude value at the sampling point at the G point and the amplitude value at the sampling point at the H point are added and divided by 2, the amplitude value at the I point near the zero cross point is obtained. Similarly, when the amplitude value at the sampling point at the J point and the amplitude value at the sampling point at the K point are added and divided by 2, the amplitude value at the L point near the zero cross point is obtained. The obtained amplitude value at point I or L is the difference between the amplitude value of the reproduction signal and the slice level at the zero cross point, that is, the DC of the reproduction signal. In the case of FIG. 5B, the amplitude value at point I or L is not zero, that is, DC remains in the reproduction signal.

  The zero cross point of the input reproduction signal and the sampling point generated by the PLL circuit 10 as shown in FIGS. 4 and 5 are shifted in phase or 180 degrees from the PLL circuit 10 and the waveform equalization circuit 11. It is caused by the configuration and coefficients. This configuration and coefficient are determined in advance (uniquely determined during operation according to the design). Therefore, an appropriate configuration (for example, FIG. 4 or FIG. 5) of the DC detection circuit (17a, 17b) may be selected by switching the switching signal # 2 (switch 12d) according to the configuration or coefficient. In this way, even if the phase relationship between the reproduction signal and the reproduction clock is different, the first and second DC detection circuits (17a, 17b) can detect the DC of the reproduction signal.

  For example, the configurations shown in FIGS. 4 and 5 are uniquely determined during operation. In addition, for example, not only areas having different characteristics but also discs having different characteristics (for example, a Blu-ray disc and a DVD-RAM disc) are reproduced by this apparatus (for example, the configuration of FIG. -RAM disk configuration shown in FIG. In this apparatus, the waveform equalization and the PLL configuration may be changed during operation, and in this case, the phase shift may occur.

<Switching control operation>
In FIG. 6, the switching control operation of the switches 12a, 12b, 12c, and 12d when the DVD-RAM disc 50 (disc 1) is reproduced will be described. As described above, the DVD-RAM disc 50 has the recording area 51 and the header area 52 in which the physical ID is embedded. At this time, for example, when the switching signal # 1 is controlled to be “HIGH” in the header area 52 and “LOW” in the recording area 51, the switch 12a switches to the B side when the switching signal # 1 is “HIGH”. When it is “LOW”, it switches to the A side. The switch 12b switches to the D side when the switching signal # 1 is “HIGH”, and switches to the C side when the switching signal # 1 is “LOW”. In short, the second DC removal circuit 13b operates when the switching signal # 1 is “HIGH”, and the first DC removal circuit 13a operates when the switching signal # 1 is “LOW”. At this time, the first DC removal circuit 13a is set to a small value as the value of the time constant 14a so that the DC can be removed for the header region 52 in a short time, and the DC is removed in a short period. It can be so. The second DC removal circuit 13b is set to a large value as the value of the time constant 14b so that DC can be removed for the recording area 51 in a long time so that steady DC can be removed. To. Thereby, it is possible to remove DC components having different time constant characteristics between the header area 52 and the recording area 51. The setting of the time constant 14 may be constant or variable.

  Further, the ON / OFF signal is turned OFF (“LOW”) in order to perform the decoding process with the output of the waveform equalization circuit 11 without using the DC removal circuit (13a, 13b) (DC removal function). Then, the switch 12c becomes the E side, and the output of the waveform equalization circuit 11 is supplied to the maximum likelihood decoding circuit 15 via the switch 12c. When the ON / OFF signal is turned ON ("HIGH"), the switch 12c is turned to the F side, and the selection output (via the switch 12b) of either the first or second DC removal circuit (13a, 13b) is switched to the switch 12c. Via the maximum likelihood decoding circuit 15.

  Further, the two DC detection circuits (17a, 17b) are switched by the switching signal # 2. For example, when characteristics such as waveform equalization are changed (when parameters of the waveform equalization circuit 11 are changed), the switching signal # 2 is switched from “HIGH” to “LOW” at timing T1. As a result, the switch 12d is switched from the G side (DC detection circuit 17a having the characteristics shown in FIG. 4) to the H side (DC detection circuit 17b having the characteristics shown in FIG. 5). Thereby, an appropriate DC detection circuit (17a, 17b) is selected according to the state of the phase of the reproduction signal and the reproduction clock according to the change.

  As described above, according to the present embodiment, two DC detections are performed even when the phase of the reproduction signal and the reproduction clock is different (shifted) depending on waveform equalization, PLL configuration, or the like. An appropriate one can be selected from the circuits (17a, 17b) to detect the DC component of the reproduction signal. Conventionally, since there was one DC detection circuit, it was not possible to cope with the above-described phase shift, but in this apparatus, it is possible to cope with two DC detection circuits (17a, 17b) of one LSI 100. Further, even when the disc 1 having a plurality of areas having different characteristics such as the DVD-RAM disc 50 is reproduced, the DC removal circuits (13a, 13b) having different time constants are operated in the respective areas. As a result, the DC component of the reproduction signal can be removed. Thereby, the reproduction performance and the ID acquisition rate can be improved. Further, the present invention can be similarly applied when there are three or more DC detection circuits and removal circuits.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used for an optical disc apparatus.

It is a figure which shows the block configuration of the optical disk apparatus in one embodiment of this invention. 1 is a block diagram illustrating an example of a PLL circuit in an optical disc apparatus according to an embodiment of the present invention. 1 is a block diagram illustrating an example of a DC component removal circuit in an optical disc apparatus according to an embodiment of the present invention. FIG. FIG. 3 is a diagram illustrating a first waveform for explaining a direct current component of a reproduction signal in the optical disc apparatus according to the embodiment of the present invention. FIG. 6 is a diagram illustrating a second waveform for explaining a direct current component of a reproduction signal in the optical disc apparatus according to the embodiment of the present invention. In the optical disk apparatus according to the embodiment of the present invention, as an example of the configuration, it is a diagram illustrating the switch switching timing. It is a figure for demonstrating the format of the DVD-RAM disc in a prior art which can be reproduced | regenerated in the optical disk apparatus of one embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Disk, 2a ... Clamper, 2b ... Turntable, 3 ... Objective lens, 4 ... Pickup, 5 ... Thread motor, 6 ... Spindle motor, 7 ... Signal processing circuit, 8 ... Servo circuit, 9 ... A / D converter DESCRIPTION OF SYMBOLS 10 ... Phase synchronous circuit (PLL circuit), 11 ... Waveform equalization circuit, 12a, 12b, 12c, 12d ... Switch (1st-4th changeover switch), 13 ... DC component (DC) removal circuit, 13a ... DC component (DC) removal circuit (# 1), 13b ... DC component (DC) removal circuit (# 2), 14, 14a, 14b ... time constant, 15 ... maximum likelihood decoding circuit, 16 ... demodulation / error correction circuit, 17a ... DC component (DC) detection circuit (# 1), 17b ... DC component (DC) detection circuit (# 2), 20 ... Phase error detection circuit, 21 ... Loop filter, 22 ... Voltage controlled oscillator (VCO), 31 , 31b ... subtractor, 32a, 32b ... multiplier, 33 ... adder, 34 ... delay register, 50 ... DVD-RAM disc, 51 ... recording area, 52 ... header area, 53 ... mirror area, 54 ... embossed pit, 55 ... Land, 56 ... Groove, 100 ... LSI.

Claims (5)

A circuit of an optical disc apparatus that optically reproduces or records / reproduces information with respect to the disc with an optical pickup for focusing the laser beam on the disc,
A circuit for analog / digital conversion of an analog input signal read from the disk through the pickup with a predetermined clock;
A first detection circuit for detecting a DC component of the analog-digital converted signal;
A second detection circuit for detecting a DC component of the analog-digital converted signal;
A first switch circuit that switches between the first and second detection circuits;
A removal circuit that removes a DC component detected by the first or second detection circuit from the analog-digital converted signal with a predetermined time constant, and
Even when the phase relationship between the signal and the clock is different, the DC component of the reproduction signal is appropriately detected by switching the first and second detection circuits using the first switch circuit according to the phase relationship. And removing it with the predetermined time constant. A circuit of an optical disc apparatus that optically reproduces or records / reproduces information with respect to the disc with an optical pickup for focusing the laser beam on the disc,
A circuit for analog / digital conversion of an analog input signal read from the disk through the pickup with a predetermined clock;
A phase synchronization circuit for synchronizing a data signal and a sampling clock for the analog / digital conversion based on a signal obtained by the analog / digital conversion circuit;
An equalization circuit for equalizing the waveform of the signal obtained by the analog-digital conversion circuit;
A first detection circuit for detecting a DC component of a signal obtained by equalizing the waveform;
A second detection circuit for detecting a DC component of the signal obtained by equalizing the waveform;
A first switch circuit that switches between the first and second detection circuits;
A first removal circuit for removing a direct current component detected by the first or second detection circuit from the signal obtained by equalizing the waveform with a first time constant;
A second removal circuit that removes a DC component detected by the first or second detection circuit from the signal obtained by equalizing the waveform with a second time constant;
A second switch circuit that switches between the first and second removal circuits, and
Even when the phase relationship between the signal and the clock is different, the first and second detection circuits are switched using the first switch circuit according to the phase relationship, and the first and second removal circuits are A circuit for an optical disc apparatus, wherein a DC component of a reproduction signal is appropriately detected by switching using a second switch circuit, and is removed with a different first or second time constant. A circuit of an optical disc apparatus that optically reproduces or records / reproduces information with respect to the disc with an optical pickup for focusing the laser beam on the disc,
A circuit for analog / digital conversion of an analog input signal read from the disk through the pickup with a predetermined clock;
A phase synchronization circuit that synchronizes a data signal and a sampling clock for analog / digital conversion based on a signal obtained by the analog / digital conversion circuit;
An equalization circuit for equalizing the waveform of the signal obtained by the analog-digital conversion circuit;
A first detection circuit for detecting a DC component of a signal obtained by equalizing the waveform;
A second detection circuit for detecting a DC component of the signal obtained by equalizing the waveform;
A first switch circuit that switches between the first and second detection circuits;
A first removal circuit for removing a direct current component detected by the first or second detection circuit from the signal obtained by equalizing the waveform with a first time constant;
A second removal circuit that removes a DC component detected by the first or second detection circuit from the signal obtained by equalizing the waveform with a second time constant;
A second switch circuit for switching between the first and second removal circuits;
A circuit that performs maximum likelihood decoding of the signal from which the DC component has been removed by the first or second removal circuit,
The first and second detection circuits are switched using the first switch circuit according to the phase relationship between the signal and the clock, and the first and second removal circuits are switched using the second switch circuit. A circuit of an optical disc apparatus, characterized in that, by switching, a DC component of a reproduction signal is appropriately detected and removed with the different first or second time constant. In the circuit of the optical disk device according to any one of claims 1 to 3,
A circuit for an optical disc apparatus, wherein the detection circuit and the removal circuit to be used are selected according to the type of the disc or the type of area on the disc. In the circuit of the optical disc device according to claim 2 or 3,
A circuit for an optical disc apparatus, wherein the detection circuit and the removal circuit to be used are selected according to a change in a parameter configuration of the equalization circuit.

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