JP2009005214A - Clock phase control apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock phase control apparatus including a voltage control delay means which enables a control voltage/delay time property to be hardly affected by variation in all samples even if the property of a component such as a transistor is varied by a manufacturing error or the like for each sample. <P>SOLUTION: The present invention relates to a clock phase control apparatus including a multi-phase clock producing means to which a high frequency clock is inputted to produce a multi-phase clock. The multi-phase clock producing means includes a voltage control delay means, the voltage control delay means includes a voltage/current converting section 108 for converting an inputted control voltage to a current, and also includes: a control means for outputting a control current in proportion to the current converted by the voltage/current converting section 108; and a delay means for delaying the high frequency clock just for a time corresponding to the control current and outputting the delayed high frequency clock, and the voltage/current converting section 108 has a linear voltage/current conversion property in a predetermined input voltage range. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a clock phase control apparatus.

  In a semiconductor integrated circuit, a voltage controlled delay line (VCDL) is used to delay a clock or data for a certain time and generate a multiphase clock. The voltage controlled delay element generates a delay time determined according to the input voltage. In recent years, multiphase clocks are often used for the purpose of increasing the clock frequency in a pseudo manner. A DLL (Delay Locked Loop) is often used as means for generating the multi-phase clock, and a voltage-controlled delay element is used to generate a delay time that is a phase difference of the multi-phase clock inside the DLL.

  FIG. 1 shows the configuration of a simple voltage controlled delay element. In FIG. 1, cki is an input clock, cko is an output clock, and Vcont is a delay time control voltage. A unit surrounded by a dotted line is considered to be one stage of voltage controlled delay elements, and FIG. 1 has a configuration in which two stages are connected. However, an inverted clock of cki is output for ckm after passing through one stage.

  The currents of the Pch Trs 101 and 102 are controlled by the Vcont in FIG. 1, and when the current increases, the delay time of the cco with respect to the cki is shortened. Conversely, when the current decreases, the delay time of cco with respect to cki becomes longer. Further, the Nch Trs 103 and 104 operate as a switch, and when one of the Nch Trs 103 and 104 is turned on, the Nch Tr drain node is pulled down.

  FIG. 2 shows the clock waveform of each node. cki is an input waveform. Further, the inverted clock is output with a delay of ckm by a delay amount Δd of one stage of the voltage controlled delay element. Also, cko is output with a delay of Δd * 2 from cki. The delay time Δd is controlled by the delay time control voltage Vcont.

  FIG. 3 shows a configuration in which a variable current source is provided on the NchTr side so that the NchTr side and the PchTr side are symmetrical. In the case of the configuration of FIG. 3, the Nch side and Pch side current sources Tr flow the same current by the delay time control voltage Vcont, and the rise time and fall time of ckm and cko become the same. As with the case of FIG. 1, when the delay time control voltage Vcont is changed, the delay time Δd is changed accordingly. The Pch Trs 105, 106, and 107 constitute a current mirror, and the Pch Tr 105 is the master.

  FIG. 4 shows the control voltage-delay time characteristics. In the case of the configuration of FIG. 3, the delay time becomes shorter as the control voltage increases. In FIG. 4, for example, when the control voltage Vcont = Vd, the delay time is Td.

  The voltage control delay element as described above is mounted on a semiconductor integrated circuit. Moreover, very fine processes such as a 90 nm process and a 65 nm process have become mainstream in recent semiconductor processes. In the case of such a fine process, it is difficult to increase the manufacturing accuracy of a device (transistor), and there are not a few variations in characteristics in the manufactured transistor. For example, when the threshold voltage variation of Tr (transistor) between a plurality of samples is 3σ = 100 mV, especially in an analog circuit, if the threshold voltage varies greatly, the function may not be satisfied. In a conventional voltage controlled delay element, the delay time varies depending on the sample even if the same control voltage is input, for example, due to this transistor variation. FIG. 5 shows the control voltage-delay time characteristics of the voltage control delay elements of three types of samples (sample 1, sample 2, sample 3). sample1 is a standard sample, sample2 is a sample with a short delay time (for example, a threshold voltage of Tr is low), and sample3 is a sample with a long delay time (for example, a threshold voltage of Tr is high). When it is desired to generate the same delay time Td in these three types of samples, the control voltages to be input are Vd1, Vd2, and Vd3, respectively. In the case of the control voltage-delay time characteristic as shown in FIG. 5, the control voltage changes greatly from sample to sample. The delay time gain with respect to the control voltage also changes. If the characteristics of the voltage-controlled delay element change depending on the sample in this way, it is difficult to use when it is desired to generate a highly accurate delay time or when it is used as a delay element in a DLL (Delay Locked Loop). End up.

  In the present invention, even if the characteristics of components such as transistors vary from sample to sample due to manufacturing errors, the control voltage-delay time characteristics (voltage delay conversion characteristics) are not easily affected by variations in all samples (that is, An object of the present invention is to provide a clock phase control device having voltage control delay means (which can have control voltage-delay time characteristics as shown in FIG. 4 in all samples).

  In order to achieve the above object, the invention according to claim 1 is a clock phase control device having a multi-phase clock generating means for generating a multi-phase clock by receiving a high frequency clock, wherein the multi-phase clock generating means comprises: The voltage control delay means includes a voltage-current converter that converts the input control voltage into a current, and outputs a control current proportional to the current converted by the voltage-current converter. Control means for delaying, and delay means for delaying and outputting the high-frequency clock by a time corresponding to the control current, and the voltage-current converter has a linear voltage-current conversion characteristic in a predetermined input voltage range. It is characterized by being.

  According to a second aspect of the present invention, in the clock phase control device according to the first aspect, the clock phase control device further includes a set pulse and a set pulse based on the multiphase clock generated by the multiphase clock generation means. A set signal generating means for generating a set signal in accordance with a position selection signal; a reset signal generating means for generating a reset signal in accordance with a reset pulse and a reset position selection signal with reference to the multiphase clock; It has an SR flip-flop that generates a controlled clock.

  According to a third aspect of the present invention, in the clock phase control device according to the first aspect, the voltage-current conversion unit includes an operational amplifier and a resistance element, and the control voltage inputted by the virtual short circuit of the operational amplifier is supplied to the resistance element. It is characterized by being converted into a current determined by a resistance value.

  According to a fourth aspect of the present invention, in the clock phase control apparatus according to the third aspect, the resistance element is a variable resistance whose resistance value can be changed.

  According to a fifth aspect of the present invention, in the clock phase control device according to any one of the first to fourth aspects, the high-frequency clock is a differential signal, and the delay means is the differential signal. It is characterized by a corresponding differential configuration.

  According to a sixth aspect of the present invention, in the clock phase control device according to any one of the first to fifth aspects, the multiphase clock generation means includes the voltage control delay means and the voltage control delay. A phase comparison means for comparing the phase difference between the first output signal and the second output signal of the means; a loop filter for receiving the output signal of the phase comparison means and outputting the control voltage of the voltage control delay means; It is characterized by having.

  According to a seventh aspect of the present invention, in the clock phase control device according to any one of the first to fifth aspects, the multiphase clock generation means includes the voltage control delay means and the voltage control delay. Means for comparing the phase difference between the first output signal and the second output signal of the means, charge pump means for converting the output signal of the phase comparison means into a current signal, and the output signal of the charge pump means And a loop filter that outputs the control voltage of the voltage control delay means.

  According to the first to seventh aspects of the present invention, even if the characteristics of the constituent elements such as the transistors vary from sample to sample due to manufacturing errors, the control voltage-delay time characteristics (voltage delay conversion characteristics) in all the samples. Is difficult to be affected by variations (that is, in a semiconductor integrated circuit, voltage delay conversion characteristics hardly vary even if characteristics of components such as transistors vary due to manufacturing errors). A circuit can be realized.

  In particular, according to the second aspect of the present invention, it is possible to realize a clock phase control device capable of digitally controlling a clock phase with a relatively easy configuration.

  According to the fourth aspect of the present invention, it is possible to set a desired voltage-current conversion gain by making the resistance element of the voltage-current conversion unit variable.

  According to the fifth aspect of the present invention, in the semiconductor integrated circuit, even if the characteristics of the constituent elements such as transistors vary due to manufacturing errors, the voltage-controlled delay means having a differential configuration that hardly varies the voltage delay conversion characteristics. A clock phase control device having the following can be realized.

According to the sixth and seventh aspects of the invention, in the semiconductor integrated circuit, even if the characteristics of components such as transistors vary due to manufacturing errors, the voltage delay conversion characteristics hardly vary, and the loop gain does not vary. A clock phase control device having a DLL circuit that hardly varies can be realized.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.

  FIG. 6 is a diagram showing a configuration example of voltage control delay means (voltage control delay circuit) used in the clock phase control apparatus according to the present invention. Referring to FIG. 6, the voltage / current converter 108 (block surrounded by a dotted line in FIG. 6) includes an operational amplifier 111, a resistance element 112, and a current source PchTr 113. Here, the delay time control voltage Vcont is input to the negative input of the operational amplifier 111, and the output of the operational amplifier 111 is connected to the gate pp of the current source PchTr113. Current source PchTr113 flows current Id into resistance element 112 (resistance value R) according to the voltage of gate pp. In addition, one end of the resistance element 112 is connected to GND, and generates a potential of Id * R at the other end Vcontm by the current Id. Node Vcontm is connected to the positive input of operational amplifier 111. As described above, the voltage / current converter 108 is a negative feedback circuit including the operational amplifier 111. By this negative feedback action, the node Vcontm is controlled to have the same potential as the delay time control voltage Vcont (virtual short).

  The gain and band of the operational amplifier 111 are determined in consideration of the stability and control accuracy of the negative feedback loop. Further, although not shown in FIG. 6, a capacitor and a filter for stabilizing the negative feedback loop can be added as appropriate. Due to the virtual short-circuit of the operational amplifier 111, Vcontm and Vcont become substantially the same potential, and the equation Id = Vcont / R is established. According to this equation, linearity is established between Id and Vcont, and the gain is 1 / R. That is, the voltage-current conversion characteristic is determined by the resistance value R of the resistance element 112 and depends only on the variation of the resistance element 112.

  In FIG. 6, when the output node pp of the operational amplifier 111 is connected to the gates of the current sources PchTr 114 to 117, the same current Id is generated when the size of each of the current sources PchTr 114 to 117 is the same as that of the PchTr 113. Further, the Nch Trs 118 to 121 constitute a current mirror, and the Nch Tr 118 serves as a master for turning back the current Id. In this way, the current Id flows from each current source Tr according to switching in each voltage controlled delay element.

  FIG. 7 is a diagram showing a transient current flow in the voltage controlled delay element. FIG. 7 is a diagram when the potential of the node ckm rises. In FIG. 7, first, when cki falls, PchTr 109 is turned on, and current Id flows from current source Tr110. The node ckm has a parasitic capacitance Cp such as a gate capacitance or a wiring capacitance of the next stage, and is charged by the current Id. The longer the time for which the current Id charges the parasitic capacitance Cp, the longer the delay time, and the shorter the charging time, the shorter the delay time. The same applies to the discharge time. Assuming that the variation of the parasitic capacitance itself is not so large, the delay time can be controlled if the current Id can be controlled to be constant regardless of the sample variation. In FIG. 6, since the voltage I / D converter 108 can generate a current Id that does not depend on sample variation, a voltage control delay means (voltage control delay circuit) whose control voltage-delay time characteristic does not depend on sample variation can be realized. . For example, when the voltage control delay circuit of FIG. 3 has sample variation as shown in FIG. 5, even if the transistor characteristics vary depending on the sample by adopting the circuit configuration as shown in FIG. 6, the control voltage-delay time characteristic is Ideally, as shown in FIG.

  The result of actual simulation using SPICE is shown below.

  In the simulation, device parameters of 90 nm process were used, and the circuit of FIG. 3 and the circuit of FIG. 6 were performed. The transistor sizes of the voltage controlled delay elements in FIGS. 3 and 6 are the same. FIGS. 8 and 9 are graphs plotting the delay time with respect to the control voltage Vcont for each of the circuits in FIGS. 3 and 6. Here, the voltage control delay element has a four-stage configuration. In addition, simulation was performed for three types (typ, slow, fast) of sample variations. The slow sample transistor is inferior in current drive capability compared to the typ sample, and the fast sample is superior to the typ sample. Specifically, for example, the threshold voltage of the slow sample is about 100 mV higher than the type sample, and the fast sample is about 100 mV lower than the type sample. Referring to FIG. 8 showing the control voltage-delay time characteristic of the circuit of FIG. 3, it can be seen that the delay time varies greatly depending on the sample. For example, when it is desired to generate a delay of 500 ps, it is necessary to input about 0.46 V as the control voltage Vcont, about 0.67 V as the slow sample, and about 0.33 V as the fast sample. Depending on the sample, Vcont varies as much as 340 mV. On the other hand, the three types (type, slow, fast) transistor variations in FIG. 9 showing the control voltage-delay time characteristics of the circuit of FIG. 6 are the same as those of FIG. 8, but the control voltage-delay time of FIG. The characteristics are considerably less varied than those in FIG. When trying to generate a delay time of 500 ps, the control voltage is about 0.52 V for both the type and fast samples, and the slow sample is about 0.58 V. Even if the characteristics of the transistors vary depending on the samples, they fall within 60 mV. ing.

  Since voltage control delay means (voltage control delay circuit) independent of sample variation can be realized in this way, by using such voltage control delay means (voltage control delay circuit) as a multiphase clock generation means, A clock phase control device with excellent clock phase control accuracy can be realized.

  FIG. 10 is a diagram showing a configuration when the resistance element of the voltage-current converter 108 in FIG. 6 is a variable resistor. The circuit in FIG. 10 basically operates in the same manner as in FIG. 6, but the voltage-current conversion gain (gain) of the voltage-current conversion unit 122 can be made variable by making the resistance element variable resistance (Rval). . That is, the expression Id = Vcont / Rval is established, and the gain (gain) of the control voltage-delay time characteristic can be changed according to the value of Rval. For example, when this voltage controlled delay circuit is used inside a DLL (Delay Locked Loop), the value of Rval can be changed in accordance with the loop gain of the DLL.

  FIG. 11 is a diagram showing a voltage control delay circuit when the voltage control delay element has a differential configuration in the circuit of FIG. In FIG. 11, a block 123 surrounded by a dotted line is one stage of a differential voltage controlled delay element. PchTrs 124 and 125 are load transistors, NchTrs 126 and 127 are switch transistors, and NchTr150 is a current source transistor. In particular, when the input is a differential clock, the circuit of FIG. 11 is used. In other words, in the case of FIG. 10, if an extremely slow delay is generated, the signal amplitude may be attenuated and extinguished due to the rise and fall. On the other hand, by making it differential as shown in FIG. 11, the common mode voltage is eliminated and the possibility of transmission even in the case of a small amplitude is increased.

  FIG. 12 is a diagram showing a configuration when the voltage control delay circuit of FIG. 6 is used in a DLL. In FIG. 12, a VCDL (Voltage Controlled Delay Line) 128 is the voltage control delay circuit of FIG. 6, and the control voltage Vcont is input to delay the input clock cki. From the VCDL 128, ck0 and ck1 are output as references for loop control, and a multiphase clock cko is generated. XOR 129 is an exclusive OR gate, which receives ck0 and ck1 and outputs an exclusive OR ckm of the two clocks. That is, when both ck0 and ck1 are clocks with a duty of 50% with a period T and the phase is shifted by T / 4, a clock with a duty of 50% is output with a period of T / 2 as ckm. The filter 130 is a filter that receives the clock ckm and outputs the control voltage Vcont. In order to output Vcont as a stable voltage, the band of the filter needs to be sufficiently lower than the frequency of the clock ckm. Thus, in the example of FIG. 12, the DLL circuit that outputs the multiphase clock cko from the input clock cki is configured by the VCDL 128, the XOR 129, and the filter 130.

  FIG. 13 shows a configuration example of the XOR 129 in FIG. In FIG. 13, 132 to 134 are inverters, and 131 is a multiplexer. The multiplexer 131 outputs one of the clocks as ckm depending on the state of ck1 when the forward clock and the inverted clock of ck0 are input. This operation will be described with reference to FIG. In FIG. 14, ck0 and ck1 are both clocks with a period T and a duty of 50%. With the configuration of FIG. 13, when ck1 is L, ck0 is output as it is, and when ck1 is H, the inversion of ck0 is output. That is, when the phase difference between ck0 and ck1 is T / 4, ckm is a clock with a cycle of T / 2 and a duty of 50%. When the duty of ckm is 50%, the voltage Vcont after passing through the filter 130 is in a stable state. FIG. 15 shows the multi-phase clock output cko in a state where Vcont is stable (the DLL is locked). In FIG. 15, it is assumed that the multiphase clock output cko has four layers, and the number of stages of the voltage controlled delay element of the VCDL 128 is four. In the state where the DLL in FIG. 12 is locked, the phase difference between ck0 and ck1 is T / 4, that is, the delay time of one stage of the voltage controlled delay element is T / 4.

  FIG. 16 is a diagram showing another configuration example when the voltage control delay circuit of FIG. 6 is used for a DLL. In FIG. 16, VCDL 135 is the voltage control delay circuit of FIG. 6, and the control voltage Vcont is input to delay the input clock cki. Also, from the VCDL 135, ck0 and ckn are output as references for loop control, and a multiphase clock cko is generated. The PD 136 is a phase comparator. The PD 136 receives ck0 and ckn, compares the phases of the two clocks, and outputs the upb and dn signals based on the result. Further, CP137 is a charge pump, and upb and dn are input, thereby outputting a multiphase clock cpo. Filter 138 is a filter that receives cpo and generates control voltage Vcont. In order to output Vcont as a stable voltage, the filter band needs to be sufficiently lower than the frequencies of the clocks ck0 and ckn. In this way, in the example of FIG. 16, the DLL circuit that outputs the multiphase clock cko from the input clock cki is configured by the VCDL 135, PD 136, CP 137, and Filter 138.

  FIG. 17 shows a configuration example of the PD 136 in FIG. In FIG. 17, reference numerals 142 to 144 denote inverters, 141 denotes a NAND gate, and 139 and 140 denote FFs (flip-flops). In the FFs 139 and 140, the data input unit is always at the H potential, the H potential is taken in accordance with ck0 and ckn, respectively, and is reset by rb. The NAND gate 141 receives the outputs a and b of the FF 139 and FF 140 and outputs rb. The nodes a and b become upb and dn through the inverter 142 and the inverters 143 and 144, respectively, but the number of inverter stages is different in order to correspond to the configuration of the charge pump described later.

  The operation of FIG. 17 will be described with reference to FIG. FIG. 18 shows waveforms of the nodes ck0, ckn, a, b, rb, upb, and dn. The phase difference between ck0 and ckn is Δt, and a and b rise when they rise. When a and b are simultaneously in the H potential state, rb falls by the NAND gate 141. When rb falls, the FFs 139 and 140 are reset, and the respective outputs a and b fall. As a result, the output rb of the NAND gate 141 rises. Therefore, the waveform is as shown in FIG. dn outputs the normal rotation of b as it is, but upb outputs the inversion of a. If upb is active in the L state and dn is active in the H state, the active period of upb is longer than dn by Δt. That is, the phase difference Δt between the input clocks ck0 and ckn is held as it is, and is taken out as the difference between the active periods of upb and dn.

  FIG. 19 shows a configuration example of CP 137 in FIG. In FIG. 19, the charge pump includes a current source Ip that is an up current source, a current source In that is a dn current source, an up switch transistor 145, and a dn switch transistor 146. Since the switch transistor 145 for up is pchTr, upb inversion of up is input as an input signal. That is, when upb is at L potential, the current source Ip flows current into cpo, and when dn is at H potential, the current source In draws current from cpo. It is assumed that the current values of the current source Ip and the current source In are equal.

  FIG. 20 shows ck0, ckn, upb, and dn when the Vcont of the DLL circuit of FIG. 16 is stable (the DLL is locked). In FIG. 20, when DLL is locked, the phases of ck0 and ckn are the same (the phase of ckn is delayed by a period T from ck0), and therefore the active period of upb and dn is the same time. Therefore, the charge flowing into cpo by the charge pump is equal to the extracted charge, and Vcont becomes a stable voltage. At this time, assuming that the number of voltage controlled delay elements between ck0 and ckn is n in the VCDL, a multiphase clock having a phase difference of T / n can be output as cko.

  FIG. 21 is a diagram illustrating a configuration example of a clock phase control device to which the voltage control delay circuit and the DLL circuit described above are applied. In FIG. 21, the multiphase CLK generation means 200 is constituted by the voltage control delay circuit of FIG. 6 or the DLL circuit of FIGS. 12 and 16, and receives the high frequency clock CKIN and outputs the multiphase clock CKM. Yes. The SET generation means 203 receives a set pulse SETPLS, a set position selection signal SETSEL, and a multiphase clock CKM, and outputs a SET. Here, SET represents the timing of the rising edge of the generated clock CKOUT. The RESET generation means 201 receives a reset pulse RESETPLS, a reset position selection signal RESETSETEL, and a multiphase clock CKM, and outputs a RESET. Here, RESET represents the timing of the falling edge of the generated clock CKOUT. The SR flip-flop SRFF 202 receives SET and RESET and outputs a generated clock CKOUT. Here, SETPLS, SETSEL, RESETPLS, and RESETSET are each input in synchronization with CKIN.

  FIG. 22 is a diagram illustrating a configuration example of the SET generation unit 203. In FIG. 22, when the multiphase clock CKM and the set position selection signal SETSEL are input, the MUX 204 selects one clock from the multiphase clock CKM according to the value of the SETSEL and outputs it as CK. . Further, when SETPLS and CK are input, the pulse delay circuit 205 delays the rising position of SETPLS according to the phase of CK and generates SET. That is, the SET generation unit 203 in FIG. 22 generates a SET by delaying the rising edge of SETPLS according to SETSEL with reference to the multiphase clock CKM.

  FIG. 23 is a diagram illustrating a configuration example of the pulse delay circuit 205. In FIG. 23, when SETPLS is low, SET is forced low. When SETPLS goes high and CK falls from high to low, SET rises. When SETPLS falls, SET falls again. That is, SETSET is generated by delaying the rising edge of SETPLS in accordance with the rising edge of CK.

  FIG. 24 is a timing chart showing the operation of the SET generation means 203 in the configuration of FIGS. FIG. 24 shows a case where the multiphase clock CKM has four phases. Referring to FIG. 24, SETPLS and SETSEL are input synchronously at a timing earlier than CKM0. FIG. 24 shows a case where SETSEL is 3, and when SETSEL is 3, CKM3 is selected as CK. That is, the rising edge position of the generated SET is the position of CKM3, and the falling edge position of the SETPLS is output as it is.

  The RESET generation unit 201 in FIG. 21 can also be realized by the same configuration as the SET generation unit 203, and the RESET generation unit 201 generates a RESET by delaying the rising edge position of RESETPLS according to the value of RESETSEL.

  FIG. 25 is a diagram illustrating a configuration example of the SRFF 202. Referring to FIG. 25, the SRFF 202 includes inverters 206 and 207 and NANDs 208 and 209. In the SRFF 202 of FIG. 25, CKOUT is high when SET is high, and CKOUT is low when RESET is high. A state in which SET and RESET are simultaneously high is prohibited. FIG. 26 is a timing chart showing the operation of FIG. In FIG. 26, SET and RESET are generated according to SETSEL and RESETSEL, respectively. Then, CKOUT rises at the rising edge of SET, and CKOUT falls at the rising edge of RESET. That is, by specifying SETSEL and RESETSEL, the phase and pulse width of CKOUT can be digitally controlled with reference to the multiphase clock. In particular, when the voltage control delay means (voltage control delay circuit) in the present invention is used as the multiphase CLK generation means 200, the clock phase can be controlled at a constant time interval regardless of manufacturing variations.

The present invention is applicable to a semiconductor integrated circuit.

It is a figure which shows the structure of a simple voltage control delay element. It is a figure which shows the clock waveform of each node. It is a figure which shows the structure which provided the variable current source also in the NchTr side so that the NchTr side and the PchTr side may become symmetrical. It is a figure which shows a control voltage-delay time characteristic. It is a figure which shows the control voltage-delay time characteristic of the voltage control delay element of three types of samples (sample1, sample2, sample3). It is a figure which shows the structural example of the voltage control delay means (voltage control delay circuit) used for the clock phase control apparatus which concerns on this invention. It is a figure which shows the flow of the transient electric current in a voltage control delay element. FIG. 4 is a diagram illustrating a graph in which a delay time is plotted with respect to a control voltage Vcont for the circuit of FIG. 3. FIG. 7 is a diagram illustrating a graph in which a delay time is plotted with respect to a control voltage Vcont for the circuit of FIG. 6. It is a figure which shows the structure at the time of making the resistance element of the voltage-current conversion part in FIG. 6 into a variable resistance. FIG. 11 is a diagram illustrating a voltage control delay circuit when the voltage control delay element has a differential configuration in the circuit of FIG. 10. It is a figure which shows the structure at the time of using the voltage control delay circuit of FIG. 6 for DLL. It is a figure which shows the structural example of XOR in FIG. It is a figure for demonstrating operation | movement of the multiplexer of FIG. It is a figure which shows the multiphase clock output cko in the state where Vcont was stable (the state where DLL was locked). FIG. 7 is a diagram showing another configuration example when the voltage control delay circuit of FIG. 6 is used in a DLL. It is a figure which shows the structural example of PD in FIG. It is a figure for demonstrating operation | movement of PD of FIG. It is a figure which shows the structural example of CP in FIG. FIG. 17 is a diagram illustrating ck0, ckn, upb, and dn in a state where Vcont of the DLL circuit of FIG. 16 is stable (a state where the DLL is locked). It is a figure which shows the structural example of the clock phase control apparatus of this invention. It is a figure which shows the structural example of a SET production | generation means. It is a figure which shows the structural example of a pulse delay circuit. 24 is a timing chart showing the operation of the SET generation means in the configuration of FIGS. 22 and 23. It is a figure which shows the structural example of SRFF. It is a timing chart which shows operation | movement of SRFF of FIG.

Explanation of symbols

108, 122 Voltage-current converter 110 Current source Tr
111 operational amplifier 112 resistance element 113 to 117 current source PchTr
118-121 NchTr
123 Differential voltage control delay element 1 stage 124, 125 PchTr
126, 127, 150 NchTr
128,135 VCDL
129 XOR
130,138 Filter
131 Multiplexer 132-134 Inverter 136 PD (Phase Comparator)
137 CP (charge pump)
139, 140 FF
141 NAND gate 142-144 Inverter 200 Multiphase CLK generating means 201 RESET generating means 202 SRFF
203 SET generation means 204 MUX
205 Pulse delay circuit 206, 207 Inverter 208, 209 NAND

Claims (7)

A clock phase control device having multi-phase clock generation means for generating a multi-phase clock when a high-frequency clock is inputted, wherein the multi-phase clock generation means has voltage control delay means, and the voltage control delay means includes: A control means for outputting a control current proportional to the current converted by the voltage-current converter, and a high-frequency clock for a time corresponding to the control current A clock phase control device comprising: delay means for outputting after delay, wherein the voltage-current converter has linear voltage-current conversion characteristics in a predetermined input voltage range. 2. The clock phase control device according to claim 1, wherein the clock phase control device further generates a set signal according to a set pulse and a set position selection signal based on the multiphase clock generated by the multiphase clock generation means. A signal generating means; a reset signal generating means for generating a reset signal according to a reset pulse and a reset position selection signal with reference to the multiphase clock; and an SR flip-flop for generating a phase-controlled clock according to the set signal and the reset signal And a clock phase control device. 2. The clock phase control device according to claim 1, wherein the voltage-current converter includes an operational amplifier and a resistance element, and converts an input control voltage into a current determined by a resistance value of the resistance element by a virtual short circuit of the operational amplifier. A clock phase control device. 4. The clock phase control device according to claim 3, wherein the resistance element is a variable resistor whose resistance value can be changed. 5. The clock phase control device according to claim 1, wherein the high-frequency clock is a differential signal, and the delay unit has a differential configuration corresponding to the differential signal. 6. A clock phase control device characterized by the above. 6. The clock phase control device according to claim 1, wherein the multiphase clock generation unit includes the voltage control delay unit, a first output signal of the voltage control delay unit, and a second output signal. And a phase comparator for comparing a phase difference between the output signal and a loop filter for receiving the output signal of the phase comparator and outputting a control voltage of the voltage control delay unit. Phase control device. 6. The clock phase control device according to claim 1, wherein the multiphase clock generation unit includes the voltage control delay unit, a first output signal of the voltage control delay unit, and a second output signal. A phase comparison means for comparing a phase difference with the output signal of the output signal; a charge pump means for converting the output signal of the phase comparison means into a current signal; an output signal of the charge pump means; A clock phase control apparatus comprising: a loop filter that outputs a control voltage.

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