JP2009004657A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device whose electrostatic protective circuit does not disturb the normal operation of internal circuit. <P>SOLUTION: The electrostatic protective circuit includes: an NW-NW field transistor 4 comprising a drain connected to an input/output terminal 10, and a metal electrode connected to a ground terminal 12 and formed on a source and an oxide film between the source and the drain and connected to the input/output terminal 10; and an electrostatic protective element 6 connected in parallel with the field transistor. The NW-NW field transistor 4 is set to start snap-back when a voltage larger than the operation voltage of the internal circuit 2 is applied between the input/output terminal 10 and the ground terminal 12, and to allow the operation voltage after snap-back to be larger than the operation voltage of the internal circuit 2. The electrostatic protective element 6 is set to be operated when a voltage is applied between the input/output terminal 10 and the ground terminal 12, which is larger than the operation voltage of the internal circuit and smaller than the voltage for the snap-back of the NW-NW field transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device provided with an electrostatic protection element for preventing electrostatic breakdown of an internal circuit.

An example in which a low voltage NMOS transistor is used as an electrostatic protection circuit as an electrostatic protection circuit for preventing electrostatic breakdown of the internal circuit 24 is shown in FIG.
The drain of the NMOS transistor 26 is connected to a pad electrode (PAD) 28 serving as an input / output terminal, and the source and gate electrodes of the NMOS transistor 26 are connected to a ground terminal (GND) 30.

FIG. 8 is a graph showing the voltage-current characteristics of this electrostatic protection circuit.
As shown in this figure, when a voltage higher than a certain voltage is applied to the drain side of the NMOS transistor, current starts to flow due to the operation of the NPN parasitic bipolar transistor existing between the drain and source, and the operating voltage Drops rapidly and causes a large current to flow. This phenomenon is called “snapback phenomenon”. The electrostatic protection circuit of a semiconductor device uses this “snapback phenomenon” and generates a snapback phenomenon when a voltage of a certain level or more is applied to the input / output terminals. By applying a current, the applied voltage and current to the internal circuit to be protected are reduced. Thereby, even when a sudden pulse voltage or pulse current is applied to the input / output terminal, the pulse voltage or pulse current is directly applied to the internal circuit so that the internal circuit is not destroyed.
In the following, “the snap phenomenon occurs” is also expressed as “snap back”.

  Similarly, when a high voltage NMOS transistor is used as an electrostatic protection circuit for protecting an internal circuit composed of a high voltage element, an NPN parasitic that exists between the drain and source when a voltage exceeding a certain level is applied. The bipolar transistor operates and snaps back. However, since the high breakdown voltage NMOS transistor has a high voltage at which the snapback starts, a large electric field is concentrated between the drain and the substrate of the NMOS transistor before the snapback starts, and at the same time the NMOS transistor Could be destroyed. FIG. 9 shows the voltage-current characteristic of this NMOS transistor. As can be seen from this characteristic, the snap-backed NMOS transistor cannot be used as an electrostatic protection circuit for protecting the internal circuit.

Therefore, it has been proposed that the electrostatic protection circuit is composed of NW-NW (N well-N well) field transistors (see, for example, Patent Documents 1 and 2). Since the NW-NW field transistor is not broken due to electric field concentration even after snapback due to its structure, the problems that occur in a high voltage NMOS transistor can be solved.
Japanese Patent Laid-Open No. 9-97844 JP 2005-94041 A

FIG. 10 shows the voltage-current characteristics of the NW-NW field transistor.
As can be seen from this figure, the NW-NW field transistor has a large decrease in operating voltage after snapback. When the operation voltage after snapback of the NW-NW field transistor is lower than the operation voltage of the internal circuit, a pulse voltage or pulse current is applied during the operation of the internal circuit, and the NW-NW field transistor snaps back. Then, the NW-NW field transistor is maintained in an operating state even though the subsequent applied voltage returns to the steady voltage for operating the internal circuit (hereinafter, this state is referred to as “malfunction”). ) Interferes with the normal operation of the internal circuit.

  Therefore, it may be possible to prevent malfunction of the NW-NW field transistor by increasing the breakdown voltage between the NW-NW and increasing the operation voltage after the NW-NW field transistor snaps back. When the operating voltage is increased, the voltage at which snapback starts increases, and there is a problem that a high voltage is applied to the internal circuit and is destroyed before the NW-NW field transistor starts to snap back.

  Accordingly, an object of the present invention is to prevent the electrostatic protection circuit from interfering with the normal operation of the internal circuit and to enhance the electrostatic protection function of the electrostatic protection circuit.

  The present invention relates to a semiconductor device including an electrostatic protection circuit connected between an input / output terminal or a power supply terminal and a ground terminal, the electrostatic protection circuit being connected to the input / output terminal or the power supply terminal and a drain. The first N-type diffusion layer, the second N-type diffusion layer connected to the ground terminal, and the metal electrode formed on the oxide film on both diffusion layers and connected to the input / output terminal or the power supply terminal. Alternatively, when a voltage larger than the steady voltage for operating the internal circuit is applied between the power supply terminal and the ground terminal, the snapback starts and the operating voltage after the snapback becomes larger than the steady voltage. And an electrostatic protection element connected in parallel to the field transistor between the input / output terminal or the power supply terminal and the ground terminal. It is set to operate when a voltage larger than the steady voltage for operating the internal circuit is applied between the terminal or the power supply terminal and the ground terminal and smaller than the voltage at which the field transistor starts to snap back. It is characterized by.

  The first example of the electrostatic protection element is a diode having a cathode connected to an input / output terminal or a power supply terminal and an anode connected to a ground terminal.

  When the electrostatic protection element is the diode, the first N-type diffusion layer is formed in the third N-type diffusion layer having a lower concentration, and the first P-type diffusion layer is formed in the third N-type diffusion layer. Preferably, the first N-type diffusion layer also serves as the cathode of the diode, and the first P-type diffusion layer serves as the anode of the diode. Then, the area of the formation region of the electrostatic protection circuit can be made smaller than in the case where the field transistor and the diode are formed in different regions, and the enlargement of the semiconductor device can be prevented.

  As a specific example for realizing the electrostatic protection circuit including the electrostatic protection element of the first example, the third N-type diffusion layer has a shape surrounding the second N-type diffusion layer in a plane parallel to the substrate surface. The first N type diffusion layer is also formed in a shape surrounding the second N type diffusion layer, and the first P type diffusion layer is formed in a shape surrounding the first N type diffusion layer. .

  Further, a fourth N-type diffusion layer is formed in the third N-type diffusion layer so as to surround the outer side of the first P-type diffusion layer at the same concentration as the first N-type diffusion layer. It may be connected to a terminal or a power supply terminal to serve as a cathode of a diode and also serve as a guard ring. By doing so, the function as an electrostatic protection element is enhanced by increasing the amount of current that can be passed through the diode, and from the element formed in another region to the electrostatic protection circuit by the action of the guard ring. It is possible to reduce an electrical influence or an electrical influence from the electrostatic protection circuit to an element formed in another region.

  As a second example of the electrostatic protection element, a PMOS transistor in which a source and a gate electrode are connected to an input / output terminal or a power supply terminal and a drain is connected to a ground terminal can be cited.

  When the electrostatic protection element is the above-described PMOS transistor, the first N-type diffusion layer is formed in the third N-type diffusion layer having a lower concentration, and the second N-type diffusion layer is included in the third N-type diffusion layer. And the third P-type diffusion layer is formed, and one of the second and third P-type diffusion layers serves as the source and drain of the PMOS transistor, and is on the substrate between the second P-type diffusion layer and the third P-type diffusion layer. It is preferable that a gate electrode is formed through a gate insulating film. By doing so, the area of the formation region of the electrostatic protection circuit can be made smaller than in the case where the field transistor and the PMOS transistor are formed in different regions, and enlargement of the semiconductor device can be prevented.

  As a specific example for realizing the electrostatic protection circuit including the electrostatic protection element of the second example, the third N-type diffusion layer surrounds the second N-type diffusion layer in a plane parallel to the substrate surface. The first N type diffusion layer is also formed in a shape surrounding the second N type diffusion layer, the second P type diffusion layer is formed in a shape surrounding the first N type diffusion layer, and the third P type diffusion layer is formed in the first P type diffusion layer. Examples thereof include those formed in a shape surrounding the outer side of the 2P type diffusion layer.

  Further, a fourth N-type diffusion layer is formed in the third N-type diffusion layer so as to surround the outer side of the third P-type diffusion layer at the same concentration as the first N-type diffusion layer. It may be connected to a terminal or a power supply terminal to form a guard ring. Then, due to the action of the guard ring, an electrical influence on the electrostatic protection circuit from an element formed in another region, or an element formed on the other region from the electrostatic protection circuit. Electrical influence can be reduced.

  The first N-type diffusion layer is formed in the third N-type diffusion layer having a lower concentration, and the second N-type diffusion layer is also formed in the fifth N-type diffusion layer having a lower concentration. The length of the third N-type diffusion layer existing under the oxide film in the channel length direction is set to be longer than the length of the fifth N-type diffusion layer existing under the oxide film in the channel length direction. Good.

A first feature of the semiconductor device according to the present invention is that snapback starts when a voltage larger than a steady voltage for operating the internal circuit is applied between the input / output terminal or the power supply terminal and the ground terminal, In addition, the field voltage set so that the operating voltage after snapback becomes larger than the above steady voltage and the steady voltage for operating the internal circuit between the input / output terminal or the power supply terminal and the ground terminal is larger than the steady voltage. An electrostatic protection circuit is configured by an electrostatic protection element set to operate when a voltage smaller than a voltage at which the field transistor starts to snap back is applied. Due to this feature, even if the field transistor is operated by the pulse voltage or pulse current during the operation of the internal circuit, the operation voltage after snapping back the field transistor is set larger than the steady voltage for operating the internal circuit. Therefore, the field transistor is not operated by a steady voltage for operating the internal circuit thereafter, and the normal operation of the internal circuit can be maintained.
In addition, when a voltage that is lower than the voltage at which the field transistor operates and is large enough to operate the electrostatic protection element, current due to the voltage flows through the electrostatic protection element without operating the field transistor. When the field transistor snaps back, sudden voltage fluctuation can be prevented.

The second feature of the semiconductor device according to the present invention is that the metal electrode on the oxide film on both diffusion layers forming the source and drain of the field transistor is connected to the input / output terminal or the power supply terminal. As a result, compared to the case where the metal electrode is not formed on the oxide film on both the diffusion layers forming the source and drain and the case where the metal electrode is connected to the ground terminal, the field transistor is snapped back. Only the voltage at which the field transistor starts to snap back can be reduced without significantly reducing the operating voltage of the transistor. If the voltage at which the field transistor begins to snap back decreases, the voltage applied to the internal circuit is reduced accordingly, so that the internal circuit can be prevented from being destroyed. Between the diffusion layers forming the source and drain of the field transistor The operating voltage of the field transistor decreases because the metal electrode on the oxide film is connected to the input / output terminal or the power supply terminal. The pulse voltage such as static electricity is applied to the metal electrode on the oxide film on both diffusion layers. When applied, the oxide film under the metal electrode instantaneously acts as a capacitor, current flows to charge the capacitor, and electrons are instantaneously drawn under the oxide film on both diffusion layers forming the source and drain. This is because a current flows between both diffusion layers by forming a channel.

[Example 1]
FIG. 1 is a circuit diagram schematically showing an embodiment of a semiconductor device.
The internal circuit 2 is connected between an input / output terminal (PAD) 10 and a ground terminal (GND) 12. An NW-NW field transistor 4 and a diode 6 as an electrostatic protection element are provided as an electrostatic protection circuit for preventing electrostatic breakdown of the internal circuit.

  The NW-NW field transistor 4 has a drain connected to the input / output terminal 10 and a source connected to the ground terminal 12. A metal gate is formed on the oxide film between the source and drain of the NW-NW field transistor 4, and the metal gate is also connected to the input / output terminal 10. The NW-NW field transistor 4 operates at a voltage higher than the operating voltage of the internal circuit 2 and is set so that the operating voltage after snapback is larger than the operating voltage of the internal circuit 2. Since the operation voltage after snapback of the NW-NW field transistor 4 is set to be larger than the operation voltage of the internal circuit 2, a pulse voltage or the like can be obtained when the internal circuit 2 is operated at a steady voltage. Even if the pulse current is applied and the NW-NW field transistor 4 operates, the NW-NW field transistor 4 does not operate if it returns to a steady voltage thereafter, so that the normal operation of the internal circuit 2 can be maintained.

  The diode 6 is connected in parallel with the NW-NW field transistor 4, the cathode is connected to the input / output terminal 10, and the anode is connected to the ground terminal 12. The diode 6 is set so that the avalanche breakdown occurs at a voltage larger than the operating voltage of the internal circuit 2 and smaller than the operating voltage of the NW-NW field transistor 4.

  Since the metal gate on the oxide film between the source and drain of the NW-NW field transistor 4 is electrically connected to the input / output terminal 10, a metal gate is formed on the oxide film between the source and drain. The voltage at which the NW-NW field transistor 4 starts to snap back is reduced compared to the case where the NW-NW field transistor 4 is not connected to the ground terminal 12.

  FIG. 6 shows voltage-current characteristics of the NW-NW field transistor when the metal gate on the oxide film between the source and drain of the NW-NW field transistor is connected to the input / output terminal and to the ground terminal. 6A shows voltage-current characteristics when a metal gate on the oxide film between the source and drain of the NW-NW field transistor is connected to the ground terminal, and FIG. 6B shows input / output of the metal gate. The voltage-current characteristics when connected to the terminal are shown. Comparing both characteristics, NW-NW is more when the metal gate is connected to the input / output terminal than when the metal gate on the oxide film between the source and drain of the NW-NW field transistor is connected to the ground terminal. The voltage at which the field transistor begins to snap back is reduced. On the other hand, the operating voltage after snapback is almost the same. That is, by connecting the metal gate on the oxide film between the source and drain to the input / output terminal, only the voltage at which the NW-NW field transistor starts to snap back compared to the case where the metal gate is connected to the ground terminal. Since it is possible to reduce the amount of voltage and the high voltage is less likely to be applied to the internal circuit, the internal circuit can be protected more safely.

  2A and 2B are diagrams showing an example of the structure of the electrostatic protection circuit in the semiconductor device of this embodiment. FIG. 2A is a cross-sectional view showing the structure, and FIG. 2B is a plan view showing an example of a layout for realizing the structure. FIG. In this figure, (A) is a cross-sectional view at the XX position of (B).

The structure of the electrostatic protection circuit of this embodiment will be described with reference to FIG.
A first N-type diffusion layer 1N serving as a drain of the NW-NW field transistor is formed in the third N-type diffusion layer 3N having a lower concentration than that of the substrate having a conductivity type of P-type (Psub). A fifth N-type diffusion layer 5N having the same concentration as the third N-type diffusion layer is formed in a region different from the third N-type diffusion layer 3N, and becomes the source of the NW-NW field transistor in the fifth N-type diffusion layer 5N. A second N type diffusion layer 2N having the same concentration as the first N type diffusion layer 1N is formed. The NW-NW field transistor composed of the first N-type diffusion layer 1N and the second N-type diffusion layer realizes the NW-NW field transistor 4 of FIG.

  A first P-type diffusion layer 1P serving as an anode of the diode is formed in a region different from the first N-type diffusion layer 1N in the third N-type diffusion layer 3N. In the first P-type diffusion layer 1P, a P + diffusion layer 1P 'having a higher concentration than the first P-type diffusion layer 1P is formed. The first N-type diffusion layer 1N also serves as the cathode of the diode, and the diode 6 of FIG. 1 is realized by the first N-type diffusion layer 1N and the first P-type diffusion layer 1P.

  A fourth N-type diffusion layer having the same concentration as the first and second N-type diffusion layers 1N and 2N at a position opposite to the first N-type diffusion layer 1N across the first P-type diffusion layer 1P in the third N-type diffusion layer 3N 4N is formed. The fourth N-type diffusion layer 4N also serves as a cathode of a diode having the first P-type diffusion layer 1P as an anode, and also serves as a guard ring for this electrostatic protection circuit.

  The diffusion layers 1N, 2N, 4N, and 1P 'are electrically separated by an oxide film 14 formed by, for example, a LOCOS (Local Oxidation Of Silicon) method.

  A metal wiring 20 is formed on the interlayer insulating film 16 on the first, second, and fourth N-type diffusion layers 1N, 2N, 4N, and the P + diffusion layer 1P '. The first, second, and fourth N-type diffusion layers 1N, 2N, 4N, and P + diffusion layer 1P ′ are electrically connected to the metal wiring 20 formed thereon through the through holes 18 formed in the interlayer insulating film 16. Connected. A metal gate 21 is formed on the interlayer insulating film 18 in a region between the third N-type diffusion layer 3N and the fifth N-type diffusion layer 5N.

  The first N-type diffusion layer 1N, the fourth N-type diffusion layer 4N, and the metal gate 21 are connected to the input / output terminals. The second N-type diffusion layer 2N and the P + diffusion layer 1P 'are connected to the ground terminal.

Each diffusion layer has a dose amount of 1.0 × 10 ^{12 to} 5.0 × 10 ¹² A / cm ² , a drive time of 3 to 20 hours, and a drive temperature of 1000 to 1300 ° C. according to the set breakdown voltage of the NW-NW field transistor. And set the conditions.
More specifically, the third N-type diffusion layer 3N and the fifth N-type diffusion layer 5N are implanted under the condition of a dose amount of 1.0 × 10 ^{12 to} 5.0 × 10 ¹² A / cm ^{2 using} arsenic or phosphorus as an implantation species. And it is formed by diffusing under conditions of a drive temperature of 1000-1300 ° C. for a drive time of 3-20 hours. The first N-type diffusion layer 1N, the second N-type diffusion layer 2N and the fourth N-type diffusion layer 4N are implanted under the condition of a dose of 1.0 × 10 ^{15 to} 8.0 × 10 ¹⁵ A / cm ^{2 using} arsenic or phosphorus as an implantation species. It is formed by injecting and diffusing under conditions of drive time of 0.5 to 2 hours and drive temperature of 600 to 1000 ° C. The first P-type diffusion layer is implanted with boron or BF ₂ as an implantation species at a dose of 1.0 × 10 ^{13 to} 8.0 × 10 ¹³ A / cm ² , a drive time of 0.5 to 5 hours, and a drive temperature. It is formed by diffusing under conditions of 800 to 1200 ° C. P + diffusion layer 1P ′ is implanted under the conditions of doses of 1.0 × 10 ^{15 to} 8.0 × 10 ¹⁵ A / cm ^{2 using} boron or BF ₂ as an implantation species, drive time of 0.5 to 2 hours, drive temperature It is formed by diffusing under conditions of 600 to 1000 ° C.

  As shown in FIG. 2B, the electrostatic protection circuit having such a structure can be formed such that each diffusion layer surrounds the second N-type diffusion layer 2N. In the layout shown in this figure, the third N type diffusion layer 3N is formed so as to surround the outside of the second N type diffusion layer 2N and the fifth N type diffusion layer 5N. The first N-type diffusion layer 1N is also formed so as to surround the outside of the fifth N-type diffusion layer 5N, and the first P-type diffusion layer 1P is formed so as to surround the outside of the first N-type diffusion layer 1N. The diffusion layer 4N is formed so as to surround the outer side of the first P-type diffusion layer 1P.

FIG. 3 shows the current-voltage characteristics of the electrostatic protection circuit of this example.
As can be seen from this voltage-current characteristic, in the electrostatic protection circuit of this embodiment, the NW-NW field transistor 4 starts to snap back at a voltage of about 100 V, and then the operating voltage rapidly decreases to 30 V or less. A large current flows by operating even with voltage, but before the NW-NW field transistor 4 snaps back, the diode 6 connected in parallel to the NW-NW field transistor 4 is ahead of the NW-NW field transistor 4. It operates to pass a certain amount of current.

  In the case where the electrostatic protection circuit is composed of only the NW-NW field transistor, as shown in FIG. 10, the electrostatic protection circuit is not completely applied unless a voltage higher than the voltage at which the NW-NW field transistor starts to snap back is applied. Since no current flows, a high voltage is applied to the internal circuit by applying a voltage until the NW-NW field transistor operates, and the internal circuit is destroyed. On the other hand, the electrostatic protection circuit of this embodiment having the characteristics shown in FIG. 3 is applied to the internal circuit by operating the diode 6 to flow current before the NW-NW field transistor 4 operates. Voltage and current can be reduced.

[Example 2]
Next, an embodiment using a PMOS transistor as an electrostatic protection element of the electrostatic protection circuit will be described. FIG. 4 is a circuit diagram schematically showing another embodiment of the semiconductor device.
The electrostatic protection circuit in the semiconductor device of this embodiment is provided with a PMOS transistor 7 instead of the diode 6 of the first embodiment (see FIG. 1). The source and gate electrodes of the PMOS transistor are connected to the input / output terminal 10, the drain is connected to the ground terminal 12, and is connected in parallel to the NW-NW field transistor 4. The PMOS transistor 7 is a parasitic transistor that exists in the structure when a voltage higher than the operating voltage of the internal circuit 2 and lower than the voltage at which the NW-NW field transistor 4 starts to snap back is applied to the input / output terminal. The PNP bipolar transistor is set to operate.
An example of a structure for realizing the electrostatic protection circuit of this embodiment is shown in FIG.

5A and 5B are diagrams for explaining an example of the structure of the electrostatic protection circuit in the semiconductor device shown in FIG. 4, in which FIG. 5A is a sectional view thereof, and FIG. 5B is a plan view showing an example of the layout. , (A) is a cross-sectional view at the YY position of (B).
A first N-type diffusion layer 1N serving as the drain of the NW-NW field transistor is formed in the third N-type diffusion layer 3N having a lower concentration than that of the substrate of the P-type conductivity type (Psub). A fifth N-type diffusion layer 5N having the same concentration as the third N-type diffusion layer is formed in a region different from the third N-type diffusion layer 3N, and the first N serving as the source of the NW-NW field transistor in the fifth N-type diffusion layer 5N. A second N type diffusion layer 2N having the same concentration as the type diffusion layer 1N is formed. The NW-NW field transistor composed of the first N-type diffusion layer 1N and the third N-type diffusion layer realizes the NW-NW field transistor 4 of FIG.

  The second P-type diffusion layer 2P serving as the source of the PMOS transistor and the third P-type diffusion layer 3P serving as the drain of the PMOS transistor are separated from each other in a region different from the first N-type diffusion layer 1N in the third N-type diffusion layer 3N. Is formed. The PMOS transistor composed of the second P-type diffusion layer 2P and the third P-type diffusion layer 3P realizes the PMOS transistor 7 in FIG.

  The first and second guard rings of the electrostatic protection element are arranged at positions opposite to the first N-type diffusion layer 1N across the second P-type diffusion layer 2P and the third P-type diffusion layer in the third N-type diffusion layer 3N. A fourth N-type diffusion layer 4N having the same concentration as the second N-type diffusion layers 1N and 2N is formed. A P + diffusion layer 2P ′ having a higher concentration than the second P-type diffusion layer 2P is formed in the second P-type diffusion layer 2P, and a higher concentration than the third P-type diffusion layer 3P in the third P-type diffusion layer 3P. P + diffusion layer 3P ′ is formed. The diffusion layers 1N, 2N, 4N, 2P 'and 3P' are electrically separated by an oxide film 14 formed by, for example, the LOCOS method.

  A metal wiring 20 is formed on the interlayer insulating film 16 on the first, second and fourth N-type diffusion layers 1N, 2N and 4N and the P + diffusion layers 2P 'and 3P'. The first, second, and fourth N-type diffusion layers 1N, 2N, and 4N, and the P + diffusion layers 1P ′ and 2P ′ are metal wirings formed thereon through through holes 18 formed in the interlayer insulating film 16, respectively. 20 is electrically connected. A metal gate 21 is formed on the interlayer insulating film 18 in a region between the third N-type diffusion layer 3N and the fifth N-type diffusion layer 5N. Further, a gate electrode 22 made of, for example, polysilicon is formed on a region between the second P-type diffusion layer 2P and the third P-type diffusion layer 3P via a gate oxide film.

  The first N-type diffusion layer 1N, the fourth N-type diffusion layer 4N, the P + diffusion layer 2P ', the metal gate 21, and the gate electrode 22 are connected to the input / output terminals. The second N-type diffusion layer 2N and the P + diffusion layer 3P 'are connected to the ground terminal.

The third N-type diffusion layer 3N and the fifth N-type diffusion layer 5N are implanted under the condition of a dose of 1.0 × 10 ^{12 to} 5.0 × 10 ¹² A / cm ^{2 using} arsenic or phosphorus as an implantation species, and a drive time of 3 It is formed by diffusing at a drive temperature of 1000 to 1300 ° C. for 20 hours. The first N-type diffusion layer 1N, the second N-type diffusion layer 2N, and the fourth N-type diffusion layer 4N are implanted under the condition of a dose of 1.0 × 10 ^{15 to} 8.0 × 10 ¹⁵ A / cm ^{2 using} arsenic or phosphorus as an implantation species. It is formed by injecting and diffusing under conditions of drive time of 0.5 to 2 hours and drive temperature of 600 to 1000. The first P-type diffusion layer 1P and the second P-type diffusion layer 2P are implanted under the condition of a dose amount of 1.0 × 10 ^{13 to} 8.0 × 10 ¹³ A / cm ^{2 using} boron or BF ₂ as an implantation species, and a drive time of 0 It is formed by diffusing at a drive temperature of 800 to 1200 ° C. for 5 to 5 hours. P + diffusion layers 1P ′ and 2P ′ are implanted under the conditions of a dose of 1.0 × 10 ^{15 to} 8.0 × 10 ¹⁵ A / cm ^{2 using} boron or BF ₂ as an implantation species, and a drive time of 0.5 to 2 hours. , And formed by diffusing under conditions of a drive temperature of 600 to 1000 ° C.
The channel region of this PMOS transistor is implanted under the condition of a dose of 1.0 × 10 ^{11 to} 8.0 × 10 ¹¹ A / cm ² using arsenic or phosphorus as an implantation species, and the drive time is 0.5 to 2 hours. It is formed by diffusing at a temperature of 600 to 1000.

  The electrostatic protection circuit shown in this embodiment can also be formed such that each diffusion layer surrounds the second N-type diffusion layer 2N as shown in FIG. 5B. In the layout shown in this figure, the third N type diffusion layer 3N is formed so as to surround the outside of the second N type diffusion layer 2N and the fifth N type diffusion layer 5N. The first N-type diffusion layer 1N is also formed so as to surround the outside of the fifth N-type diffusion layer 5N, and the second P-type diffusion layer 2P is formed so as to surround the outside of the first N-type diffusion layer 1N. The diffusion layer 3P is formed so as to surround the outer side of the second P-type diffusion layer 2P, and the fourth N-type diffusion layer 4N is formed so as to surround the outer side of the first P-type diffusion layer 1P.

  Also in the electrostatic protection circuit of this embodiment, when a voltage lower than the voltage at which the PMOS transistor 7 is higher than the operating voltage of the internal circuit 2 and the NW-NW field transistor 4 starts to snap back is applied to the input / output terminal. Since the parasitic PNP bipolar transistor existing in the structure is set to operate, the PMOS transistor 7 is turned on when a voltage lower than the voltage at which the NW-NW field transistor 4 starts to snap back is applied. It operates so as to pass a current and prevent a high voltage from being applied to the internal circuit 2. Further, since the operating PMOS transistor can increase the amount of current to flow per unit area as compared with the operating diode, a larger pulse can be generated without causing the NW-NW field transistor 4 to malfunction during the operation of the internal circuit 2. A current can flow, and the normal operation of the internal circuit 2 can be maintained.

In this embodiment, the P + diffusion layer 2P ′ of FIG. 5B is connected to the input / output terminal via the metal electrode 20, and the P + diffusion layer 3P ′ is connected to the ground terminal via the metal electrode 20. On the contrary, the P + diffusion layer 3P ′ may be connected to the input / output terminal, and the P + diffusion layer 2P ′ may be connected to the ground terminal.
The numerical values shown in this specification are merely examples, and can be changed according to the withstand voltage of the designed internal circuit and electrostatic protection circuit.

  In the above embodiment, the case where the electrostatic protection circuit is connected between the input / output terminal and the ground terminal has been described. However, the electrostatic protection circuit is also connected between the power terminal and the ground terminal and applied through the power terminal. The internal circuit can be protected from static electricity.

It is a circuit diagram which shows roughly one Example of a semiconductor device. It is a figure which shows concretely the structure of the electrostatic protection circuit of the Example, (A) is sectional drawing, (B) is a top view which shows an example of the layout, (A) is X of (B) It is sectional drawing in -X position. It is a graph which shows the voltage-current characteristic of the electrostatic protection circuit of the Example. It is a circuit diagram which shows schematically the other Example of a semiconductor device. It is a figure which shows concretely the structure of the electrostatic protection circuit of the Example, (A) is sectional drawing, (B) is a top view which shows an example of the layout, (A) is X of (B) It is sectional drawing in -X position. It is a graph which shows the current-voltage characteristic of a NW-NW field transistor, (A) is when the metal gate on the area | region between a source and a drain is connected to a ground terminal, (B) is the same metal gate as an input-output terminal. This is the case when connected. It is a circuit diagram which shows roughly an example of the structure of the conventional semiconductor device. It is a graph which shows the voltage-current characteristic of the NMOS transistor by which the gate electrode was connected to the ground terminal. It is a graph which shows the voltage-current characteristic of the high voltage | pressure-resistant NMOS transistor after being destroyed. It is a graph which shows the current-voltage characteristic of a NW-NW field transistor.

Explanation of symbols

2 Internal circuit 4 NW-NW field transistor 6 Diode 7 PMOS transistor 10 Pad electrode 12 Ground terminal 14 LOCOS oxide film 16 Interlayer insulating film 20 Metal wiring 21 Metal gate 22 Polysilicon gate 1N, 2N, 3N, 4N, 5N N-type diffusion Layer 1P, 1P ′, 2P, 2P ′, 3P, 3P ′ P-type diffusion layer

Claims (10)

In a semiconductor device including an electrostatic protection circuit connected between an input / output terminal or a power supply terminal and a ground terminal,
The electrostatic protection circuit is formed on a first N-type diffusion layer connected to an input / output terminal or a power supply terminal and serving as a drain, a second N-type diffusion layer connected to a ground terminal and serving as a source, and an oxide film on both diffusion layers. It consists of a metal electrode connected to the input / output terminal or power supply terminal, and snaps back when a voltage larger than the steady voltage for operating the internal circuit is applied between the input / output terminal or power supply terminal and the ground terminal. A field transistor set so that the operating voltage after starting and snapping back becomes larger than the steady voltage, and a static transistor connected in parallel to the field transistor between the input / output terminal or the power supply terminal and the ground terminal. Equipped with electrical protection elements,
When the electrostatic protection element is applied with a voltage larger than a steady voltage for operating the internal circuit between an input / output terminal or a power supply terminal and a ground terminal and smaller than a voltage at which the field transistor starts to snap back. A semiconductor device characterized in that the semiconductor device is set to operate.   2. The semiconductor device according to claim 1, wherein the electrostatic protection element is a diode having a cathode connected to an input / output terminal or a power supply terminal and an anode connected to a ground terminal. The first N type diffusion layer is formed in the third N type diffusion layer having a lower concentration than that, and the first P type diffusion layer is formed in the third N type diffusion layer.
The semiconductor device according to claim 2, wherein the first N-type diffusion layer also serves as a cathode of the diode, and the first P-type diffusion layer serves as an anode of the diode. In a plane parallel to the substrate surface, the third N-type diffusion layer is formed in a shape surrounding the second N-type diffusion layer,
The first N-type diffusion layer is also formed in a shape surrounding the second N-type diffusion layer,
The semiconductor device according to claim 3, wherein the first P-type diffusion layer is formed in a shape surrounding the outer side of the first N-type diffusion layer.   A fourth N-type diffusion layer is formed in the third N-type diffusion layer so as to surround the outer side of the first P-type diffusion layer at the same concentration as the first N-type diffusion layer. The semiconductor device according to claim 4, wherein the semiconductor device is connected to a power supply terminal to serve as a cathode of the diode and also serves as a guard ring.   2. The semiconductor device according to claim 1, wherein the electrostatic protection element is a PMOS transistor having a source and a gate electrode connected to an input / output terminal or a power supply terminal, and a drain connected to a ground terminal. The first N type diffusion layer is formed in the third N type diffusion layer having a lower concentration than that,
A second P-type diffusion layer and a third P-type diffusion layer are formed in the third N-type diffusion layer, and one of the second and third P-type diffusion layers is the source of the PMOS transistor and the other is the drain.
The semiconductor device according to claim 6, wherein the gate electrode is formed on a substrate between the second P-type diffusion layer and the third P-type diffusion layer via a gate insulating film. In a plane parallel to the substrate surface, the third N-type diffusion layer is formed in a shape surrounding the second N-type diffusion layer,
The first N-type diffusion layer is also formed in a shape surrounding the second N-type diffusion layer,
The second P-type diffusion layer is formed in a shape that further surrounds the first N-type diffusion layer,
The semiconductor device according to claim 7, wherein the third P-type diffusion layer is formed in a shape surrounding the outer side of the second P-type diffusion layer.   A fourth N-type diffusion layer is formed in the third N-type diffusion layer so as to surround the outer side of the third P-type diffusion layer at the same concentration as the first N-type diffusion layer. The semiconductor device according to claim 8, wherein the semiconductor device is connected to a power supply terminal to form a guard ring. The first N-type diffusion layer is formed in the third N-type diffusion layer having a lower concentration, and the second N-type diffusion layer is also formed in the fifth N-type diffusion layer having a lower concentration than that,
In the field transistor, the length in the channel length direction of the third N type diffusion layer existing under the oxide film is longer than the length in the channel length direction of the fifth N type diffusion layer existing under the oxide film. The semiconductor device according to claim 1, wherein the semiconductor device is set.

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