JP2009004635A - Semiconductor integrated circuit and method of designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit etc. that has attained coexistence of the efficiency of noise removal and area efficiency. <P>SOLUTION: In the semiconductor integrated circuit 100, there are provided a first circuit block 101 having a relatively high operating frequency, a second circuit block 102 having a relatively low operating frequency, a first MOS-type decoupling capacitive element F connected to a wire that supplies a power source to the first circuit block and having a relatively small dimension between source and drain, and a second MOS-type decoupling capacitive element A connected to a wire that supplies a power source to the second circuit block and having a relatively large dimension between source and drain compared to that of the first MOS-type decoupling capacitive element. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a method for designing a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a decoupling capacitor and a method for designing a semiconductor integrated circuit.

  A decoupling capacitance element for absorbing power supply noise of a semiconductor integrated circuit has been integrated in the semiconductor integrated circuit as the operating frequency is increased. For example, Patent Document 1 discloses a semiconductor device having a capacitive element for noise suppression and a pattern generation method thereof.

  FIG. 10 is a diagram illustrating a structure of a capacitive element arranged in a conventional semiconductor device. FIG. 10 shows three types of MOS capacitors having different structures arranged in the semiconductor device, from part (a) to part (c).

The capacitive element 70 shown in part (a) of FIG. 10 has the same structure as a general MOS transistor. This type of capacitive element is referred to as a basic capacitive element. The capacitor element 70 functions as a capacitor by forming a channel in a region 71 indicated by a broken line below the gate electrode 72. In the capacitive element 80 shown in part (b) of FIG. 10, the other diffusion layer 82 is formed in an island shape at the center of one diffusion layer 81 formed in an annular shape. A ring-shaped gate electrode 83 is formed so as to cover the ring-shaped region therebetween. A capacitor is formed under the ring-shaped gate electrode 83. This type of capacitive element is referred to as a ring gate type capacitive element. In the capacitive element 90 shown in part (c) of FIG. 10, the diffusion layer 91 is formed in a ring shape, and the gate electrode 93 having a shape covering the region 92 surrounded by the ring-shaped diffusion layer 91 is formed. . A capacitor is formed under the gate electrode 93. This type of capacitive element is referred to as a flat capacitive element. In the pattern generation method disclosed in Patent Document 1, a plurality of flat plate capacitive elements having a large capacitance per unit area are arranged in an array for the purpose of increasing the capacitance in a portion that operates at a high frequency in the semiconductor device. Be placed.
JP 2002-246548 A

  However, the flat capacitor shown in part (c) of FIG. 10 has a structure in which the gate electrode and the power supply wiring are connected above the region where the channel is formed. It is not easy to manufacture. For this reason, flat capacitor elements are rarely used in actual semiconductor devices, and basic capacitor elements are exclusively used.

  In addition, the capacitance in an actual capacitive element has frequency characteristics, and the capacitance decreases as the frequency increases. Therefore, simply increasing the area in which the capacitor is formed or increasing the number of capacitive elements may not provide the capacitance expected at the time of design in the high frequency region, and high frequency noise may not be removed. There is a problem that sufficient performance as a semiconductor device cannot be exhibited.

  In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit and a method for designing a semiconductor integrated circuit in which both noise removal efficiency and area efficiency are achieved.

The semiconductor integrated circuit of the present invention that achieves the above object includes a first circuit block having a relatively high operating frequency, a second circuit block having a relatively low operating frequency,
A first MOS type decoupling capacitance element having a relatively small source-drain dimension connected to a wiring for supplying power to the first circuit block;
A second MOS type decoupling capacitive element having a larger source-drain dimension than the first MOS type decoupling capacitive element, connected to a wiring for supplying power to the second circuit block; It is characterized by having.

  In the semiconductor integrated circuit according to the present invention, a first MOS type decoupling capacitor element having a small source-drain dimension is connected to a wiring for supplying power to a first circuit block having a high operating frequency, so that the operating frequency is low. A first MOS type decoupling capacitance element having a large source-drain dimension is connected to a wiring for supplying power to the second circuit block having. Since the first MOS type decoupling capacitance element has a small source-drain dimension and the change in channel charge can follow the fluctuation of the power supply voltage at a high frequency, high-frequency noise can be efficiently removed. On the other hand, in the second circuit block that operates at a low frequency, the MOS type decoupling capacitance element having a large source-drain dimension is arranged, so that the area efficiency per capacitance is improved. Therefore, it is possible to achieve both high area efficiency and noise removal in a wide frequency band.

Here, in the semiconductor integrated circuit of the present invention, the structures of both the first MOS type decoupling capacitance element and the second MOS type decoupling capacitance element are formed in an active region provided on the surface of the semiconductor substrate, The MOS transistor has a structure including a gate electrode that overlaps the active region via a capacitive insulating film and covers the active region and extends in one direction.
It is preferable that the dimension between the source and the drain is a dimension in a direction perpendicular to the one direction of the gate electrode.

  By using a highly versatile MOS transistor structure, it is possible to easily manufacture a semiconductor integrated circuit that achieves both high area efficiency and noise removal in a wide frequency band. In addition, since both the first MOS type decoupling capacitance element and the second MOS type decoupling capacitance element have the same structure, it is necessary to introduce a complicated manufacturing process to cope with different frequency characteristics. Can be done without.

Also, a first semiconductor integrated circuit design method of the present invention that achieves the above object is provided with a plurality of circuit blocks and a power supply provided corresponding to each of the plurality of circuit blocks and supplied to the corresponding circuit block. A method of designing a semiconductor integrated circuit having a decoupling capacitor that reduces noise of
The data including the operating frequency of each of the plurality of circuit blocks is recorded in a database, the pattern data of the first MOS type decoupling capacitance element having a relatively small source-drain dimension, and the first data Recording pattern data of a second MOS type decoupling capacitance element having a relatively larger source-drain dimension than the MOS type decoupling capacitance element in a database;
The plurality of circuit blocks are arranged in the chip area of the semiconductor integrated circuit, and the operation frequency of the circuit block is higher than a predetermined value at a position corresponding to each of the arranged circuit blocks. Disposing a first MOS type decoupling capacitance element, and disposing the second MOS type decoupling capacitance element when the operating frequency is a predetermined value or less;
Arranging a power supply wiring for supplying power to each of the plurality of arranged circuit blocks so that decoupling capacitance elements arranged at positions corresponding to the plurality of circuit blocks are connected to each other. It is characterized by.

  According to the first method for designing a semiconductor integrated circuit of the present invention, it is possible to design a semiconductor integrated circuit that achieves both high area efficiency and noise removal in a wide frequency band.

Also, a second semiconductor integrated circuit design method of the present invention that achieves the above object is provided with a plurality of circuit blocks and a power supply provided corresponding to each of the plurality of circuit blocks and supplied to the corresponding circuit block. A method of designing a semiconductor integrated circuit having a decoupling capacitor that reduces noise of
Data including the operating frequencies of the plurality of circuit blocks is recorded in a database, and pattern data and response frequency data of a plurality of MOS type decoupling capacitance elements having different source-drain dimensions are stored in the database. Recording step;
The plurality of circuit blocks are arranged in the chip region of the semiconductor integrated circuit, and the lowest response frequency that is equal to or higher than the circuit block operating frequency is provided at a position corresponding to each of the arranged circuit blocks. Disposing a MOS type decoupling capacitance element having;
Arranging a power supply wiring for supplying power to each of the plurality of arranged circuit blocks so that decoupling capacitance elements arranged at positions corresponding to the plurality of circuit blocks are connected to each other. According to the second method for designing a semiconductor integrated circuit of the present invention, the MOS type decoupling capacitance element having the best area efficiency is arranged according to the operating frequency of each circuit block.

  As described above, according to the present invention, a semiconductor integrated circuit and a method for designing a semiconductor integrated circuit in which noise removal efficiency and area efficiency are compatible can be realized.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing an example of the structure of a MOS type decoupling capacitance element integrated in a semiconductor integrated circuit according to an embodiment of the present invention. Part (a) of FIG. 1 is a plan view of a MOS type decoupling capacitance element viewed perpendicularly to the semiconductor substrate surface of the semiconductor integrated circuit, and part (b) of FIG. FIG.

  A MOS type decoupling capacitive element 10 (hereinafter referred to as MOS capacitive element 10) shown in FIG. 1 is a basic capacitive element having the same structure as a general n-channel MOS transistor. The MOS capacitor element 10 includes a substantially rectangular source 12 and drain 13 each made of an N diffusion layer, which are formed side by side in a P well 11a on the surface of a P-type semiconductor substrate 11, and a source 12 on the surface of the P well 11a. A gate electrode 16 is formed on an active region 14 between the drain 13 and an oxide insulating film 15 so as to overlap with each other. The gate electrode 16 covers the active region 14 and extends long in one direction, that is, a direction substantially perpendicular to the direction connecting the source 12 and the drain 13. A gate contact 17 connected to the power supply wiring is formed at one end of the gate electrode 16 that is off the active region 14. A source contact 18 and a drain contact 19 are also formed on the respective surfaces of the source 12 and the drain 13. In FIG. 1B, the illustration of contacts is omitted, and each contact is shown as an electrical wiring.

  When the source contact 18 and the drain contact 19 of the MOS capacitor 10 shown in FIG. 1 are connected to the ground wiring and the gate contact 17 is connected to the power supply wiring, the active region 14 indicated by a broken line in part (a) of FIG. A channel is formed on the surface of the substrate. The oxide insulating film 15 functions as a capacitive insulating film, and the MOS capacitive element 10 functions as a capacitive element. The dimension of the gate electrode 16 in the direction connecting the source 12 and the drain 13 is referred to as a gate length L. The dimension of the portion overlapping the active region 14 in the direction in which the gate electrode 16 extends, that is, the direction perpendicular to the direction connecting the source 12 and the drain 13 is referred to as the gate width W. Here, the gate length L, which is a physical dimension of the gate electrode 16, and the distance between the source 12 and the drain 13 do not exactly match. However, when the source 12 and the drain 13 are formed by a standard process in which ion implantation is performed using the gate electrode 16 as a mask, both are substantially equal. In this sense, the gate length L corresponds to an example of a source-drain dimension according to the present invention.

  In addition to the MOS capacitor 10 shown in FIG. 1, the semiconductor integrated circuit of the present embodiment includes a plurality of types of MOS having the same basic structure as the MOS capacitor 10 and having different gate lengths L and gate widths W. The capacitive element 10 is integrated. The capacitance of the MOS capacitor element 10 basically depends on the product of the gate length L and the gate width W. However, this capacity also has frequency dependence.

  FIG. 2 is a graph showing frequency characteristics of the MOS capacitor of the type shown in FIG.

  The graph of FIG. 2 shows each of the six types of MOS capacitance elements having the basic structure shown in FIG. 1 and having different gate lengths L, with a capacitance measurement value for a 1 MHz signal as a reference (= 1), and each frequency. The value (C / C @ 1MHz) which normalized the capacity | capacitance measured value in is shown. The gate lengths L of the six types of MOS capacitor elements are 0.4 μm, 2.0 μm, 4.0 μm, 10.0 μm, 20.0 μm, and 40.0 μm, respectively.

  As shown in the graph of FIG. 2, the capacitance of the MOS capacitance element decreases as the signal frequency increases regardless of the gate length. This means that the ability to absorb high frequency power noise is reduced when connected to power wiring. However, as the MOS capacitance element has a shorter gate length L, a higher capacitance is maintained up to a higher frequency. Here, in each MOS capacitor element, the upper limit of a practical frequency range in which the capacitance at a low frequency is maintained is defined as a response frequency. In the present embodiment, a frequency at which the capacitance of a certain MOS capacitive element is 80% of the capacitance at 1 MHz near DC is set as the response frequency of the MOS capacitive element. For example, the response frequency of a MOS capacitor having a gate length L of 0.4 μm shown in the graph of FIG. 2 is about 350 MHz. The response frequency of the MOS capacitor element with a gate length L of 2.0 μm is about 110 MHz, the response frequency of the MOS capacitor element with a gate length L of 4.0 μm is about 60 MHz, and the gate length L is 10.0 μm. The response frequency of the MOS capacitor element is about 30 MHz, the response frequency of the MOS capacitor element with a gate length L of 20.0 μm is about 18 MHz, and the response frequency of the MOS capacitor element with a gate length L of 40.0 μm is about 10 MHz. is there. A MOS capacitor element having a shorter gate length L has a higher response frequency.

  On the other hand, the capacity of one MOS capacitor having a short gate length L is small. However, by connecting a plurality of such MOS capacitor elements in parallel, a MOS capacitor having a capacity (at a low frequency) equal to that of a MOS capacitor element having a long gate length L is maintained up to a high frequency. An element can be realized.

  FIG. 3 is a diagram showing a structure of an array of MOS capacitor elements in which a plurality of MOS capacitor elements shown in FIG. 1 are arranged.

  In the array of FIG. 3, 16 MOS capacitive elements 10 are arranged in a matrix on the surface of a semiconductor substrate 11 (see FIG. 1). In this way, a desired capacitance can be obtained by electrically connecting a plurality of MOS capacitor elements 10 in parallel. In addition, the capacity is maintained up to a higher frequency as compared with the case where the same capacity is realized by one large MOS capacitor element.

  On the other hand, in the MOS capacitive element 10 having the structure shown in FIG. 1, the longer the gate length L, the smaller the proportion of the contact portion, and the larger the proportion of the active region 14 (see FIG. 1) in the entire MOS capacitive element. Therefore, the area efficiency is higher as the gate length L is longer. That is, a large capacity can be obtained when an array is formed in the same area.

  FIG. 4 shows that for the six types of MOS capacitance elements shown in FIG. 2, when the gate length L is 40 μm, the area of the MOS capacitance element is 1, and a capacitance equal to the capacitance of this MOS capacitance element is set for each gate length. It is a table | surface which shows ratio of the area required to obtain. As shown in FIG. 4, the shorter the gate length L, the larger the area required to obtain a certain capacity.

  In the semiconductor integrated circuit of the present embodiment, a noise reduction efficiency and an area efficiency are obtained by connecting a MOS capacitance element having an appropriate gate length L according to the operating frequency of each circuit block to each of a plurality of integrated circuit blocks. And coexistence is achieved.

For example, a set of selectable capacitor elements consisting of all or a part of the following six types of MOS capacitor elements is prepared, and a type of MOS corresponding to the operating frequency for each circuit block is prepared from this set. A capacitive element is selected. Then, an array is configured by connecting a plurality of MOS capacitor elements in parallel so as to obtain a capacity required for design.
MOS capacitance element A: gate length L = 40 μm, gate width W = 40 μm
MOS capacitance element B: gate length L = 20 μm, gate width W = 20 μm
MOS capacitance element C: gate length L = 10 μm, gate width W = 10 μm
MOS capacitance element D: gate length L = 4 μm, gate width W = 4 μm
MOS capacitance element E: gate length L = 2 μm, gate width W = 4 μm
MOS capacitance element F: gate length L = 0.4 μm, gate width W = 4 μm
These six types of MOS capacitance elements have the response frequencies described with reference to FIG. 2 according to their gate lengths.

  In the MOS capacitor, the aspect ratio, that is, the ratio between the gate length L and the gate width W is preferably close to 1: 1 in terms of arrangement efficiency. However, in the MOS capacitive element of this embodiment, when the gate width W is 4 μm or less, the widths of the source contact 18 and drain contact 19 (see FIG. 1) need to be increased, so the layout efficiency decreases. And not practical. Therefore, the gate width W of the MOS capacitor element E and the MOS capacitor element F is 4 μm, which is the same as that of the MOS capacitor element D, regardless of the gate length L.

  FIG. 5 is a layout diagram showing an embodiment of a semiconductor integrated circuit according to the present invention.

  A semiconductor integrated circuit 100 shown in FIG. 5 is realized as a semiconductor device formed on the surface of a semiconductor substrate, and has a large number of circuit elements. These circuit elements are arranged in a substantially rectangular chip region 100a on the semiconductor substrate. The semiconductor integrated circuit 100 is roughly composed of five circuit blocks 101 to 105 from an A block 101 to an E block 105. These blocks are divided and arranged in the chip region 100a, and each circuit block is provided with a wiring (not shown) for supplying power to the circuit block. The four circuit blocks 101 to 104 from the A block 101 to the D block 104 are respectively arranged on the four corner sides of the chip region 100a. These four circuit blocks 101 to 104 exchange signals with each other via the E block 105. The E block 105 is arranged across the chip region 100a in a cross. Of the five blocks, the A block 101 and the D block 104 operate at a relatively high operating frequency relative to the remaining three blocks. The A block 101 and the D block 104 are examples of the first circuit block according to the present invention, and the remaining B block 102, C block 103, and E block 105 are examples of the second circuit block according to the present invention. It is.

  A MOS capacitor element F having a short gate length L is connected to each of a wiring for supplying power to the A block 101 having a high operating frequency and a wiring for supplying power to the D block 104. On the other hand, the remaining block B102, block C103, and block E105 are connected to a MOS capacitor element A having a gate length L that is relatively longer than that of the MOS capacitor element F and a gate width W that is also relatively long. .

  The MOS capacitor element F having a short gate length L efficiently removes high frequency noise generated in the A block 101 and the D block 104. On the other hand, the MOS capacitor A having a long gate length L has high area efficiency. For this reason, the area increase of the block B102, the block C103, and the block E105 is suppressed. Low frequency noise generated in the block B102, the block C103, and the block E105 is efficiently removed by the MOS capacitor element A connected to the power supply wiring of each circuit block. In the semiconductor integrated circuit 100 as a whole, a sufficient decoupling capacitance is ensured, and the stability of the power supply and the ground potential is increased. Thus, high area efficiency and noise removal in a wide frequency band are compatible, contributing to improvement of the characteristics of the semiconductor device.

  In the embodiment described above, each block of the semiconductor integrated circuit 100 operates at either one of the high or low operating frequencies. However, the operating frequency of each block of the semiconductor integrated circuit may be three or more.

  FIG. 6 is a layout diagram showing an embodiment of a semiconductor integrated circuit different from FIG.

  In the following description of the second embodiment, the same reference numerals are given to the same elements as those in the embodiments described so far, and differences from the above-described embodiment will be described.

  The semiconductor integrated circuit 200 shown in FIG. 6 includes five circuit blocks, that is, an A block 101, a B block 102, a C block 103, a D block 201, and an E block 105. These blocks are divided and arranged in the chip region 200a, and each block is provided with wiring (not shown) for supplying power. In the semiconductor integrated circuit 200 shown in FIG. 6, the D block 201 among the five circuit blocks operates at an intermediate operating frequency between the A block 101 and the C block 103. The wiring for supplying power to the D block 201 includes a MOS capacitor having a gate length L that is intermediate between the MOS capacitor element F and the MOS capacitor element A among the six types of MOS capacitor elements described above. Element C is connected.

  As in the semiconductor integrated circuit 200 shown in FIG. 6, even when the operation frequency of the circuit block is three or more, it is possible to achieve both high area efficiency and noise removal in a wide frequency band.

  Next, a method for designing a semiconductor integrated circuit according to the second embodiment of the present invention will be described.

  FIG. 7 is a block diagram showing a schematic configuration of a design system that realizes the semiconductor integrated circuit design method according to the second embodiment of the present invention.

  A design system 300 shown in FIG. 7 is realized by, for example, an engineering workstation or a personal computer on which design tool software is executed. The design system 300 includes a design execution unit 310 that executes each function of design, and a database 320 that stores data necessary for the design.

  The design execution unit 310 has hardware such as a CPU and a memory, and these hardware and software executed there cooperate to realize the function of each tool. The design execution unit 310 includes a floor plan tool 311, a layout tool 312, a decoupling capacitance arrangement tool 313, and a mask creation tool 314. The design execution unit 310 is also provided with a design tool such as a logic synthesis tool (not shown). The database 320 includes a storage device such as a hard disk and stores input / output data of each tool of the design execution unit 310. The database 320 stores circuit block data 321 and decoupling capacitance element data 322. In the design system 300, each tool of the design execution unit 310 operates in order to design a semiconductor integrated circuit.

  FIG. 8 is a flowchart showing a design method for designing a semiconductor integrated circuit by the design system 300 shown in FIG. A design method of the semiconductor integrated circuit 200 shown in FIG. 6 will be described with reference to FIGS.

  In designing by the design system 300, first, a circuit block database is prepared (step S1). More specifically, based on the logic specifications of the semiconductor integrated circuit to be designed, the logic synthesis tools are A block 101, B block 102, C block 103, D block 201, and E block 105 shown in FIG. Logic synthesis is performed on two circuit blocks to generate netlist data. The netlist data is recorded in the database 320 as circuit block data 321 including the operating frequency data of the circuit block. Alternatively, data of macrocells such as a memory and a CPU prepared in advance, including the data of the operating frequency, is stored as circuit block data 321. In this step, pattern data and response frequency data of a plurality of types of MOS capacitor elements are recorded in the database 320 as decoupling capacitor element data 322. In the present embodiment, among the above-described set of six types of MOS capacitor elements, the MOS capacitor element A having a response frequency of 10 MHz, the MOS capacitor element C having a response frequency of 30 MHz, and the MOS capacitor having a response frequency of 350 MHz. Data is stored for the three types of MOS capacitance elements of the element F. Further, pattern data of circuit elements other than the MOS capacitance elements is recorded in the database 320 in advance.

  Next, the floor plan tool 311 performs a floor plan (step S2). The floor plan tool 311 reads out the data of the circuit block prepared in step S1 from the database 320, and places the A block 101, the B block 102, the C block 103, the D block 201, and the E block 105 in any position in the chip area 200a. Decide what to do.

  Next, the layout tool 312 performs circuit block arrangement (step S3). The layout tool 312 arranges the individual circuit elements constituting the net list in the location assigned for each circuit block in step S2.

  Next, the decoupling capacity placement tool 313 performs decoupling capacity placement (step S4). The decoupling capacitance arrangement tool 313 reads the data of the MOS capacitance element from the database 320, and adds and arranges the MOS capacitance element for each circuit block arranged in step S3. The decoupling capacitance arrangement tool 313 selects an appropriate type of MOS capacitance element according to the operating frequency of the circuit block from the three types of MOS capacitance elements whose data is stored in the database 320. Details of selection and arrangement of the MOS capacitance element will be described later.

  Next, the layout tool 312 performs wiring (step S5). The layout tool 312 generates wiring data between the arranged circuit elements. In this step, the layout tool 312 arranges power supply lines for supplying power to the circuit block so that the MOS capacitance elements arranged at positions corresponding to the circuit blocks are connected.

  Next, the mask creation tool 314 creates mask data (step S6). Based on the placement data and wiring data of each circuit element, mask data for each layer of the semiconductor substrate is generated.

  The semiconductor integrated circuit 200 shown in FIG. 6 is manufactured by using the mask formed based on the mask data in the semiconductor manufacturing process.

  Next, details of the decoupling capacitance arrangement shown in FIG. 8 will be described.

  FIG. 9 is a flowchart showing processing of the decoupling capacitance arrangement of FIG.

  At the start of the decoupling capacitance arrangement process, the decoupling capacitance arrangement tool 313 takes over the arrangement data before the decoupling capacitance arrangement from the layout tool 312 and holds it (step S41). This is data indicating the arrangement of circuit elements constituting each circuit block.

  The decoupling capacitance arrangement tool 313 takes in the operation frequency data of the circuit block (step S42). The operating frequency data is fetched for one circuit block at a time, and is read by reading the circuit block data 321 from the database 320 (see FIG. 7). The decoupling capacitance arrangement tool 313 also reads decoupling capacitance element data 322 from the database 320 (see FIG. 7).

  Next, the decoupling capacitance arrangement tool 313 arranges a MOS type decoupling capacitance element having the lowest response frequency that is equal to or higher than the circuit block operating frequency in the circuit block that has received the operating frequency data. More specifically, the decoupling capacitance arrangement tool 313 determines whether the operation frequency of the circuit block captured in step S43 is high, low, or medium. The response frequency of the MOS capacitor element that can be arranged is used as a threshold value for determination. For example, in this embodiment, the threshold frequency is 10 MHz, which is the response frequency of the MOS capacitor element A, and 30 MHz, which is the response frequency of the MOS capacitor element C, and the operating frequency of the circuit block is the two threshold values. Compare.

  For example, if the operating frequency data captured in step S42 is for the A block 101 shown in FIG. 6, when the operating frequency of the A block 101 is 100 MHz, for example, it is determined that this operating frequency is high, and The MOS capacitor element F having a short gate length is selected from the MOS capacitor cells (step S44). Then, the cell pattern of the MOS capacitor element F is arranged at a position corresponding to the A block 101, specifically, for example, in an area where the A block is arranged and in a peripheral empty area. In this way, the cell data of the MOS capacitor element F is added to the arrangement data of the A block 101 (step S45).

  In addition, when the data of the operating frequency captured in step S43 is for the B block 102, and the operating frequency of the B block 102 is, for example, 8 MHz, it is determined that the operating frequency is low, and the MOS capacitor having a long gate length. Element A is selected (step S48). Then, the cell pattern of the MOS capacitor element A is arranged at a position corresponding to the B block 102. In this way, the cell data of the MOS capacitor A is added to the B block 102 arrangement data (step S49).

  Further, when the operating frequency data captured in step S42 is for the D block 204 shown in FIG. 6 and the operating frequency of the D block 204 is, for example, 20 MHz, the operating frequency is determined to be medium and the gate is operated. The MOS capacitor C having a medium length is selected (step S46). Then, the cell of the MOS capacitor element C is arranged at a position corresponding to the D block 204. In this way, the cell pattern data of the MOS capacitance element C is added to the arrangement data of the D block 204 (step S47).

  The decoupling capacitance arrangement tool 313 repeats the above processing until the arrangement of the MOS capacitance elements is completed in all circuit blocks in the circuit block data 321 (step S50: No), and the arrangement of the MOS capacitance elements is all circuit blocks. Is finished (step S50: Yes), the arrangement of the decoupling capacitors is finished (step S51). Finally, the circuit block arrangement data after the decoupling capacitance arrangement is stored in the database 320 (step S52).

  By the design method shown in FIGS. 8 and 9, a MOS capacitor element F having a short gate length is connected to the wiring for supplying power to the A block 101 (see FIG. 6) having a high operating frequency, and the B block having a low operating frequency. The MOS capacitor element A having a long gate length is connected to the wiring for supplying power to the 102, C block 103, and E block 105. Further, for the D block 204 having an intermediate operating frequency, a MOS capacitor element C having a medium gate length is connected. The MOS capacitor element F having a small gate length can efficiently remove high-frequency noise generated in the A block. On the other hand, in the B block, the C block, and the E block that operate at a low frequency, the arrangement capacity efficiency is improved by arranging the MOS capacitor element A having a long gate length. In this way, by selecting a MOS capacitor having an appropriate size according to the operating frequency of the circuit block, the semiconductor integrated circuit 200 in which both noise removal efficiency and area efficiency are achieved is designed.

  In the above-described method, three types of six types of MOS capacitor elements can be selected, and a capacitor element selected from these is described. However, the design method of the present invention is not limited to this. Absent. For example, all six types of MOS capacitor elements may be arranged, and a more optimal MOS capacitor element may be selected according to the operating frequency. Further, only two types out of the six types of MOS capacitance elements can be selected, and the design system may be simplified.

  In the above-described embodiment, the example of the structure of the MOS capacitor has been described in which the gate electrode extends substantially perpendicular to the source-drain direction. However, the MOS decoupling capacitor of the present invention is not limited to this. Alternatively, other types of MOS type decoupling capacitive elements such as a ring gate capacitive element shown in part (b) of FIG. 10 and a flat capacitive element shown in part (b) of FIG. 10 may be used. In the case of a flat capacitor, the dimension of one side of the rectangular active region corresponds to the source-drain dimension.

  Further, in the above-described embodiment, the example of the n-channel type MOS capacitive element has been described. However, the MOS-type decoupling capacitive element of the present invention is not limited to this, and is a p-channel type MOS capacitive element. Also good.

It is a figure which shows the example of the structure of the MOS type decoupling capacitive element integrated in the semiconductor integrated circuit which is one Embodiment of this invention. It is a graph which shows the frequency characteristic of the MOS capacitive element of the type shown in FIG. FIG. 2 is a diagram showing a structure of an array of MOS capacitor elements in which a plurality of MOS capacitor elements shown in FIG. 1 are arranged. FIG. 3 is a table showing ratios of areas necessary for obtaining equal capacitances for the six types of MOS capacitive elements having the characteristics shown in FIG. FIG. 3 is a layout diagram illustrating an example of a semiconductor integrated circuit according to the present invention. FIG. 6 is a layout diagram showing an embodiment of a semiconductor integrated circuit different from FIG. 5. It is a block diagram which shows schematic structure of the design system which implement | achieves the design method of the semiconductor integrated circuit which is the 2nd Embodiment of this invention. It is a flowchart which shows the procedure in which the design system shown in FIG. 7 performs a design. It is a flowchart which shows the process of the decoupling capacity | capacitance arrangement | positioning of FIG. It is a figure which shows the structure of the capacitive element arrange | positioned at the semiconductor device of a prior art.

Explanation of symbols

10 MOS capacitor (MOS type decoupling capacitor)
DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Source 13 Drain 14 Active region 15 Oxide insulating film 16 Gate electrode 100, 200 Semiconductor integrated circuit 100a, 200a Chip region 101, 102, 103, 104, 105, 204 Circuit block 300 Design system 311 Floor plan tool 312 Layout Tool 313 Decoupling capacitance arrangement tool 320 Database 321 Circuit block data 322 Decoupling capacitance element data L Gate length (size between source and drain)

Claims (4)

A first circuit block having a relatively high operating frequency; a second circuit block having a relatively low operating frequency;
A first MOS type decoupling capacitance element having a relatively small source-drain dimension connected to a wiring for supplying power to the first circuit block;
A second MOS type decoupling capacitive element having a larger source-drain dimension than the first MOS type decoupling capacitive element, connected to a wiring for supplying power to the second circuit block; A semiconductor integrated circuit comprising: The structures of both the first MOS type decoupling capacitive element and the second MOS type decoupling capacitive element overlap with the active region provided on the surface of the semiconductor substrate via the capacitive insulating film. A structure of a MOS transistor comprising a gate electrode covering the active region and extending in one direction,
2. The semiconductor integrated circuit according to claim 1, wherein the dimension between the source and the drain is a dimension in a direction perpendicular to the one direction of the gate electrode. In a design method of a semiconductor integrated circuit having a plurality of circuit blocks and a decoupling capacitor that is provided corresponding to each of the plurality of circuit blocks and reduces noise of a power source supplied to the corresponding circuit block.
The data including the operating frequency of each of the plurality of circuit blocks is recorded in a database, and the pattern data of the first MOS type decoupling capacitance element having a relatively small source-drain dimension, the first Recording pattern data of a second MOS type decoupling capacitance element having a relatively larger source-drain dimension than the MOS type decoupling capacitance element in a database;
The plurality of circuit blocks are arranged in the chip area of the semiconductor integrated circuit, and the operation frequency of the circuit block is higher than a predetermined value at a position corresponding to each of the arranged circuit blocks. Disposing a first MOS type decoupling capacitance element, and disposing the second MOS type decoupling capacitance element when the operating frequency is a predetermined value or less;
Arranging a power supply wiring for supplying power to each of the plurality of arranged circuit blocks so that decoupling capacitance elements respectively arranged at positions corresponding to the plurality of circuit blocks are connected to each other. A method of designing a semiconductor integrated circuit. In a design method of a semiconductor integrated circuit having a plurality of circuit blocks and a decoupling capacitor that is provided corresponding to each of the plurality of circuit blocks and reduces noise of a power source supplied to the corresponding circuit block.
Data including operating frequencies of the plurality of circuit blocks is recorded in a database, and pattern data and response frequency data of a plurality of MOS decoupling capacitance elements having different source-drain dimensions are stored in the database. Recording step;
The plurality of circuit blocks are arranged in the chip region of the semiconductor integrated circuit, and the lowest response frequency that is equal to or higher than the circuit block operating frequency is provided at a position corresponding to each of the arranged circuit blocks. Disposing a MOS type decoupling capacitance element having;
Arranging a power supply wiring for supplying power to each of the plurality of arranged circuit blocks so that decoupling capacitance elements respectively arranged at positions corresponding to the plurality of circuit blocks are connected to each other. A method of designing a semiconductor integrated circuit.

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