JP2009004494A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of simply improving resistance to external stress or flexural stress without need of a complex manufacturing process. <P>SOLUTION: An IC chip 10 which is resin-sealed by covering an upper surface and a side face with a sealing resin layer 4 is mounted on a substrate 3. The sealing resin layer 4 comprises two parts including a first structural part 4a in contact with a surface of the substrate 3 and a second structural part 4b in a different shape constituted in conjunction on the first structural part 4a. The first structural part 4a is shaped in a rectangular parallelopiped or a truncated square pyramid having a bottom face and an upper face of a rectangular shape. The second structural part 4b is in a three-dimensional shape comprising a bottom face structured in a rectangular shape common to the upper surface of the first part 4a and two rectangles or trapezoids and two triangles formed by connecting ridge lines parallel to a longer side of the bottom face formed on the uppermost part, both ends of the ridge lines and respective vertexes of the bottom face or comprising the bottom face and four triangles formed by connecting one vertex formed at the uppermost position with the respective vertexes of the bottom face. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor package in which a semiconductor chip is sealed with a resin.

  In recent years, with the miniaturization of electric devices, multifunctionality and portability have been improved. In particular, IC cards and mobile phones are preliminarily assumed to be carried when used, and high reliability such as impact resistance is required.

  In addition, recent IC cards and mobile phones can be used for payment processing in public transportation, electronic passports, medical management systems, etc., and a lot of personal information or external Information used for reading personal information in connection with other devices has been recorded. For this reason, high security is also required in addition to impact resistance. Furthermore, in such a situation where it can be used for various systems, the chances of using an IC card or a mobile phone are greatly increased, so that higher reliability than before is required.

  FIG. 4 is a block diagram showing an inlet configuration of a conventional non-contact type IC card, and FIG. 5 is a schematic plan view of the inlet. FIG. 6 is a schematic cross-sectional view when cut along line A-A ′ in FIG. 5.

  The non-contact type IC card shown in FIG. 4 has an IC chip 10 mounted with an RF communication circuit 11 and a calculation and data storage unit 12 mounted on a substrate 3 (see FIGS. 5 and 6) on which an electric circuit is molded. Then, the semiconductor package 8 called an IC card module in which the IC chip 10 is sealed with the mold resin 4 (see FIGS. 5 and 6) and the antenna coil 7 formed by winding or etching are electrically connected. Composed. The calculation and data storage unit 12 is equipped with a CPU 13 and a memory 14, and necessary information is read from or written to the memory 14 according to the process, and the CPU 13 performs the calculation process.

  As shown in FIGS. 5 and 6, the sealing resin layer 4 is formed in the region where the IC chip 10 is mounted on the substrate 3, and thereby the IC chip 10 is resin-sealed. The resin sealing is performed to ensure long-term reliability and physical characteristics for the IC chip 10. The antenna coil 7 is formed so as to go around the outer peripheral region of the IC card base 6 while having connection with the semiconductor package 8. The semiconductor package 8 and the antenna coil 7 are collectively referred to as “inlet 9” below.

  The IC chip 10 and the substrate 3 are electrically connected by wire bonding with the wire 2.

  Further, a reinforcing member 5 such as a metal is mounted between the IC chip 10 and the substrate 3 in order to prevent damage such as breakage or chipping of the IC chip 10. By forming the reinforcing member 5, the strength of the IC chip 10 is increased, thereby preventing damage to the IC chip 10 due to vertical and local external stress being applied to the substrate surface of the substrate 3. Such a technique is disclosed in Patent Documents 1 and 2 below.

  Further, a method of preventing damage to the IC chip 10 by imparting an inclination by making the sealing resin layer 4 hemispherical or conical (conical, polygonal pyramidal), thereby dispersing external stress is disclosed in the following patent. It is disclosed in Document 3. FIG. 7 schematically shows a cross-sectional structure and a planar structure of a semiconductor package described in each patent document. 7A shows the case where the reinforcing member 5 is provided (similar to FIG. 6), FIG. 7B shows the case where the sealing resin layer 4 is formed in a hemispherical shape, and FIG. 7C shows the sealing resin layer. 4 shows the case where it is formed in a cone shape.

JP 2004-326351 A JP-A-8-324166 JP-A-10-006671

  In the case of a semiconductor device that is highly likely to be always carried, such as an IC card, an impact caused by dropping on the road, and bending or pressing accompanying folding when stored in a wallet or pocket can occur on a daily basis. Further, when an IC chip is mounted on an electronic passport, a predetermined area is intensively impacted by pressing a stamp. In these utilization modes, particularly high resistance to external stress is particularly required. By adopting the method described in each of the above patent documents, the resistance to external stress can be increased to a certain extent.

  However, in the case of using the method of mounting the reinforcing member 5 as in Patent Documents 1 and 2 (see FIG. 7A), a process of attaching the reinforcing member 5 between the substrate 3 and the IC chip 10 is necessary, and the manufacturing process There is a problem that becomes complicated.

  Further, among the methods described in Patent Document 3, when the sealing resin layer 4 is hemispherical (see FIG. 7B), the module is not directional, so that mounting becomes difficult. Further, when the sealing resin layer 4 is formed in a cone shape (see FIG. 7C), a sufficient height is required if the resin sealing region is narrowed, and as a result, it is difficult to make a thin package. Become. On the other hand, in order to realize a thin package, the resin sealing region may be sufficiently wide. However, in this case, another problem that a bending stress is easily applied and a crack or the like is easily generated occurs.

  In view of the above problems, an object of the present invention is to provide a semiconductor device that does not require a complicated manufacturing process and can easily increase resistance to external stress and bending stress.

  In order to achieve the above object, a semiconductor device according to the present invention mounts an IC chip resin-sealed by covering an upper surface and a side surface with a sealing resin layer on a substrate, and the sealing resin layer includes: It is composed of two parts, a first component contacting the substrate surface and a second component having a different shape connected to the first component, and the first component includes a bottom surface and It is a quadrangular prism shape or a truncated pyramid shape with the upper surface being a quadrilateral shape, and the second constituent part is a bottom face having a quadrangular shape common to the upper face of the first constituent part, and the highest part with the highest position A ridge line parallel to the rectangular long side of the bottom surface, and a three-dimensional shape formed by two rectangles or trapezoids and two triangles formed by connecting both ends of the ridge line and each vertex of the bottom surface, or , A square common to the upper surface of the first component And a three-dimensional shape constituted by four triangles formed by connecting the vertex and each vertex of the bottom surface. It is characterized by.

  According to the first characteristic configuration of the semiconductor device according to the present invention, since the sealing resin layer is formed in a sloped shape having an inclination above the IC chip, the external stress from above is appropriately dispersed. Thus, the impact on the IC chip can be reduced without forming the reinforcing member.

  And according to the structure of this invention, the sealing resin layer has two shapes, the 1st structure part from the bottom face to a fixed height position, and the 2nd structure part above it, The 1st structure part It is comprised so that the inclination of the side surface of the 2nd structure part located in the upper direction may become gentle rather than the inclination of the side surface. Therefore, compared to the case where the sealing resin layer is formed in a polygonal pyramid shape having a certain angle of inclination from the substrate surface to the uppermost part, the sealing resin layer of the sealing resin layer is the same when the formation area of the bottom surface is the same. When the height of the sealing resin layer is the same, the occupied area of the sealing resin layer on the bottom surface, that is, the substrate surface can be reduced. Accordingly, it is possible to achieve both the suppression of the impact of external stress on the IC chip and the reduction in thickness and size of the semiconductor device. In addition, since the area occupied by the sealing resin layer can be narrowed, resistance to bending stress can be increased.

  Furthermore, in the case of the configuration of the present invention, it can be realized simply by changing the shape of the sealing resin layer. Therefore, in addition to the conventional method, resistance to external stress and bending stress can be easily increased without adding a new complicated process.

In addition to the first characteristic configuration, the semiconductor device according to the present invention includes the first configuration unit,
The second feature is that the inclination of the side surface connecting the bottom surface and the top surface with respect to the substrate surface is 60 ° or more and 90 ° or less.

  According to the second characteristic configuration of the semiconductor device according to the present invention, the occupied area of the sealing resin layer necessary for sealing the IC chip on the substrate surface can be minimized.

  Further, in the semiconductor device according to the present invention, in addition to the first or second characteristic configuration, the second component section extends from the uppermost portion to a bottom surface of the second component portion, and the uppermost portion is the ridgeline. If the uppermost part is constituted by the one apex, the surface perpendicular to the rectangular long side of the bottom surface is formed. The third feature is that the shape is a triangular shape with the position of the bottom surface as the base, and the angle of the other two sides with respect to the base is between 1 ° and 30 °.

  According to the third characteristic configuration of the semiconductor device according to the present invention, the occupation height of the sealing resin layer necessary for alleviating the influence of the external stress on the IC chip can be suppressed to the minimum. It is possible to achieve both a reduction in thickness and high resistance to external stress.

  According to the configuration of the present invention, a semiconductor device that does not require a complicated manufacturing process and can easily increase resistance to external stress and bending stress is realized.

  In the following, an embodiment of a semiconductor device according to the present invention (hereinafter referred to as “the present device” as appropriate) will be described with reference to FIGS.

  The apparatus of the present invention is different from the conventional configuration only in the formation shape of the sealing resin layer, and the other is the same as the conventional configuration. In the following, the same components as those in FIGS. 4 to 7 are described as such, and the same reference numerals are given in the drawings, and the description thereof is simplified or omitted.

  1 and 2 show schematic structural views of the device of the present invention. FIGS. 1 (a) to 1 (c) and FIGS. 2 (a) to 2 (c) are all examples. 1 and FIG. 2 is a cross-sectional structural diagram in which the uppermost portion is formed by a ridgeline and is a surface perpendicular to the ridgeline, and the uppermost portion is formed by the one vertex. The cross-sectional structure figure when cut | disconnecting from the uppermost part to a bottom face in the surface perpendicular | vertical to the rectangular long side is shown.

  In each of the embodiments of FIGS. 1 and 2, the shape of the sealing resin layer 4 is such that the lower first component 4 a whose bottom surface is in contact with the substrate surface of the substrate 3 and the second component connected to the upper portion thereof. Consists of a part 4b, and both constituent parts 4a and 4b have different shapes. In addition, each Example shown to Fig.1 (a)-(c) has shown the common cross-section, and each Example shown to Fig.2 (a)-(c) is the case of FIG. A common cross-sectional structure diagram different from FIG.

  In the case of FIG. 1A, the first component 4a has a quadrangular prism shape having a rectangular bottom surface on the substrate 3 and an upper surface having the same shape as the bottom surface. In addition, the quadrangular shape in this specification does not indicate only a pure quadrangle in which each vertex is a right angle, but also includes a shape conforming to a quadrangle having a certain rounded corner. Similarly, what is described as a triangle is not limited to a pure triangle, but includes a shape that conforms to a triangle with a certain roundness at the apex.

  And on the 1st structure part 4a which shows the said square pole shape, it connects with the 1st structure part 4a and the 2nd structure part 4b is comprised. The second component 4b has a rectangular bottom surface (rectangular shape composed of vertices 23 to 26) common to the upper surface of the first component 4a, and the bottom of the bottom surface is the highest at the highest position. The ridgeline 22 is parallel to the rectangular long side 21 (corresponding to the side between the vertices 23 and 24 or the side between the vertices 25 and 26). And it has two triangular surfaces comprised by connecting the both ends of this ridgeline 22, and the vertex of the 2nd structure part 4b close | similar to each endpoint, and two rectangular surfaces. Specifically, the triangular surface T1 formed by connecting the end point 27, the vertex 23, and the vertex 26, the triangular surface T2 formed by connecting the end point 28, the vertex 24, and the vertex 25, and the end point 27, a rectangular surface Q1 formed by connecting the end point 28, the vertex 24, and the vertex 23, and a rectangular surface Q2 formed by connecting the end point 27, the end point 28, the vertex 25, and the vertex 26. Have. The sealing resin layer 4 configured in this way has a form in which a triangular prism-shaped second component 4b is superimposed on a quadrangular prism-shaped first component 4a.

  That is, in the case of FIG. 1A, the sealing resin layer 4 surrounds the substrate surface from the surface of the substrate 3 to a predetermined height position so as to cover the side surface of the IC chip 10, and the height position is higher. In the region, the sealing resin layer 4 surrounds the two opposite side surfaces parallel to the ridge line 22 with an inclination, and the other two side surfaces facing each other still have a shape surrounding the vertical side. That is, on the upper surface of the sealing resin layer 4, the ridgeline 22 and the quadrangular surfaces Q1 and Q2 having an inclination are configured. At this time, the angle θ2 of the inclined surface of the sealing resin layer 4 with respect to the bottom surface in the second component 4b is expressed by 1 ° ≦ θ2 ≦ 30 °.

  Further, in the case of FIG. 1B, the triangular surfaces T1 and T2 in FIG. 1A are inclined on the opposite surface side (T3, T4), and the rectangular surfaces Q1 and Q2 Instead, the structure has trapezoidal surfaces Q3 and Q4.

  Specifically, the second component 4b has a rectangular bottom surface (rectangular shape composed of vertices 33 to 36) common to the upper surface of the first component 4a, and is the uppermost portion having the highest height position. 1 has a ridge line 32 parallel to the rectangular long side 31 (corresponding to the side between the vertices 33 and 34 or the side between the vertices 35 and 36). The ridge line 32 is shorter than the long side 31, thereby forming a triangular surface T3 formed by connecting the end point 37, the vertex 33, and the vertex 36 of the ridge line, and the end point 38, the vertex 34, and the vertex of the ridge line. The triangular surface T4 formed by tying 35 is formed with an inclination on the opposite surface side, that is, on the central portion side where the IC chip 10 is formed, as compared with the case of FIG. .

  Further, a trapezoidal surface Q3 formed by connecting the end point 37, the end point 38, the vertex 34, and the vertex 33, and a trapezoidal surface Q4 formed by connecting the end point 37, the end point 38, the vertex 35, and the vertex 36. And having. The sealing resin layer 4 configured in this way has a form in which a second component 4b having a three-dimensional shape according to a triangular prism shape is superimposed on a first component 4a having a quadrangular prism shape.

  Moreover, in the case of FIG.1 (c), the 1st structure part 4a has the same quadrangular prism shape as the case of Fig.1 (a). And on the 1st structure part 4a which shows this square pillar shape, it connects with the 1st structure part 4a and the 2nd structure part 4b is comprised. The second component 4b has a rectangular bottom surface (rectangular shape composed of vertices 43 to 46) common to the top surface of the first component 4a, and the bottom of the bottom surface is the highest at the highest position. It has a vertex 47 located in the region above the intersection of the rectangular diagonal lines. And it has four triangular surfaces comprised by connecting this vertex 47 and each square-shaped vertex 43-46 of a bottom face. Specifically, a triangular surface T5 formed by connecting the vertex 47, the vertex 43, and the vertex 44, a triangular surface T6 formed by connecting the vertex 47, the vertex 44, and the vertex 45, and the vertex 47, the vertex 45, and the triangular surface T7 formed by connecting the vertex 46, and the triangular surface T8 formed by connecting the vertex 47, the vertex 46, and the vertex 43. The sealing resin layer 4 configured in this way has a form in which a quadrangular pyramid-shaped second component 4b is superimposed on a quadrangular prism-shaped first component 4a.

  That is, in the case of FIG. 1C, the sealing resin layer 4 surrounds the substrate surface of the substrate 3 from the substrate surface to a predetermined height position so as to cover the side surface of the IC chip 10, and further in the height position. In the high region, the triangular side surfaces T5 to T8 have a shape that surrounds with an inclination. Also in this case, the angle θ2 of the inclined surface of the sealing resin layer 4 with respect to the bottom surface in the second component 4b is expressed by 1 ° ≦ θ2 ≦ 30 °.

  In the case of FIG. 2A, the first component 4a has a quadrangular frustum shape having a quadrangular bottom surface on the substrate 3 and a quadrangular top surface having a smaller area than the bottom surface.

  And on the 1st structure part 4a which shows the said quadrangular frustum shape, it connects with the 1st structure part 4a and the 2nd structure part 4b is comprised. The second component 4b has a rectangular bottom surface (rectangular shape composed of vertices 53 to 56) common to the top surface of the first component 4a, and the bottom of the bottom surface is the highest at the highest position. A ridgeline 52 parallel to the rectangular long side 51 (corresponding to the side between the vertices 53 and 54 or the side between the vertices 55 and 56) is provided. And it has two triangular surfaces comprised by connecting the both ends of this ridgeline 52, and the vertex of the 2nd structure part 4b close | similar to each end point, and two rectangular surfaces. Specifically, a triangular surface T9 formed by connecting the end point 57, the vertex 53, and the vertex 56, a triangular surface T10 formed by connecting the end point 58, the vertex 54, and the vertex 55, and the end point 57, a rectangular surface Q5 formed by connecting the end point 58, the vertex 54, and the vertex 53, and a rectangular surface Q6 formed by connecting the end point 57, the end point 58, the vertex 55, and the vertex 56. Have. The sealing resin layer 4 configured as described above has a form in which a triangular prism-shaped second component 4b is superimposed on a quadrangular pyramid-shaped first component 4a.

  That is, in the case of FIG. 2A, the two opposite side surfaces parallel to the ridge line 52 from the substrate surface of the substrate 3 to a predetermined height position so as to cover the side surface of the IC chip 10 are 90 relative to the substrate surface. The sealing resin layer 4 surrounds with an inclination of an angle of less than or equal to 0 °, and the sealing resin layer 4 surrounds the other two opposite side surfaces perpendicular to the substrate surface. Further, in the region where the height is high, the sealing resin layer 4 surrounds the two side surfaces facing each other parallel to the ridgeline 52 with an inclination with a gentler slope than the first structure portion 4a. The other two opposite sides still have a vertically surrounding shape. That is, on the upper surface of the sealing resin layer 4, as in the case of FIG. 1A, the ridgeline 52 and the rectangular surfaces Q5 and Q6 having an inclination are formed.

  At this time, in FIG. 2A, the angle θ1 formed between the sealing resin layer 4 in the first structure portion 4a and the bottom surface, that is, the substrate surface of the substrate 3, is the same as that of the sealing resin layer 4 in the second structure portion 4b. It is larger than the angle θ2 formed by the bottom surface of the second structure portion 4b. More specifically, it is represented by 60 ° ≦ θ1 <90 °, 1 ° ≦ θ2 ≦ 30 °. Note that the case of θ1 = 90 ° corresponds to the shape shown in FIG.

  In the case of FIG. 2B, the triangular surfaces T9 and T10 of FIG. 2A are inclined on the opposite surface side (T11, T12), and the rectangular surfaces Q5 and Q6 Instead, it has a trapezoidal surface Q7 and Q8.

  Specifically, the second component 4b has a rectangular bottom surface (rectangular shape composed of vertices 63 to 66) common to the upper surface of the first component 4a, and the highest top portion. 2 has a ridge line 62 parallel to the rectangular long side 61 of the bottom surface (corresponding to the side between the vertices 63 and 64 or the side between the vertices 65 and 66). The ridge line 62 is shorter than the long side 61, and thereby, the triangular surface T11 formed by connecting the end point 67, the vertex 63, and the vertex 66 of the ridge line, and the end point 68, the vertex 64, and the vertex of the ridge line. The triangular surface T12 formed by connecting 65 is formed with an inclination on the opposite surface side, that is, on the central portion side where the IC chip 10 is formed, as compared with the case of FIG. .

  Further, a trapezoidal surface Q7 formed by connecting the end point 67, the end point 68, the vertex 64, and the vertex 63, and a trapezoidal surface Q8 formed by connecting the end point 67, the end point 68, the vertex 65, and the vertex 66. And having. The sealing resin layer 4 configured as described above has a form in which a second configuration portion 4b having a three-dimensional shape according to a triangular prism shape is superimposed on a first configuration portion 4a having a truncated pyramid shape.

  Further, in the case of FIG. 2C, the first component 4a has a quadrangular frustum shape similar to that in the case of FIG. And on the 1st structure part 4a which shows this square frustum shape, it connects with the 1st structure part 4a and the 2nd structure part 4b is comprised. The second component 4b has a rectangular bottom surface (rectangular shape composed of vertices 73 to 76) common to the upper surface of the first component 4a, and the bottom of the bottom surface is the highest at the highest position. It has a vertex 77 located in the region above the intersection of the rectangular diagonal lines. And it has four triangular surfaces comprised by connecting this vertex 77 and each square-shaped vertex 73-76 of a bottom face. Specifically, a triangular surface T13 formed by connecting the vertex 57, the vertex 53, and the vertex 54, a triangular surface T14 formed by connecting the vertex 77, the vertex 74, and the vertex 75, and the vertex 77, the vertex 75, and the triangular surface T15 formed by connecting the vertex 76, and the triangular surface T16 formed by connecting the vertex 77, the vertex 76, and the vertex 73. The sealing resin layer 4 configured as described above has a form in which a quadrangular pyramid-shaped second component 4b is superimposed on a quadrangular pyramid-shaped first component 4a.

  That is, in the case of FIG. 2C, each side surface of the trapezoid has an inclination from the substrate surface of the substrate 3 to a predetermined height position so as to cover the side surface of the IC chip 10, and the sealing resin layer 4 Is surrounded, and in the region where the height is higher, the triangular side surfaces T13 to T16 are surrounded by a slope. Also in this case, as in FIG. 2A, the angle θ1 formed by the sealing resin layer 4 in the first structure portion 4a and the bottom surface, that is, the substrate surface of the substrate 3, is the sealing in the second structure portion 4b. The angle θ2 is larger than the angle θ2 formed by the resin layer 4 and the bottom surface of the second structure portion 4b, and is represented by 60 ° ≦ θ1 <90 ° and 1 ° ≦ θ2 ≦ 30 °, respectively.

  When configured as shown in FIGS. 1A to 1C and FIGS. 2A to 2C, when the external stress from the upper direction is applied to the sealing resin layer 4, the ridge line 22 is applied. The presence of the ridgeline 32, the vertex 47, the ridgeline 52, the ridgeline 62, and the vertex 77 has a repulsive force against a certain impact. Further, in each, the sealing resin layer 4 is inclined on the upper surface (in the case of FIG. 1 (a), the rectangular surfaces Q1 and Q2, in the case of FIG. 1 (b), the rectangular surfaces Q3 and Q4, FIG. 1 (c), triangular surfaces T5 to T8, FIG. 2 (a), rectangular surfaces Q5 and Q6, and FIG. 2 (b), rectangular surfaces Q7 and Q8, FIG. Since c) has triangular surfaces T13 to T16), external stress from above can be dispersed moderately, and impact on the IC chip 10 can be dispersed. Therefore, even if the reinforcing member 5 is not formed as shown in FIG. 7A, the resistance to a certain degree of external stress can be increased.

  On the other hand, when the area occupied by the sealing resin layer 4 on the bottom surface is the same as in the case of a polygonal pyramid having a certain angle of inclination from the bottom surface to the top as shown in FIG. When forming the sealing resin layer 4 so as to completely cover the chip 10, the inclination of the second structure portion 4b can be made gentler than in the case of FIG. For this reason, compared with the structure of FIG.7 (c), the occupation height to the uppermost part and bottom face of the sealing resin layer 4 can be made low, and, thereby, thickness reduction of a semiconductor device is realizable. . Further, when the sealing resin layer 4 is to be realized at the same height, the device of the present invention has a sealing resin layer on the substrate surface of the substrate 3 as compared with the structure of FIG. Since the occupation area of 4 can be narrowed, the apparatus scale can be reduced and the resistance to bending stress can be improved.

  1A to 1C and FIGS. 2A to 2C show the case where the sealing resin layer 4 is formed on one surface of the substrate 3. A sealing resin layer 4 ′ having the same shape as that of the front surface side sealing resin layer 4 may also be formed on the back surface side of the surface. FIG. 4 shows a cross-sectional view when the sealing resin layer 4 is also formed on the back surface side. Even when the sealing resin layer 4 is formed on the back surface side, the plan view is the same as FIG. 3 (a) shows the case of FIGS. 1 (a) to (c), and FIG. 3 (b) shows the case of FIGS. 2 (a) to (c). Sectional drawing at the time of forming is shown.

By doing in this way, the effect which relieve | moderates the impact to the IC chip 10 with respect to external stress can further be heightened. In particular, when the device of the present invention is used for an IC card having no contact terminal surface, the sealing resin layer 4 is formed on both surfaces in this way in order to increase the impact resistance to the IC chip 10 against external stress. Is a useful method. However, in this case, if the thickness of the sealing resin layer 4 is increased too much, that is, the height from the substrate surface to the uppermost position, the sealing resin layer 4 is formed on both surfaces of the substrate, so that the thickness of the entire IC card is reduced. Therefore, depending on the specification of the thickness of the IC card, the mounting is difficult, and depending on the size of the IC chip 10, there is a possibility that the effect cannot be exhibited sufficiently. Therefore, particularly for an IC card having a specification with a large thickness (for example, 700 μm or more) and a relatively small size of the IC chip 10 (occupied area of 10 mm ² or less), the sealing resin layer 4 on both sides in this way. It is useful to form

  In addition, since the sealing resin layer 4 has both the first structure portion 4a and the second structure portion 4b having flat sides, the hemisphere as shown in FIG. Implementation is greatly facilitated compared to the situation.

  Thus, according to the device of the present invention, resistance to external stress and bending stress can be easily increased only by changing the molding of the sealing resin layer 4. Further, by changing the shape of the sealing resin layer 4, the contact area between the exterior resin of the IC card substrate to be mounted and the sealing resin layer 4 is increased, so that the adhesion with the IC card substrate is improved, This also has the effect of alleviating cracks in the IC card substrate.

  In the above-described embodiment, only the case where the semiconductor chip 10 and the substrate 3 are connected by wire bonding has been described. However, the present invention can also be used in the connection method by flip chip bonding.

Schematic structural diagram of a semiconductor device according to the present invention Another schematic structure diagram of the semiconductor device according to the present invention Schematic cross-sectional structure diagram of another embodiment of a semiconductor device according to the present invention Block diagram showing the inlet configuration of a non-contact type IC card Non-contact type IC card inlet schematic plan structure diagram Non-contact type IC card inlet schematic cross-sectional structure diagram Schematic cross-sectional structure diagram of a conventional semiconductor package

Explanation of symbols

3: Substrate 4: Sealing resin layer 5: Reinforcing member 6: IC card substrate 7: Antenna coil 8: Semiconductor package 9: Inlet 10: IC chip 11: RF communication circuit 12: Calculation and data storage unit 13: CPU
14: Memory 22, 32, 52, 62: Edge line 23-26, 33-36, 43-46, 53-56, 63-66, 73-76: Vertex 27, 28, 37, 38, 57, 58, 67 68: End points T1-T16: Triangular shape Q1-Q2, Q5-Q6: Square shape Q3-Q4, Q7-Q8: Trapezoidal shape

Claims (3)

On the substrate, an IC chip that is resin-sealed by covering the upper surface and side surfaces with a sealing resin layer is mounted,
The sealing resin layer is
Consists of two parts, a first component that contacts the substrate surface, and a second component having a different shape configured by being connected to the first component,
The first component is a quadrangular prism shape or a quadrangular frustum shape having a rectangular bottom and top surface,
The second component is
A bottom surface configured by a square shape common to the top surface of the first component, a ridge line parallel to the long side of the rectangular shape of the bottom surface configured at the top of the highest position, and both ends of the ridge line and the bottom surface A solid shape formed by two rectangles or trapezoids and two triangles formed by connecting the vertices of each of the above, or a bottom surface formed by a quadrangular shape common to the top surface of the first component, at the top position 1. A semiconductor device comprising: a configured vertex, and a three-dimensional shape composed of four triangles formed by connecting the vertex and each vertex of the bottom surface. The first component is
2. The semiconductor device according to claim 1, wherein an inclination of a side surface connecting the bottom surface and the top surface with respect to the substrate surface is 60 ° or more and 90 ° or less. The second component is
From the uppermost part to the bottom surface of the second component part, when the uppermost part is constituted by the ridge line, the surface is perpendicular to the ridgeline, and when the uppermost part is constituted by the one vertex. The shape formed by cutting each of the bottom surfaces of the bottom surface with a rectangular long side is a triangular shape having the bottom surface as the base, and the angle of the other two sides with respect to the bottom is 1 ° or more. The semiconductor device according to claim 1, wherein the semiconductor device is 30 ° or less.

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