JP2008520101A - Thermal process for producing in-situ bonding layers in CIGS - Google Patents

Thermal process for producing in-situ bonding layers in CIGS Download PDF

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JP2008520101A
JP2008520101A JP2007541291A JP2007541291A JP2008520101A JP 2008520101 A JP2008520101 A JP 2008520101A JP 2007541291 A JP2007541291 A JP 2007541291A JP 2007541291 A JP2007541291 A JP 2007541291A JP 2008520101 A JP2008520101 A JP 2008520101A
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アール. タトル,ジョン
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デイスター テクノロジーズ,インコーポレイティド
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Abstract

本発明は、一般的には光起電力技術の分野に関し、より具体的には熱プロセスを用いた薄膜太陽電池の作製に関する。具体的には、現場接合形成プロセスによってCIGS太陽電池を製造するための方法が開示される。  The present invention relates generally to the field of photovoltaic technology, and more specifically to the fabrication of thin film solar cells using thermal processes. Specifically, a method for manufacturing a CIGS solar cell by an in-situ junction formation process is disclosed.

Description

本明細書に開示される本発明は、一般的には光起電力技術の分野に関し、より具体的には現場接合プロセスを用いた薄膜太陽電池の作製に関する。   The invention disclosed herein relates generally to the field of photovoltaic technology, and more specifically to the fabrication of thin film solar cells using an in-situ bonding process.
比較的高効率の光起電力(「PV」)電池は実験室において製造することができる。しかしながら、商業化にとって重要な再現性と効率性を両立しつつ、これらのプロセスを商業的な規模に拡大することは困難であることがわかっている。効率性を欠く薄膜製造プロセスは、PV電池が市場において従来のエネルギー源を有効に代替しないことの一因となっている。実験室のバッチ処理法をより安価でかつより良く制御された有効な産業プロセスに変換することは、PV技術を主流の市場へ前進させるのに役立つであろう。   Relatively high-efficiency photovoltaic (“PV”) cells can be manufactured in the laboratory. However, it has proven difficult to scale these processes to a commercial scale, while achieving both reproducibility and efficiency, which are important for commercialization. Inefficient thin film manufacturing processes contribute to PV cells not effectively replacing conventional energy sources in the market. Converting laboratory batch processes into cheaper and better controlled and effective industrial processes will help advance PV technology into the mainstream market.
高効率の薄膜製造プロセスなしに、PV電池は現在のエネルギー源を有効に代替することはできない。PV電池を製造するために、PV材料の薄い半導体層が支持層、例えば、ガラス、金属又はプラスチックの箔上に堆積される。薄膜の直接遷移半導体材料は、間接遷移結晶半導体材料よりも高い光吸収性を有するので、PV材料は、原子、分子又はイオンの極薄の連続層において堆積される。基本的な光電池のスタックデザインは、PV電池の典型的な構造を例示している。このデザインでは、電池は、基材と、バリヤー層と、バック接点層と、半導体層と、アルカリ材料層と、n型接合バッファ層と、真性透明酸化物層と、導電性透明酸化物層とを含む。   Without a highly efficient thin film manufacturing process, PV cells cannot effectively replace current energy sources. To manufacture a PV cell, a thin semiconductor layer of PV material is deposited on a support layer, for example a glass, metal or plastic foil. Since thin film direct transition semiconductor materials have higher light absorption than indirect transition crystalline semiconductor materials, PV materials are deposited in a very thin continuous layer of atoms, molecules or ions. The basic photovoltaic stack design illustrates the typical structure of a PV cell. In this design, the battery comprises a substrate, a barrier layer, a back contact layer, a semiconductor layer, an alkali material layer, an n-type junction buffer layer, an intrinsic transparent oxide layer, and a conductive transparent oxide layer. including.
銅−インジウム−セレン(CIS)化合物、インジウムのすべて又は一部をガリウムで置換したもの(CIGS)及び/又はセレンのすべて又は一部を硫黄で置換したもの(CISS)は、薄膜太陽電池の吸収体層において使用するのに最も期待されている。CIGS電池は、他の吸収体層化合物と比べて最も高い効率性と優れた安定性を実証している。典型的には、CIGS膜は減圧系技術によって堆積される。しかしながら、PV素子を含む多層は量産方式に対して課題がある。現在、CIGS素子を連続的に生産するための実績のある技術はない。加えて、典型的なPV電池の製造技術は、接触作業と、高い資本コストと、低い製造業生産高とを必然的に伴うバッチ処理を必要とする。対照的に、連続プロセスは、資本コストと接触作業を最小限に抑え、一方で製品のスループットと産出高を最大にすることができる。   Copper-indium-selenium (CIS) compounds, all or part of indium substituted with gallium (CIGS) and / or all or part of selenium substituted with sulfur (CISS) are absorbed by thin film solar cells. Most expected to use in body layer. CIGS batteries have demonstrated the highest efficiency and superior stability compared to other absorber layer compounds. Typically, CIGS films are deposited by reduced pressure system techniques. However, the multilayer including the PV element has a problem with the mass production system. Currently, there is no proven technology for continuously producing CIGS elements. In addition, typical PV cell manufacturing techniques require batch processing that entails contact operations, high capital costs, and low manufacturing output. In contrast, a continuous process can minimize capital costs and contact operations, while maximizing product throughput and yield.
とりわけ、CIGS系は製造業者に特有の困難をもたらす。2002年10月14日にRamanathanらによって論じられているように、大面積モジュールの製造に用いられるプロセスは、金属前駆体スタックの堆積と、その後のセレン及び硫黄環境での化合物の形成とを伴う。光電池の用途では、p型CIGS層をn型CdS層と組み合わせてp−nヘテロ接合CdS/CIGS素子が形成される。しかしながら、このプロセスには問題がある。CdS層のバンドギャップは、依然として吸収体に達することができる太陽スペクトルの短波長部分を制限するほど十分低く、このため、集めることができる電流が低くなる。このような低下は、より高いバンドギャップのCIGS電池に関して比例してより深刻になる。さらには、このプロセスは、その廃棄が将来の製造にとって課題である有害廃棄物を作り出す。したがって、化学浴析出法(「CBD」)CdSプロセスの実用的な代替法を見出すことが当技術分野で求められている。   In particular, the CIGS system presents unique difficulties for manufacturers. As discussed by Ramanathan et al. On October 14, 2002, the process used to manufacture large area modules involves the deposition of a metal precursor stack followed by the formation of compounds in selenium and sulfur environments. . For photovoltaic cell applications, a p-n heterojunction CdS / CIGS element is formed by combining a p-type CIGS layer with an n-type CdS layer. However, there are problems with this process. The band gap of the CdS layer is low enough to limit the short wavelength portion of the solar spectrum that can still reach the absorber, thus lowering the current that can be collected. Such degradation is proportionally more severe for higher bandgap CIGS cells. Furthermore, this process creates hazardous waste whose disposal is a challenge for future production. Accordingly, there is a need in the art to find a practical alternative to chemical bath deposition (“CBD”) CdS processes.
CBD CdSプロセスに対する幾つかの代替法が提案されているが、大規模な連続製造との関連において実行可能な選択肢はない。これらの幾つかは、中でも、ZnS、ZnO、Zn(S,O)、ZnSe、In23及びIn(OH)xyから構成される層の追加を含む。しかしながら、これらの代わりとなるバッファ層の挿入は、より多くの化学工程、並びに完全に活性化するための堆積後アニール又は光照射を伴う場合が多い。これらの堆積後工程の追加は、製造プロセスの効率を低下させ、取り扱いミスや汚染の可能性を製品にもたらす。したがって、追加の化学工程なしにバッファ層を挿入するためのCBD CdS技術に代わる方法を用いた薄膜太陽電池の製造方法が当技術分野で求められている。 Although several alternatives to the CBD CdS process have been proposed, there are no viable options in the context of large scale continuous production. Some of these include, among other things, the addition of layers composed of ZnS, ZnO, Zn (S, O), ZnSe, In 2 S 3 and In (OH) x S y . However, the insertion of these alternative buffer layers often involves more chemical steps, as well as post-deposition annealing or light irradiation to fully activate. The addition of these post-deposition steps reduces the efficiency of the manufacturing process and introduces potential handling errors and contamination to the product. Accordingly, there is a need in the art for a method of manufacturing a thin film solar cell that uses an alternative to CBD CdS technology for inserting a buffer layer without additional chemical steps.
本発明は、光起電力素子を製造するための新規方法及びそれによって製造された光起電力素子に関する。   The present invention relates to a novel method for producing a photovoltaic device and to the photovoltaic device produced thereby.
好ましい実施態様では、n型層は処理の延長として形成され、それによりCIGSが460℃未満の高温でIn、Ga及びSeの活量にさらされる。このような実施態様では、In、Ga及びSeの活量は実質的に変化しないが、基材の温度は、In、Ga及びSeの活量がCIGS吸収体層ともはや反応しない点まで意図的に又はより高温からの自然冷却の結果として低下する。その代わりに、これらの元素は堆積して、接合パートナーとして及びCIGSとそれに続く真性ZnO層との間のバッファとして作用する(In,Ga)ySeのn型層の形態でそれ自体が化合物を形成する。真性透明酸化物層は、透明導電性酸化物層と上部金属グリッドを支持する。   In a preferred embodiment, the n-type layer is formed as an extension of the process whereby CIGS is exposed to In, Ga and Se activities at high temperatures below 460 ° C. In such embodiments, the In, Ga, and Se activities are not substantially changed, but the substrate temperature is deliberate to the point that the In, Ga, and Se activities no longer react with the CIGS absorber layer. Or as a result of natural cooling from higher temperatures. Instead, these elements deposit and form themselves in the form of an (In, Ga) ySe n-type layer that acts as a junction partner and as a buffer between CIGS and the subsequent intrinsic ZnO layer. To do. The intrinsic transparent oxide layer supports the transparent conductive oxide layer and the upper metal grid.
銅−インジウム−セレン(CuInSe2)と銅−インジウム−ガリウム−セレン(CuIn1-xGaxSe2)の黄銅鉱三元薄膜は、その両方が一般にCu(In,Ga)Se2又はCIGSと称され、近年、半導体素子に関して多大な関心及び研究の対象となっている。硫黄も同様に置換することができ及び時にセレンと置換され、その化合物は、これらの可能性のある組み合わせのすべてを包含するように、より一般的にCu(In,Ga)(Se,S)2と称されることもある。これらの素子はまた、それらの構成元素のグループに従ってI−III−VI2素子とも称される。これらの素子は、光起電力素子又は太陽電子の吸収体用途に関して特に興味深い。光起電力の用途に関して、p型CIGS層をn型CdS層と組み合わせてp−nヘテロ接合CIGS/CdS素子が形成される。 Copper-indium-selenium (CuInSe 2 ) and copper-indium-gallium-selenium (CuIn 1-x Ga x Se 2 ) chalcopyrite ternary films, both of which are generally Cu (In, Ga) Se 2 or CIGS and In recent years, it has become a subject of great interest and research on semiconductor devices. Sulfur can be substituted as well, and sometimes substituted with selenium, and the compound is more commonly Cu (In, Ga) (Se, S) to encompass all of these possible combinations. Sometimes called 2 . These elements are also referred to as I-III-VI 2 elements according to their constituent element groups. These devices are of particular interest for photovoltaic devices or solar electron absorber applications. For photovoltaic applications, a p-n heterojunction CIGS / CdS element is formed by combining a p-type CIGS layer with an n-type CdS layer.
CIGSの直接エネルギーギャップにより、大きな光吸収係数が得られ、1〜2μm程度の薄膜の使用が可能となる。CIGS素子の追加の利点はその長期間安定性である。   A large light absorption coefficient is obtained by the direct energy gap of CIGS, and a thin film of about 1 to 2 μm can be used. An additional advantage of CIGS elements is their long-term stability.
図1を参照すると、すべての層が、複数の機能材料、例えば、ガラス、金属、セラミック又はプラスチックのうちの1つを含むことができる基材105の上に堆積される。基材の厚さは約10.0μm〜10mmであることができ、硬質でもよいし又は軟質でもよいことが意図される。好ましくは、基材は相互接続のためのバック接点として機能する。   Referring to FIG. 1, all layers are deposited on a substrate 105 that can include one of a plurality of functional materials, such as glass, metal, ceramic, or plastic. The thickness of the substrate can be about 10.0 μm to 10 mm and is intended to be hard or soft. Preferably, the substrate functions as a back contact for interconnection.
基材105上には、バリヤー層110が直接堆積される。バリヤー層110は、薄い導体又は非常に薄い絶縁材料を含み、基材から電池の残りの部分までの望ましくない元素又は化合物の外部拡散をブロックする役目を果たす。このバリヤー層110は、クロム、チタン、酸化ケイ素、窒化チタン、及び必要な導電性と耐久性を有する関連する材料を含むことができる。より薄いバリヤー層110を有することが好ましい。   A barrier layer 110 is deposited directly on the substrate 105. The barrier layer 110 comprises a thin conductor or very thin insulating material and serves to block out-diffusion of undesirable elements or compounds from the substrate to the rest of the battery. This barrier layer 110 can include chromium, titanium, silicon oxide, titanium nitride, and related materials having the necessary electrical conductivity and durability. It is preferable to have a thinner barrier layer 110.
次の堆積層は、非反応性金属、例えば、モリブデンを含むバック接点層120である。バック接点層は、太陽電池のための電気接点である。この層は、他の層から太陽電池構造まで化学化合物が拡散するのを防ぐ役目もさらに果たすことができる。この層はまた、基材105と太陽電池構造との間の熱膨張の緩衝体としての役目も果たす。   The next deposited layer is a back contact layer 120 comprising a non-reactive metal, such as molybdenum. The back contact layer is an electrical contact for the solar cell. This layer can further serve to prevent chemical compounds from diffusing from other layers to the solar cell structure. This layer also serves as a buffer for thermal expansion between the substrate 105 and the solar cell structure.
次の層はバック接点層120の上に堆積され、吸収体とバック接点との間の接着を改善するためのp型半導体層130である。p型半導体層130は、I−IIIa,b−VIイソタイプ半導体であることができるが、好ましい組成は、先の化合物のいずれかと合金されたCu:Ga:Se、Cu:Al:Se又はCu:In:Seである。 The next layer is a p-type semiconductor layer 130 deposited on the back contact layer 120 to improve the adhesion between the absorber and the back contact. The p-type semiconductor layer 130 can be an I-III a, b -VI isotype semiconductor, but preferred compositions are Cu: Ga: Se, Cu: Al: Se or Cu alloyed with any of the preceding compounds. : In: Se.
この実施態様では、p型吸収体層155の形成は、多くの別々の層の相互拡散を伴う。最終的には、図1に見られるように、p型半導体層130及び150が複合して、太陽エネルギーの主要な吸収体として作用する単一複合層155になる。この実施態様では、アルカリ材料140は、以降の層の成長の種をまく目的で、並びに吸収体層155のキャリヤー濃度及び粒子サイズを増加させ、それによりPV電池の変換効率を向上させる目的で加えられる。   In this embodiment, the formation of the p-type absorber layer 155 involves the interdiffusion of many separate layers. Eventually, as seen in FIG. 1, the p-type semiconductor layers 130 and 150 are combined into a single composite layer 155 that acts as the primary absorber of solar energy. In this embodiment, the alkaline material 140 is added for the purpose of seeding subsequent layer growth and for the purpose of increasing the carrier concentration and particle size of the absorber layer 155, thereby improving the conversion efficiency of the PV cell. It is done.
さらに図1を参照すると、次の層は、CIGS吸収体層としても公知の別の半導体層150を含む。層150は、I族元素(例えば、Cu又はAg)及び/又はIII族元素(例えば、In、Ga又はAl)及び/又はVI族元素(例えば、Se及び/又はS)を含む1つ又は複数の化合物を含むことができる。好ましくは、p型層150は、I−(IIIa,IIIb)−VI2層(IIIa=In、IIIb=Ga、Al)(式中、0.0<IIIb/(IIIa+IIIb)<0.4)を含む。好ましくは、p型吸収体層は、CuIn1-x:Gax:Se2(式中、xは0.2〜0.3である)を含み、厚さは約1μm〜約3μmである。 Still referring to FIG. 1, the next layer includes another semiconductor layer 150, also known as a CIGS absorber layer. Layer 150 may include one or more of group I elements (eg, Cu or Ag) and / or group III elements (eg, In, Ga, or Al) and / or group VI elements (eg, Se and / or S). Can be included. Preferably, p-type layer 150, I- (III a, III b ) -VI 2 layer (III a = In, III b = Ga, Al) ( wherein, 0.0 <III b / (III a + III b ) includes <0.4). Preferably, p-type absorber layer, CuIn 1-x: Ga x : ( wherein, x is a 0.2 to 0.3) Se 2 wherein the thickness is about 1μm~ about 3 [mu] m.
半導体層150は、I、III及びVI族の前駆体材料又は反応したI−III−VI化合物をアルカリ材料140の上部に供給することによって形成される。1つ又は複数の半導体層は、薄層の混合物又は一連の薄層として形成することができる。   The semiconductor layer 150 is formed by supplying a group I, III and VI precursor material or reacted I-III-VI compound on top of the alkali material 140. The one or more semiconductor layers can be formed as a mixture of thin layers or as a series of thin layers.
他の実施態様では、半導体層は、スパッタターゲット前駆体の種々の組み合わせからなる多層を含む段階的な吸収体層からなることができる。例えば、Cu2Se:Ga2Se3:In2Se3又は任意の同様の組み合わせである。他の実施態様では、これらの層はSeを含まない。 In other embodiments, the semiconductor layer can comprise a graded absorber layer comprising multiple layers of various combinations of sputter target precursors. For example, Cu 2 Se: Ga 2 Se 3 : In 2 Se 3 or any similar combination. In other embodiments, these layers do not include Se.
I、III、VI族の前駆体材料は、続いて約400℃〜約600℃の温度で反応してI−III−VI2化合物材料を形成する。p型半導体130の存在は、p型吸収体層155を形成できる同種の化学及び物理表面を提供することで最適なI−III−VI2化合物の形成速度を可能にする。約400℃〜約600℃の温度で、p型半導体層130とp型半導体層150は、III族元素の交換によって相互拡散する。加えて、アルカリ材料140中に含まれるNaが半導体層150中に拡散するので、完成した素子のp型吸収体層155の成長が改善される。いったん堆積されると、層は約400℃〜600℃の温度で熱処理される。 The Group I, III, VI precursor materials are subsequently reacted at temperatures of about 400 ° C. to about 600 ° C. to form I-III-VI 2 compound materials. The presence of the p-type semiconductor 130 allows for the optimal I-III-VI 2 compound formation rate by providing a similar chemical and physical surface capable of forming the p-type absorber layer 155. At a temperature of about 400 ° C. to about 600 ° C., the p-type semiconductor layer 130 and the p-type semiconductor layer 150 are interdiffused by the exchange of group III elements. In addition, since Na contained in the alkali material 140 diffuses into the semiconductor layer 150, the growth of the p-type absorber layer 155 of the completed device is improved. Once deposited, the layer is heat treated at a temperature of about 400 ° C to 600 ° C.
p型吸収体層150の熱処理の後、光電池製造プロセスでは、引き続いてn型接合層160が堆積される。この層160は最終的に半導体層150と相互作用し、必要なp−n接合165を形成する。好ましくは、接合バッファ層は、材料が反応してCIGS材料を形成するよりはむしろn型材料を堆積するような時間及びより低い温度でIn、Se、Gaを提供することによって本発明において形成される。典型的には、これは温度が約450℃よりも低くなったときに行われ、約300℃まで続く。n型接合層の1つ又は複数の成分はp型吸収体層に全体的に又は部分的に拡散し、p−n接合の形成を助けることができる。厚さはこの層に関して約50nm〜約500nmである。接合層のバンドギャップは、p型吸収体層のバンドギャップよりも大きくてもよいし又は小さくてもよい。接合層は、先に達成された最大温度よりも低い周囲温度、例えば、上流のp型吸収体層の形成工程の間に、具体的には300℃〜450℃の範囲で形成することができる。   After the heat treatment of the p-type absorber layer 150, the n-type bonding layer 160 is subsequently deposited in the photovoltaic manufacturing process. This layer 160 ultimately interacts with the semiconductor layer 150 to form the necessary pn junction 165. Preferably, the junction buffer layer is formed in the present invention by providing In, Se, Ga at a time and at a lower temperature such that the material reacts to form a CIGS material rather than to form an n-type material. The This is typically done when the temperature is below about 450 ° C. and continues to about 300 ° C. One or more components of the n-type junction layer can diffuse in whole or in part into the p-type absorber layer to help form a pn junction. The thickness is about 50 nm to about 500 nm for this layer. The band gap of the bonding layer may be larger or smaller than the band gap of the p-type absorber layer. The bonding layer can be formed at an ambient temperature lower than the previously achieved maximum temperature, for example, in the range of 300 ° C. to 450 ° C., specifically during the upstream p-type absorber layer forming step. .
1つの実施態様においては、より低温の接合プロセスは、p型吸収体層が熱形成される同じチャンバーにおいて行うことができる。この実施態様によれば、完成したp型吸収体層は、In、Ga、Seの蒸気に追加の時間さらされる。同時に、温度が第1の温度から約300℃〜450℃の好ましい範囲まで下げられる。より好ましくは、より低い温度範囲は約350℃〜400℃である。この実施態様によれば、新規のバッファ層(InGa)ySeが作り出される。この実施態様では、したがって、チャンバーは、より高温の領域においてp型吸収体前駆体材料をアニールし、続いて同じチャンバーのより低温の下流領域において接合層を形成するよう構成することができる。   In one embodiment, the lower temperature bonding process can be performed in the same chamber where the p-type absorber layer is thermoformed. According to this embodiment, the completed p-type absorber layer is exposed to In, Ga, Se vapor for an additional period of time. At the same time, the temperature is lowered from the first temperature to a preferred range of about 300 ° C to 450 ° C. More preferably, the lower temperature range is from about 350 ° C to 400 ° C. According to this embodiment, a new buffer layer (InGa) ySe is created. In this embodiment, the chamber can thus be configured to anneal the p-type absorber precursor material in the hotter region, followed by forming a bonding layer in the cooler downstream region of the same chamber.
次の層は、真性透明酸化物層170である。透明真性酸化物層170は堆積され、次に吸収体とのヘテロ接合として作用する。好ましくは、透明酸化物層170は、I−III−VI2吸収体とのヘテロ接合のパートナーとして作用するII−VI又はIIIxVIy化合物を含む。例えば、酸化物は、典型的にはIn、Sn又はZnの酸化物である。好ましくは、真性層170の厚さは約10nm〜約50nmである。 The next layer is an intrinsic transparent oxide layer 170. A transparent intrinsic oxide layer 170 is deposited and then acts as a heterojunction with the absorber. Preferably, the transparent oxide layer 170 comprises a II-VI or IIIxVIy compound that acts as a heterojunction partner with the I-III-VI 2 absorber. For example, the oxide is typically an oxide of In, Sn, or Zn. Preferably, the thickness of intrinsic layer 170 is about 10 nm to about 50 nm.
最後に、導電性透明酸化物層180は、電池の電極上部として作用するよう堆積される。酸化物をドープして、それをグリッド構造に電流を流す役目を果たす導電性でかつ透明なものにする。例えば、透明導電性酸化物層180は、CVD又はスパッタによって堆積されたZnO又はITOを含むことができる。上部導電性層は、好ましくは透明で導電性であり、II族元素(例えば、Cd又はZn)及び/又はIII族元素(例えば、In又はAl)及び/又はIV族(例えば、Sn)及び/又はVI族元素(例えば、酸素)を含む化合物を含有する。   Finally, a conductive transparent oxide layer 180 is deposited to act as the cell's electrode top. Doping the oxide makes it conductive and transparent which serves to pass current through the grid structure. For example, the transparent conductive oxide layer 180 can include ZnO or ITO deposited by CVD or sputtering. The top conductive layer is preferably transparent and conductive, and comprises a group II element (eg Cd or Zn) and / or a group III element (eg In or Al) and / or a group IV (eg Sn) and / or Or a compound containing a group VI element (for example, oxygen).
グリッド構造は、導電性透明酸化物層の上部に堆積され、捕集を最適にしかつ暗さを最小限に抑えるよう設計されたパターンにおいて金属層から構成される。好ましくは、グリッドは、グリッド構造と透明導電性酸化物との間で優れた抵抗接点を保証するタイプAの薄い金属層と、外部回路に電流を流すタイプBの第2金属とを含む。典型的なグリッド金属は、タイプA:ニッケル(10nm〜約50nm)と、タイプB:アルミニウム又は銀(3〜5μm)とを含む。   The grid structure is deposited on top of the conductive transparent oxide layer and is composed of metal layers in a pattern designed to optimize collection and minimize darkness. Preferably, the grid includes a thin metal layer of type A that ensures an excellent resistive contact between the grid structure and the transparent conductive oxide, and a second metal of type B that conducts current to the external circuit. Typical grid metals include Type A: Nickel (10 nm to about 50 nm) and Type B: Aluminum or Silver (3-5 μm).
本発明は、特定の実施態様を参照して説明されたが、本発明の範囲を逸脱することなく種々の変更を行うことができかつそれらの要素を同等なもので置換できることは当業者であれば理解するであろう。加えて、本発明の範囲を逸脱することなく、特定の状態又は材料を本発明の教示に適合するよう多くの改良を行うことができる。   Although the invention has been described with reference to particular embodiments, those skilled in the art will recognize that various modifications can be made and equivalent elements can be substituted without departing from the scope of the invention. You will understand. In addition, many modifications may be made to adapt a particular state or material to the teachings of the invention without departing from the scope of the invention.
それゆえ、本発明は、発明を実施するための最良の形態として開示された特定の実施態様に限定されず、本発明は、特許請求の範囲及びその趣旨の範囲内にあるすべての実施態様を包含するものである。   Therefore, the present invention is not limited to the specific embodiments disclosed as the best mode for carrying out the invention, and the present invention covers all embodiments that fall within the scope of the claims and the spirit thereof. It is included.
吸収体層がCIGSであり、接合バッファ層が本発明の方法によって形成された光電池スタックデザインの堆積に関する本発明に従った薄膜太陽電池の実施態様を示す。Fig. 4 shows an embodiment of a thin film solar cell according to the present invention for the deposition of a photovoltaic stack design in which the absorber layer is CIGS and the junction buffer layer is formed by the method of the present invention.

Claims (11)

  1. (a)基材上にCIGSのp型半導体層を提供する工程、及び
    (b)該p型半導体層をIn+Se+Gaの蒸気に約300℃〜約450℃の温度範囲で2〜4分間さらし、n型半導体層を生成してp−n接合を形成する工程
    を含む、光起電力素子を製造するための方法。
    (A) providing a CIGS p-type semiconductor layer on a substrate; and (b) exposing the p-type semiconductor layer to In + Se + Ga vapor at a temperature range of about 300 ° C. to about 450 ° C. for 2 to 4 minutes, n A method for manufacturing a photovoltaic device comprising the step of forming a p-n junction by generating a type semiconductor layer.
  2. (a)基材上にCIGSのp型半導体層を提供する工程、及び
    (b)該p型半導体層をIn+Se+Gaの蒸気にさらして約50nm〜約500nmの厚さを得、n型半導体層を生成してp−n接合を形成する工程
    を含む、光起電力素子を製造するための方法。
    (A) providing a CIGS p-type semiconductor layer on a substrate; and (b) exposing the p-type semiconductor layer to vapor of In + Se + Ga to obtain a thickness of about 50 nm to about 500 nm. A method for manufacturing a photovoltaic device comprising the step of forming to form a pn junction.
  3. (a)CIGS層を備えた基材と、
    (b)In+Se+Gaを約300℃〜約450℃の温度範囲で2〜4分間提供することにより作製されたn型接合と
    を含む、光起電力素子。
    (A) a substrate provided with a CIGS layer;
    (B) A photovoltaic device comprising an n-type junction made by providing In + Se + Ga in a temperature range of about 300 ° C. to about 450 ° C. for 2 to 4 minutes.
  4. (a)CIGS層を備えた基材と、
    (b)In+Se+Gaを提供して約50nm〜約500nmの厚さを得、n型層を生成してp−n接合を形成することにより作製されたn型接合と
    を含む、光起電力素子。
    (A) a substrate provided with a CIGS layer;
    (B) A photovoltaic device comprising In + Se + Ga to obtain a thickness of about 50 nm to about 500 nm, and an n-type junction formed by forming an n-type layer to form a pn junction.
  5. p型吸収体層が熱形成され、次いでIn+Se+Gaの蒸気に追加の時間さらされ、同時に温度が第1の温度から約300℃〜450℃の範囲まで下げられた、光起電力素子。   A photovoltaic device, wherein the p-type absorber layer is thermoformed and then exposed to an In + Se + Ga vapor for an additional time while the temperature is lowered from a first temperature to a range of about 300 ° C to 450 ° C.
  6. 前記温度範囲が約350℃〜400℃である、請求項3に記載の素子。   The device of claim 3, wherein the temperature range is about 350 ° C. to 400 ° C.
  7. 前記温度範囲が約350℃〜400℃である、請求項5に記載の素子。   The device of claim 5, wherein the temperature range is about 350 ° C. to 400 ° C.
  8. 前記温度範囲内で(InxGa1-x2Se3層を堆積するのに十分な時間In+Se+Gaの蒸気にさらされた、請求項3に記載の素子。 Wherein within the temperature range (In x Ga 1-x) for a time sufficient to deposit a 2 Se 3 layer has been exposed to the vapor of In + Se + Ga, element according to claim 3.
  9. 前記温度範囲内で(InxGa1-x2Se3層を堆積するのに十分な時間In+Se+Gaの蒸気にさらされた、請求項5に記載の素子。 Wherein within the temperature range (In x Ga 1-x) for a time sufficient to deposit a 2 Se 3 layer has been exposed to the vapor of In + Se + Ga, element according to claim 5.
  10. 前記(InxGa1-x2Se3層が350℃〜370℃で堆積された、請求項3に記載の素子。 The device of claim 3, wherein the (In x Ga 1-x ) 2 Se 3 layer is deposited at 350 ° C. to 370 ° C. 5.
  11. 前記(InxGa1-x2Se3層が350℃〜370℃で堆積された、請求項5に記載の素子。 The device of claim 5, wherein the (In x Ga 1-x ) 2 Se 3 layer is deposited at 350 ° C. to 370 ° C. 6.
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