JP2008520101A - Thermal process for producing in-situ bonding layers in CIGS - Google Patents

Abstract

  The present invention relates generally to the field of photovoltaic technology, and more specifically to the fabrication of thin film solar cells using thermal processes. Specifically, a method for manufacturing a CIGS solar cell by an in-situ junction formation process is disclosed.

Description

  The invention disclosed herein relates generally to the field of photovoltaic technology, and more specifically to the fabrication of thin film solar cells using an in-situ bonding process.

  Relatively high-efficiency photovoltaic (“PV”) cells can be manufactured in the laboratory. However, it has proven difficult to scale these processes to a commercial scale, while achieving both reproducibility and efficiency, which are important for commercialization. Inefficient thin film manufacturing processes contribute to PV cells not effectively replacing conventional energy sources in the market. Converting laboratory batch processes into cheaper and better controlled and effective industrial processes will help advance PV technology into the mainstream market.

  Without a highly efficient thin film manufacturing process, PV cells cannot effectively replace current energy sources. To manufacture a PV cell, a thin semiconductor layer of PV material is deposited on a support layer, for example a glass, metal or plastic foil. Since thin film direct transition semiconductor materials have higher light absorption than indirect transition crystalline semiconductor materials, PV materials are deposited in a very thin continuous layer of atoms, molecules or ions. The basic photovoltaic stack design illustrates the typical structure of a PV cell. In this design, the battery comprises a substrate, a barrier layer, a back contact layer, a semiconductor layer, an alkali material layer, an n-type junction buffer layer, an intrinsic transparent oxide layer, and a conductive transparent oxide layer. including.

  Copper-indium-selenium (CIS) compounds, all or part of indium substituted with gallium (CIGS) and / or all or part of selenium substituted with sulfur (CISS) are absorbed by thin film solar cells. Most expected to use in body layer. CIGS batteries have demonstrated the highest efficiency and superior stability compared to other absorber layer compounds. Typically, CIGS films are deposited by reduced pressure system techniques. However, the multilayer including the PV element has a problem with the mass production system. Currently, there is no proven technology for continuously producing CIGS elements. In addition, typical PV cell manufacturing techniques require batch processing that entails contact operations, high capital costs, and low manufacturing output. In contrast, a continuous process can minimize capital costs and contact operations, while maximizing product throughput and yield.

  In particular, the CIGS system presents unique difficulties for manufacturers. As discussed by Ramanathan et al. On October 14, 2002, the process used to manufacture large area modules involves the deposition of a metal precursor stack followed by the formation of compounds in selenium and sulfur environments. . For photovoltaic cell applications, a p-n heterojunction CdS / CIGS element is formed by combining a p-type CIGS layer with an n-type CdS layer. However, there are problems with this process. The band gap of the CdS layer is low enough to limit the short wavelength portion of the solar spectrum that can still reach the absorber, thus lowering the current that can be collected. Such degradation is proportionally more severe for higher bandgap CIGS cells. Furthermore, this process creates hazardous waste whose disposal is a challenge for future production. Accordingly, there is a need in the art to find a practical alternative to chemical bath deposition (“CBD”) CdS processes.

Although several alternatives to the CBD CdS process have been proposed, there are no viable options in the context of large scale continuous production. Some of these include, among other things, the addition of layers composed of ZnS, ZnO, Zn (S, O), ZnSe, In ₂ S ₃ and In (OH) _x S _y . However, the insertion of these alternative buffer layers often involves more chemical steps, as well as post-deposition annealing or light irradiation to fully activate. The addition of these post-deposition steps reduces the efficiency of the manufacturing process and introduces potential handling errors and contamination to the product. Accordingly, there is a need in the art for a method of manufacturing a thin film solar cell that uses an alternative to CBD CdS technology for inserting a buffer layer without additional chemical steps.

  The present invention relates to a novel method for producing a photovoltaic device and to the photovoltaic device produced thereby.

  In a preferred embodiment, the n-type layer is formed as an extension of the process whereby CIGS is exposed to In, Ga and Se activities at high temperatures below 460 ° C. In such embodiments, the In, Ga, and Se activities are not substantially changed, but the substrate temperature is deliberate to the point that the In, Ga, and Se activities no longer react with the CIGS absorber layer. Or as a result of natural cooling from higher temperatures. Instead, these elements deposit and form themselves in the form of an (In, Ga) ySe n-type layer that acts as a junction partner and as a buffer between CIGS and the subsequent intrinsic ZnO layer. To do. The intrinsic transparent oxide layer supports the transparent conductive oxide layer and the upper metal grid.

Copper-indium-selenium (CuInSe ₂ ) and copper-indium-gallium-selenium (CuIn _1-x Ga _x Se ₂ ) chalcopyrite ternary films, both of which are generally Cu (In, Ga) Se ₂ or CIGS and In recent years, it has become a subject of great interest and research on semiconductor devices. Sulfur can be substituted as well, and sometimes substituted with selenium, and the compound is more commonly Cu (In, Ga) (Se, S) to encompass all of these possible combinations. Sometimes called ₂ . These elements are also referred to as I-III-VI ₂ elements according to their constituent element groups. These devices are of particular interest for photovoltaic devices or solar electron absorber applications. For photovoltaic applications, a p-n heterojunction CIGS / CdS element is formed by combining a p-type CIGS layer with an n-type CdS layer.

  A large light absorption coefficient is obtained by the direct energy gap of CIGS, and a thin film of about 1 to 2 μm can be used. An additional advantage of CIGS elements is their long-term stability.

  Referring to FIG. 1, all layers are deposited on a substrate 105 that can include one of a plurality of functional materials, such as glass, metal, ceramic, or plastic. The thickness of the substrate can be about 10.0 μm to 10 mm and is intended to be hard or soft. Preferably, the substrate functions as a back contact for interconnection.

  A barrier layer 110 is deposited directly on the substrate 105. The barrier layer 110 comprises a thin conductor or very thin insulating material and serves to block out-diffusion of undesirable elements or compounds from the substrate to the rest of the battery. This barrier layer 110 can include chromium, titanium, silicon oxide, titanium nitride, and related materials having the necessary electrical conductivity and durability. It is preferable to have a thinner barrier layer 110.

  The next deposited layer is a back contact layer 120 comprising a non-reactive metal, such as molybdenum. The back contact layer is an electrical contact for the solar cell. This layer can further serve to prevent chemical compounds from diffusing from other layers to the solar cell structure. This layer also serves as a buffer for thermal expansion between the substrate 105 and the solar cell structure.

The next layer is a p-type semiconductor layer 130 deposited on the back contact layer 120 to improve the adhesion between the absorber and the back contact. The p-type semiconductor layer 130 can be an I-III _{a, b} -VI isotype semiconductor, but preferred compositions are Cu: Ga: Se, Cu: Al: Se or Cu alloyed with any of the preceding compounds. : In: Se.

  In this embodiment, the formation of the p-type absorber layer 155 involves the interdiffusion of many separate layers. Eventually, as seen in FIG. 1, the p-type semiconductor layers 130 and 150 are combined into a single composite layer 155 that acts as the primary absorber of solar energy. In this embodiment, the alkaline material 140 is added for the purpose of seeding subsequent layer growth and for the purpose of increasing the carrier concentration and particle size of the absorber layer 155, thereby improving the conversion efficiency of the PV cell. It is done.

Still referring to FIG. 1, the next layer includes another semiconductor layer 150, also known as a CIGS absorber layer. Layer 150 may include one or more of group I elements (eg, Cu or Ag) and / or group III elements (eg, In, Ga, or Al) and / or group VI elements (eg, Se and / or S). Can be included. Preferably, p-type layer _{150, I- (III a, III b} ) -VI 2 layer _{(III a = In, III b} = Ga, Al) ( _{wherein, 0.0 <III b / (III} a + III _b ) includes <0.4). Preferably, p-type absorber _{layer, CuIn 1-x: Ga x} : ( wherein, x is a 0.2 to 0.3) Se ₂ wherein the thickness is about 1μm~ about 3 [mu] m.

  The semiconductor layer 150 is formed by supplying a group I, III and VI precursor material or reacted I-III-VI compound on top of the alkali material 140. The one or more semiconductor layers can be formed as a mixture of thin layers or as a series of thin layers.

In other embodiments, the semiconductor layer can comprise a graded absorber layer comprising multiple layers of various combinations of sputter target precursors. For example, Cu ₂ Se: Ga ₂ Se ₃ : In ₂ Se ₃ or any similar combination. In other embodiments, these layers do not include Se.

The Group I, III, VI precursor materials are subsequently reacted at temperatures of about 400 ° C. to about 600 ° C. to form I-III-VI ₂ compound materials. The presence of the p-type semiconductor 130 allows for the optimal I-III-VI ₂ compound formation rate by providing a similar chemical and physical surface capable of forming the p-type absorber layer 155. At a temperature of about 400 ° C. to about 600 ° C., the p-type semiconductor layer 130 and the p-type semiconductor layer 150 are interdiffused by the exchange of group III elements. In addition, since Na contained in the alkali material 140 diffuses into the semiconductor layer 150, the growth of the p-type absorber layer 155 of the completed device is improved. Once deposited, the layer is heat treated at a temperature of about 400 ° C to 600 ° C.

  After the heat treatment of the p-type absorber layer 150, the n-type bonding layer 160 is subsequently deposited in the photovoltaic manufacturing process. This layer 160 ultimately interacts with the semiconductor layer 150 to form the necessary pn junction 165. Preferably, the junction buffer layer is formed in the present invention by providing In, Se, Ga at a time and at a lower temperature such that the material reacts to form a CIGS material rather than to form an n-type material. The This is typically done when the temperature is below about 450 ° C. and continues to about 300 ° C. One or more components of the n-type junction layer can diffuse in whole or in part into the p-type absorber layer to help form a pn junction. The thickness is about 50 nm to about 500 nm for this layer. The band gap of the bonding layer may be larger or smaller than the band gap of the p-type absorber layer. The bonding layer can be formed at an ambient temperature lower than the previously achieved maximum temperature, for example, in the range of 300 ° C. to 450 ° C., specifically during the upstream p-type absorber layer forming step. .

  In one embodiment, the lower temperature bonding process can be performed in the same chamber where the p-type absorber layer is thermoformed. According to this embodiment, the completed p-type absorber layer is exposed to In, Ga, Se vapor for an additional period of time. At the same time, the temperature is lowered from the first temperature to a preferred range of about 300 ° C to 450 ° C. More preferably, the lower temperature range is from about 350 ° C to 400 ° C. According to this embodiment, a new buffer layer (InGa) ySe is created. In this embodiment, the chamber can thus be configured to anneal the p-type absorber precursor material in the hotter region, followed by forming a bonding layer in the cooler downstream region of the same chamber.

The next layer is an intrinsic transparent oxide layer 170. A transparent intrinsic oxide layer 170 is deposited and then acts as a heterojunction with the absorber. Preferably, the transparent oxide layer 170 comprises a II-VI or IIIxVIy compound that acts as a heterojunction partner with the I-III-VI ₂ absorber. For example, the oxide is typically an oxide of In, Sn, or Zn. Preferably, the thickness of intrinsic layer 170 is about 10 nm to about 50 nm.

  Finally, a conductive transparent oxide layer 180 is deposited to act as the cell's electrode top. Doping the oxide makes it conductive and transparent which serves to pass current through the grid structure. For example, the transparent conductive oxide layer 180 can include ZnO or ITO deposited by CVD or sputtering. The top conductive layer is preferably transparent and conductive, and comprises a group II element (eg Cd or Zn) and / or a group III element (eg In or Al) and / or a group IV (eg Sn) and / or Or a compound containing a group VI element (for example, oxygen).

  The grid structure is deposited on top of the conductive transparent oxide layer and is composed of metal layers in a pattern designed to optimize collection and minimize darkness. Preferably, the grid includes a thin metal layer of type A that ensures an excellent resistive contact between the grid structure and the transparent conductive oxide, and a second metal of type B that conducts current to the external circuit. Typical grid metals include Type A: Nickel (10 nm to about 50 nm) and Type B: Aluminum or Silver (3-5 μm).

  Although the invention has been described with reference to particular embodiments, those skilled in the art will recognize that various modifications can be made and equivalent elements can be substituted without departing from the scope of the invention. You will understand. In addition, many modifications may be made to adapt a particular state or material to the teachings of the invention without departing from the scope of the invention.

  Therefore, the present invention is not limited to the specific embodiments disclosed as the best mode for carrying out the invention, and the present invention covers all embodiments that fall within the scope of the claims and the spirit thereof. It is included.

Fig. 4 shows an embodiment of a thin film solar cell according to the present invention for the deposition of a photovoltaic stack design in which the absorber layer is CIGS and the junction buffer layer is formed by the method of the present invention.

Claims (11)

(A) providing a CIGS p-type semiconductor layer on a substrate; and (b) exposing the p-type semiconductor layer to In + Se + Ga vapor at a temperature range of about 300 ° C. to about 450 ° C. for 2 to 4 minutes, n A method for manufacturing a photovoltaic device comprising the step of forming a p-n junction by generating a type semiconductor layer. (A) providing a CIGS p-type semiconductor layer on a substrate; and (b) exposing the p-type semiconductor layer to vapor of In + Se + Ga to obtain a thickness of about 50 nm to about 500 nm. A method for manufacturing a photovoltaic device comprising the step of forming to form a pn junction. (A) a substrate provided with a CIGS layer;
(B) A photovoltaic device comprising an n-type junction made by providing In + Se + Ga in a temperature range of about 300 ° C. to about 450 ° C. for 2 to 4 minutes. (A) a substrate provided with a CIGS layer;
(B) A photovoltaic device comprising In + Se + Ga to obtain a thickness of about 50 nm to about 500 nm, and an n-type junction formed by forming an n-type layer to form a pn junction.   A photovoltaic device, wherein the p-type absorber layer is thermoformed and then exposed to an In + Se + Ga vapor for an additional time while the temperature is lowered from a first temperature to a range of about 300 ° C to 450 ° C.   The device of claim 3, wherein the temperature range is about 350 ° C. to 400 ° C.   The device of claim 5, wherein the temperature range is about 350 ° C. to 400 ° C. Wherein within the temperature range (In _x Ga _1-x) for a time sufficient to deposit a ₂ Se ₃ layer has been exposed to the vapor of In + Se + Ga, element according to claim 3. Wherein within the temperature range (In _x Ga _1-x) for a time sufficient to deposit a ₂ Se ₃ layer has been exposed to the vapor of In + Se + Ga, element according to claim 5. The device of claim 3, wherein the (In _x Ga _1-x ) ₂ Se ₃ layer is deposited at 350 ° C. to 370 ° C. 5. The device of claim 5, wherein the (In _x Ga _1-x ) ₂ Se ₃ layer is deposited at 350 ° C. to 370 ° C. 6.

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