JP2008516346A5 - - Google Patents

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JP2008516346A5
JP2008516346A5 JP2007535843A JP2007535843A JP2008516346A5 JP 2008516346 A5 JP2008516346 A5 JP 2008516346A5 JP 2007535843 A JP2007535843 A JP 2007535843A JP 2007535843 A JP2007535843 A JP 2007535843A JP 2008516346 A5 JP2008516346 A5 JP 2008516346A5
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JP4857274B2 (ja
JP2008516346A (ja
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JP2007535843A 2004-10-12 2005-10-06 超並列型スーパーコンピュータでのアプリケーション・レイアウトの最適化 Expired - Fee Related JP4857274B2 (ja)

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Application Number Priority Date Filing Date Title
US10/963,101 US8117288B2 (en) 2004-10-12 2004-10-12 Optimizing layout of an application on a massively parallel supercomputer
US10/963,101 2004-10-12
PCT/US2005/036196 WO2006044258A1 (en) 2004-10-12 2005-10-06 Optimizing layout of an aplication on a massively parallel supercomputer

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JP2008516346A JP2008516346A (ja) 2008-05-15
JP2008516346A5 true JP2008516346A5 (https=) 2008-08-21
JP4857274B2 JP4857274B2 (ja) 2012-01-18

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JP2007535843A Expired - Fee Related JP4857274B2 (ja) 2004-10-12 2005-10-06 超並列型スーパーコンピュータでのアプリケーション・レイアウトの最適化

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US (1) US8117288B2 (https=)
EP (1) EP1807758A1 (https=)
JP (1) JP4857274B2 (https=)
CN (1) CN100568183C (https=)
WO (1) WO2006044258A1 (https=)

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