JP4857274B2 - 超並列型スーパーコンピュータでのアプリケーション・レイアウトの最適化 - Google Patents

超並列型スーパーコンピュータでのアプリケーション・レイアウトの最適化 Download PDF

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JP4857274B2
JP4857274B2 JP2007535843A JP2007535843A JP4857274B2 JP 4857274 B2 JP4857274 B2 JP 4857274B2 JP 2007535843 A JP2007535843 A JP 2007535843A JP 2007535843 A JP2007535843 A JP 2007535843A JP 4857274 B2 JP4857274 B2 JP 4857274B2
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バノット、ギャン、ヴィ
ガーラ、アラン
ハイデルベルガー、フィリップ
ローレス、オーエン、エム
セクストン、ジェイムズ、シー
ウォークアップ、ロバート、イー
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs

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JP2007535843A 2004-10-12 2005-10-06 超並列型スーパーコンピュータでのアプリケーション・レイアウトの最適化 Expired - Fee Related JP4857274B2 (ja)

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US10/963,101 US8117288B2 (en) 2004-10-12 2004-10-12 Optimizing layout of an application on a massively parallel supercomputer
US10/963,101 2004-10-12
PCT/US2005/036196 WO2006044258A1 (en) 2004-10-12 2005-10-06 Optimizing layout of an aplication on a massively parallel supercomputer

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JP2008516346A5 JP2008516346A5 (https=) 2008-08-21
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US (1) US8117288B2 (https=)
EP (1) EP1807758A1 (https=)
JP (1) JP4857274B2 (https=)
CN (1) CN100568183C (https=)
WO (1) WO2006044258A1 (https=)

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EP1807758A1 (en) 2007-07-18
US8117288B2 (en) 2012-02-14
WO2006044258A1 (en) 2006-04-27
CN101048736A (zh) 2007-10-03
US20060101104A1 (en) 2006-05-11
CN100568183C (zh) 2009-12-09
JP2008516346A (ja) 2008-05-15

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