JP2008311484A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that has sufficiently reduced parasitic resistance while securing the flatness of a semiconductor substrate. <P>SOLUTION: A semiconductor device includes: a semiconductor substrate 100; a dummy active layer 103 formed on a surface of the semiconductor substrate 100; a shield insulation film 109 formed on the surface, which has the dummy active layer 103, of the semiconductor substrate 100; a shield layer 110 formed on the shield insulation film 109; an interlayer dielectric 111 formed on the semiconductor substrate 100 so as to cover the shield insulation film 109 and the shield layer 110; and a conductor pad 114 formed on the interlayer dielectric 111 so as to be located above the shield layer 110. The semiconductor device has sufficiently reduced parasitic resistance while stabilizing the flatness of the semiconductor substrate 100 by CMP. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a high-frequency signal input unit and a manufacturing method thereof.

  In order to stably operate a high frequency circuit, particularly a semiconductor device such as a low noise amplifier, it is important to reduce the parasitic resistance of the semiconductor substrate.

As a semiconductor device for reducing the parasitic resistance of a semiconductor substrate, a shield layer grounded to the ground, for example, a polysilicon having a silicide layer on the surface, below a conductor pad as a signal input portion formed on an interlayer insulating layer A semiconductor device in which a layer is formed on a semiconductor substrate by the same process as that for forming an element is known (see, for example, Patent Document 1).

However, in this conventional semiconductor device, the entire surface of the semiconductor substrate under the shield layer below the conductor pad is a field layer such as STI (Shallow Trench Isolation). Therefore, CMP (Chemical Mechanical Polishing) is performed in the manufacturing process of the semiconductor device. Therefore, when flattening the semiconductor substrate, the flatness of the semiconductor substrate cannot be sufficiently ensured.

On the other hand, by forming a dummy active layer in a certain range on the surface of the semiconductor substrate on which the field layer below the conductor pad is formed, the planarization of the semiconductor substrate by CMP is stabilized, and a silicide layer is formed on the surface of the dummy active layer. A semiconductor device is known in which parasitic resistance of a semiconductor substrate is reduced by forming (see, for example, Patent Document 2).

However, in this conventional semiconductor device, a part of the input high-frequency signal leaks into the semiconductor substrate through the dummy active layer formed on the surface of the semiconductor substrate in order to improve flatness. There is a possibility that the parasitic resistance cannot be sufficiently reduced.
Japanese Patent Laid-Open No. 2000-223584 (FIG. 6) JP 2003-224189 (FIG. 1)

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device in which parasitic resistance is sufficiently reduced while ensuring flatness of a semiconductor substrate.

  In order to achieve the above object, a semiconductor device of one embodiment of the present invention includes a semiconductor substrate, a dummy active layer formed on a surface of the semiconductor substrate, a shield insulating film formed on the dummy active layer, A shield layer formed on the shield insulation film; an interlayer insulation layer formed on the semiconductor substrate so as to cover the shield insulation film and the shield layer; and the interlayer insulation layer positioned above the shield layer And a conductor pad formed thereon.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: etching a part of a semiconductor substrate to form a groove on a surface of the semiconductor substrate; and a field layer on the semiconductor substrate and in the groove. Polishing the field layer outside the trench to expose the semiconductor substrate, forming an element formation region and a dummy active layer on the surface of the semiconductor substrate, respectively, the element formation region and the element Implanting impurity ions into the dummy active layer; forming an insulating film on the semiconductor substrate including the element forming region and the dummy active layer forming region; and forming a conductive layer on the insulating film; The conductive layer is etched, and a gate electrode is positioned on the dummy active layer on the insulating film positioned on the element formation region. Forming a shield layer on the insulating film, etching the insulating film using the gate electrode and the shield layer as a mask, a gate insulating film under the gate electrode, and a shield insulating film under the shield layer; A step of forming an interlayer insulating layer on the semiconductor substrate so as to cover the gate electrode and the shield layer; and a conductor pad on the interlayer insulating layer so as to be positioned above the shield layer. And a step of forming the structure.

  According to the present invention, it is possible to provide a semiconductor device in which parasitic resistance is sufficiently reduced while ensuring flatness of a semiconductor substrate.

  A semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described below with reference to the drawings.

First, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment, and FIG. 2 is a plan view showing the surface of the semiconductor substrate 100 below the conductor pad 114 in FIG. Further, the plan view shown in FIG. 2 shows the conductor pad 114, the interlayer insulating layer 111, the shield layer 110, and the shield insulating film 109 in a perspective view for easy understanding.

  In the semiconductor device according to this example, an STI (field layer 101) in which an insulating layer such as a silicon oxide film or a silicon nitride film is embedded is formed on the surface of a silicon substrate which is the semiconductor substrate 100. On the surface of the semiconductor substrate 100, an element formation region 102 containing impurity ions, a dummy active layer 103, and a substrate potential extraction region 104 are formed by a field layer 101, respectively.

Here, the dummy active layer 103, which will be described later, improves the flatness by uniformly adjusting the polishing characteristics of the entire semiconductor substrate 100 when part of the embedded field layer 101 is polished and removed by CMP. This is a dummy diffusion region formed for this purpose.

A plurality of elements are formed on the element formation region 102. The element includes a gate insulating film 105 formed on the semiconductor substrate 100, a gate electrode 106 formed on the gate insulating film 105, a side surface of the gate insulating film 105, a gate side wall insulating film 107 formed on the side surface of the gate electrode 106, a gate. The dummy active layer 103 formed on the surface of the semiconductor substrate 100 on both sides of the electrode 106 is composed of source / drain regions (not shown) containing impurity ions of a different conductivity type. Here, for example, a silicon oxide film is used for the gate insulating film 105, for example, a polysilicon layer is used for the gate electrode 106, and for example, a silicon nitride film or a silicon oxide film is used for the gate sidewall insulating film 107. Further, in order to reduce the resistance of the gate electrode 106 and the source / drain region, a silicide layer 108 such as TiSi ₂ , CoSi ₂ , NiSi, PtSi ₂ is formed on the surface of the gate electrode 106 and the source / drain region. . Note that the silicide layer 108 is also formed on the surface of the substrate potential extraction region 104 in order to facilitate extraction of the substrate potential to the outside of the semiconductor device.

In addition, on the surface of the semiconductor substrate 100 on which the field layer 101 and the dummy active layer 103 are formed, leakage of an input high-frequency signal into the semiconductor substrate 100 is prevented, and a parasitic resistance that is a resistance component of the semiconductor substrate 100 is provided. In order to reduce this, a shield insulating film 109 is formed, and a shield layer 110 is further formed on the shield insulating film 109. The shield layer 110 used in the present embodiment has the same shape as that of the shield layer 110 that is generally used. For example, the shield layer 110 has a flat plate shape whose planar shape is a short shape with a side of about 110 nm.

At this time, the surface region of the semiconductor substrate 100 located immediately below the shield layer 110 has a short shape with a side of about 110 nm, similar to the planar shape of the shield layer 110, but the field layer 101 is formed in a certain range or more of this region. Then, when the embedded field layer 101 is polished and removed by CMP, the flatness of the entire semiconductor substrate 100 cannot be ensured sufficiently.

In other words, in this embodiment, the surface of the element formation region 102 is made of silicon, while the field layer 101 having a polishing rate different from that of silicon is formed in a certain range or more of the surface region of the semiconductor substrate 100 located immediately below the shield layer 110. When formed, a portion having a locally different polishing rate is generated in a part of the entire surface of the semiconductor substrate 100 to be polished, and the polishing characteristics cannot be made constant over the entire surface of the semiconductor substrate 100. As a result, when the entire surface of the semiconductor substrate 100 is polished using CMP, a portion of the semiconductor substrate 100 where polishing does not proceed sufficiently occurs, and the flatness of the entire semiconductor substrate 100 cannot be ensured sufficiently.

Therefore, in this embodiment, for example, as shown in FIG. 2, the dummy active layer 103 having the same polishing rate as the element formation region 102 is formed in a lattice pattern on the surface of the semiconductor substrate 100 below the shield layer 110. The area of the field layer 101 exposed on the surface of the semiconductor substrate 100 below the shield layer 110 is reduced, and the CMP polishing characteristics are made constant over the entire surface of the semiconductor substrate 100.

Although described later, the shield insulating film 109 can be formed at the same time as the gate insulating film 105. Therefore, in this embodiment, the shield insulating film 109 has the same thickness as the gate insulating film 105 and is formed using the same silicon oxide film as the gate insulating film 105. At this time, if the thickness of the shield insulating film 109 is the same as that of the gate insulating film 105 having the largest thickness among the gate insulating films 105 of a plurality of elements, the penetration of the high-frequency signal into the semiconductor substrate 100 is most effective. Can be prevented.

The shield layer 110 can also be formed simultaneously with the formation of the gate electrode 106. Therefore, in this embodiment, the shield layer 110 has the same thickness as the gate electrode 106 and the same polysilicon as the gate electrode 106. Formed with layers. Further, a silicide layer 108 similar to the silicide layer 108 on the surface of the gate electrode 106 is formed on the surface of the shield layer 110.

On the semiconductor substrate 100, a plurality of interlayer insulating layers 111 made of a silicon oxide film or the like are formed so as to cover the shield insulating film 109, the shield layer 110, and the element. A wiring layer 112 made of a metal material such as aluminum, tungsten, or copper is formed between the plurality of interlayer insulating layers 111. The wiring layer 112, the shield layer 110, the wiring layer 112, and the substrate potential extraction region 104 and the wiring layer 112 are electrically connected to the source / drain regions via contact plugs 113, respectively.

Further, in the semiconductor device according to the present embodiment, although not shown, the shield layer 110 is grounded to the ground through the contact plug 113 and the wiring layer 112 together with the substrate potential extraction region 104. Thereby, since the shield layer 110 and the semiconductor substrate 100 become a ground potential, the parasitic resistance which is a resistance component of the semiconductor substrate 100 can be effectively reduced.

On the interlayer insulating layer 111, conductor pads 114, which are input / output portions of the semiconductor device, are formed so as to be positioned above the shield layer 110. The conductor pad 114 is made of a metal material such as aluminum, and has a size similar to that of the generally used conductor pad 114, that is, a flat plate shape whose planar shape is a short shape having a side of about 100 nm. At this time, in order to effectively prevent leakage of a high-frequency signal input to the conductor pad 114 to the semiconductor substrate 100, the conductor pad 114 is disposed so that the entire lower surface thereof is located above the shield layer 110. . On the other hand, the conductor pad 114 is not positioned above the substrate potential extraction region 104 so that the high-frequency signal input to the conductor pad 114 does not leak to the semiconductor substrate 100 via the substrate potential extraction region 104. Is formed.

Although not shown, bonding wires for transmitting signals between the semiconductor device and the outside thereof are connected to the conductor pads 114. Furthermore, the conductor pad 114 is electrically connected to an element or the like through a number of wiring layers and contact plugs formed between the interlayer insulating layers 111.

Next, with reference to FIG. 3, the manufacturing method of the semiconductor device according to the present embodiment as described above will be described. FIG. 3 is a process cross-sectional view illustrating the method of manufacturing the semiconductor device according to this example.

First, as shown in FIG. 3A, an STI (field layer 101) is formed on the surface of a silicon substrate, which is the semiconductor substrate 100, and an element formation region 102, a dummy active layer 103, and a field layer 101 are formed on the surface of the semiconductor substrate 100 by the field layer 101. Substrate potential extraction regions 104 are partitioned and formed.

Specifically, first, a portion where the element formation region 102, the dummy active layer 103, and the substrate potential extraction region 104 on the surface of the semiconductor substrate 100 are formed is masked with a silicon oxide film and a silicon nitride film, and RIE (Reactive Ion Etching) is performed. The semiconductor substrate 100 is removed by etching to form a groove 115 on the surface of the semiconductor substrate 100.

Next, a field layer 101, for example, a silicon oxide film is deposited on the inside of the formed trench 115 and the semiconductor substrate 100 on which a silicon nitride film or the like is formed by a CVD (Chemical Vapor Deposition) method, and further, CMP (Chemical Mechanical Polishing) is performed. The semiconductor substrate 100 is exposed by polishing and removing the silicon oxide film and silicon nitride film outside the trench 115, and the field layer 101, the element formation region 102, and the dummy active layer 103 are formed on the surface of the semiconductor substrate 100, respectively. Further, impurity ions are implanted into the element formation region 102 and the dummy active layer 103 to form a diffusion region.

At this time, when the dummy active layer is not formed between the field layers on the surface of the semiconductor substrate as in the prior art, the silicon oxide film and the silicon nitride film are removed by polishing by CMP and exposed when the semiconductor substrate starts to be exposed. Since the polishing rate differs greatly between the element isolation region on the surface of the semiconductor substrate and in the vicinity of the field layer, the polishing characteristics on the entire surface of the semiconductor substrate may be adversely affected, and the flatness of the semiconductor substrate may not be sufficiently ensured.

In contrast, in this embodiment, since the dummy active layer 103 is formed in a predetermined range between the field layers 101 on the surface of the semiconductor substrate 100, the silicon oxide film and the silicon nitride film are polished and removed by CMP to remove the semiconductor substrate. Even when the surface of the semiconductor substrate 100 begins to be exposed, the polishing rate in the vicinity of the element isolation region on the exposed surface of the semiconductor substrate 100 and the field layer 101 can be made substantially equal. The flatness of the semiconductor substrate 100 can be sufficiently ensured.

Next, as shown in FIG. 3B, an insulating film 116 such as a silicon oxide film whose thickness is partially changed is formed on the semiconductor substrate 100. Further, after a polysilicon layer is formed on the insulating film 116 by using, for example, a CVD method, impurity ions are implanted into the polysilicon layer and thermally diffused. In this manner, the conductive layer 117 is formed over the insulating film 116. As another example of the conductive layer 117, a doped polysilicon layer or a metal layer such as tungsten may be used.

Here, the insulating films 116 having partially different thicknesses are formed as follows. An insulating film 116 is formed on the semiconductor substrate 100 by using, for example, a CVD method, and then a predetermined portion of the insulating film 116 on the element formation region 102 is removed by etching by photolithography to form an opening. Further, the same insulating film 116, in this embodiment a silicon oxide film, is formed on the element formation region 102 and the insulating film 116 below the opening. In this way, by repeating the partial etching of the insulating film 116 and the re-formation of the insulating film 116, the insulating film 116 having partially different thicknesses can be formed on the element formation region 102.

Further, here, in order to effectively reduce the high-frequency signal leaking into the semiconductor substrate 100 via the dummy active layer 103, the insulating film 116 on the dummy active layer 103 is the most of the insulating films 116 on the element region. It is preferable to form the same thickness as the thick part, for example, about 6 nm.

Next, as shown in FIG. 3C, the conductive layer 117 on the insulating film 116 is etched by photolithography, so that the gate electrode 106, the dummy active layer 103, and the field layer 101 are formed above the element formation region 102. A shield layer 110 is formed above. At this time, when the plurality of gate electrodes 106 and the shield layer 110 are formed on the semiconductor substrate 100 as in this embodiment, they can be formed by the same etching process.

Further, the insulating film 116 is etched using the gate electrode 106 and the shield layer 110 as a mask to form the gate insulating film 105 under the gate electrode 106 and the shield insulating film 109 under the shield layer 110. Also in this case, the plurality of gate insulating films 105 and the shield insulating film 109 can be formed by the same etching process.

Subsequently, a silicon oxide film is formed on the semiconductor substrate 100 and the gate electrode 106 by a CVD method or the like, and further this silicon oxide film is etched back, whereby a gate sidewall is formed on the sidewalls of the gate electrode 106 and the gate insulating film 105. An insulating film 107 is formed. Thereafter, impurity ions having a conductivity type different from that of the diffusion region are implanted on the element formation region 102 on the surface of the semiconductor substrate 100 using the gate electrode 106, the gate insulating film 105, and the gate sidewall insulating film 107 as a mask, and the impurity ions are thermally diffused. As a result, source / drain regions (not shown) are formed. Further, silicide such as TiSi ₂ , CoSi ₂ , NiSi, PtSi _2, etc. is formed on the surface of the substrate electrode 100 on the surface of the semiconductor substrate 100 in a self-aligned manner by the salicide process on the surfaces of the substrate electrode extraction region 104, source / drain regions, gate electrode 106 and shield layer 110. Layer 108 is formed.

Next, as illustrated in FIG. 3D, an interlayer insulating layer 111 having a stacked structure is formed on the semiconductor substrate 100 so as to cover the gate insulating film 105, the gate electrode 106, the shield insulating film 109, and the shield layer 110. For example, a silicon oxide film is used as the interlayer insulating layer 111, but a low dielectric constant insulating film such as an organic film may be used in order to reduce the wiring capacitance.

A wiring layer 112 made of copper or aluminum or the like is formed between the interlayer insulating layers 111, and the wiring layer 112 and the shield layer 110, the wiring layer 112 and the substrate potential extraction region 104, the wiring layer 112 and the source / drain are formed. The regions are electrically connected through contact plugs 113 made of copper, aluminum, or the like. At this time, although not shown, the wiring layer 112 electrically connected to the shield layer 110 and the substrate potential extraction region 104 via a contact is grounded to the ground, and the shield layer 110 and the semiconductor substrate 100 are set to the ground potential. To do. Further, a plurality of wiring layers 112 and contact plugs 113 that electrically connect them are formed at predetermined positions in the interlayer insulating layer 111, thereby electrically connecting the wiring layers 112 and elements to each other. Build a wiring circuit.

Subsequently, a conductor pad 114 which is an input / output part of the semiconductor device is formed on the interlayer insulating layer 111 so as to be positioned above the shield layer 110. The conductor pad 114 can be formed by forming aluminum on the interlayer insulating layer 111 by sputtering, for example, and then etching aluminum other than the upper part of the shield layer 110 by photolithography.

In order to prevent a high-frequency signal input to the conductor pad 114 from leaking to the semiconductor substrate 100 via the substrate potential extraction region 104, the conductor pad 114 is not formed above the substrate potential extraction region 104. To.

Although not shown, the conductor pads 114 are connected to bonding wires serving as input / output terminals and contact plugs 113 for electrical connection with a wiring circuit formed between the interlayer insulating layers 111.

In the semiconductor device according to this embodiment manufactured as described above, the shield layer 110 having the silicide layer 108 on the surface is formed immediately below the conductor pad 114 to which a high-frequency signal is input. Parasitic resistance can be reduced. Furthermore, since the shield layer 110 is grounded together with the semiconductor substrate 100, the parasitic resistance of the semiconductor substrate 100 can be more effectively reduced.

In the semiconductor device according to the present embodiment, the rectangular dummy active layer 103 is formed in a lattice pattern on the field layer 101 on the surface of the semiconductor substrate 100 below the shield layer 110. By forming the dummy active layer 103 in this way, the coverage of the surface of the semiconductor substrate can be adjusted, the planarization of the semiconductor substrate 100 by CMP can be stabilized, and the flatness of the semiconductor substrate 100 can be sufficiently secured. be able to.

Further, according to the semiconductor device of this embodiment, the shield insulating film 109 having a certain thickness is formed between the shield layer 110 and the dummy active layer 103 formed on the surface of the semiconductor substrate 100 below the shield layer 110. ing. Therefore, as compared with the conventional semiconductor device in which the shield layer 110 is directly formed on the surface of the dummy active layer 103, when a high frequency signal is input, the signal leaks from the shield layer 110 to the semiconductor substrate 100 via the dummy active layer 103. Since the high-frequency signal can be shielded by the shield insulating film 109, the parasitic resistance of the semiconductor substrate 100 can be reduced.

Further, according to the method of manufacturing a semiconductor device according to the present embodiment, the shield layer 110, the shield insulating film 109, and the silicide layer 108 on the surface of the shield layer 110 are formed on the surface of the gate electrode 106, the gate insulating film 105, and the surface of the gate electrode 106. Since the silicide layer 108 can be formed at the same time, a semiconductor device can be manufactured by a simple method.

(Modification of Example)
Next, a modification of the semiconductor device according to the above-described embodiment will be described with reference to FIG. FIG. 4 is a plan view showing the surface of the semiconductor substrate below the conductor pad 114 of the semiconductor device of this modification. Further, the plan view shown in FIG. 4 shows the conductor pad 114, the interlayer insulating layer 111, the shield layer 110, and the shield insulating film 109 in a perspective view for easy understanding. The semiconductor device according to this modification differs from the semiconductor device according to the embodiment in the shape of the dummy active layers 203 and 303 formed on the surface of the semiconductor substrate 100 below the shield layer 110, and other configurations and manufacturing methods. Is the same as in the example. Therefore, the same parts as those of the semiconductor device of the embodiment are denoted by the same reference numerals, and the description of the same parts is omitted.

As described above, in order to make the CMP polishing characteristics constant over the entire surface of the semiconductor substrate 100, the field layer 101 exposed on the surface of the semiconductor substrate 100 below the shield layer 110, which is a part of the polishing surface, needs to be within a certain range. There is. As a more specific example, when the surface region of the semiconductor substrate 100 below the shield layer 110 has a short shape with a side of about 100 nm, the polishing rate of the element formation region 102 and the surface of the semiconductor substrate 100 below the shield layer 110 is substantially the same. Therefore, it is preferable that the surface of the field layer 101 exposed on the surface of the semiconductor substrate 100 below the shield layer 110 has a short shape with sides of 30 nm and 60 nm or less.

Therefore, in this modified example, as shown in FIG. 4A, the dummy active layer 203 having a cross-shaped surface is formed on the surface of the semiconductor substrate 100 below the shield layer 110, thereby forming the semiconductor substrate 100 below the shield layer 110. The surface field layer 101 is divided, and the area of the field layer 101 exposed on the surface of the semiconductor substrate 100 below the shield layer 110 is divided into short shapes having a side of about 50 nm (the length indicated by a in FIG. 4A). To do. Further, as shown in FIG. 4B, the cross-shaped dummy active layer 203 formed on the surface of the semiconductor substrate 100 below the shield layer 110 is combined with the L-shaped dummy active layer 303. By doing so, the area of the field layer 101 exposed on the surface of the semiconductor substrate 100 below the shield layer 110 may be further reduced.

In the semiconductor device according to the present modification, the dummy active layers 203 and 303 formed on the surface of the semiconductor substrate 100 below the shield layer 110 are formed in a predetermined shape, and the surface of the field layer 101 on the surface of the semiconductor substrate 100 below the shield layer 110. By adjusting the shape, planarization of the semiconductor substrate 100 by CMP can be further stabilized and the planarity of the semiconductor substrate 100 can be further improved as compared with the semiconductor device according to the embodiment.

Further, in the semiconductor device according to this modification, similarly to the semiconductor device according to the embodiment, the shield layer 110 and the shield layer 110 having the silicide layer 108 on the surface are formed below the conductor pad 114 to which a high-frequency signal is input. Therefore, the input high frequency signal can be effectively shielded, and the parasitic resistance of the semiconductor substrate 100 can be reduced.

Also in the method of manufacturing the semiconductor device according to this example, as in the example, the shield layer 110, the shield insulating film 109, and the silicide layer 108 on the surface of the shield layer 110 are replaced with the gate electrode 106, the gate insulating film 105, and the gate of the element. Since the silicide layer 108 on the surface of the electrode 106 can be formed at the same time, a semiconductor device can be manufactured by a simple method.

In addition, this invention is not limited to the Example mentioned above or the modification of an Example, In the range which does not deviate from the summary of invention, it can change and implement variously.

For example, the surface shape of the field layer 101 and the dummy active layers 103, 203, and 303 exposed on the surface of the semiconductor substrate 100 below the shield layer 110 may be other shapes than those shown in the embodiments and the modified examples of the embodiments. Specifically, the shape of the exposed surface of the dummy active layer may be a stripe shape or the like, and it is only necessary that the planarization of the semiconductor substrate 100 by CMP can be stabilized by forming the dummy active layer.

In the embodiment and the like, the shield insulating film 109 is formed not only on the dummy active layers 103, 203, and 303 but also on the field layer 101, but the shield insulating film 109 is only formed on the dummy active layers 103, 203, and 303. The input high frequency signal may be prevented from leaking to the semiconductor substrate 100 via the dummy active layer 103.

In the examples and the like, the shield layer 110 has the same material and thickness as that of the gate electrode 106 in order to simplify the manufacturing process, but the shield layer 110 and the gate electrode 106 may be made of different materials.

For example, a polysilicon layer can be used for the gate electrode 106 and a metal material such as aluminum can be used for the shield layer 110. In this case, the shield layer 110 is formed by removing all the polysilicon layer except the portion where the gate electrode 106 is formed on the insulating film 116 in the manufacturing process of the semiconductor device according to the embodiment shown in FIG. Thereafter, aluminum can be formed on the insulating film 116 by sputtering, and aluminum can be formed by etching away except for a portion where the shield layer 110 is formed by photolithography.

Similarly, in the embodiment, the shield insulating film 109 has the same thickness as that of the gate insulating film 105 in order to simplify manufacturing, but the shield insulating film 109 and the gate insulating film 105 may have different thicknesses.

In this case, in the manufacturing process of the semiconductor device according to the embodiment shown in FIG. 3B, the thickness on the field layer 101 and the dummy are larger than the thickness of the insulating film 116 formed on the element formation region 102 on the surface layer of the semiconductor substrate 100. If the thickness of the insulating film 116 formed on the active layer 103 is partially increased, the shield insulating film 109 can be formed thicker than the gate insulating film 105. When the thickness of the shield insulating film 109 is increased in this way, the effect of the shield insulating film 109 that shields the high-frequency signal input from the conductor pad 114 can be further improved, and the parasitic resistance of the semiconductor substrate 100 is further reduced. be able to.

Sectional drawing which shows the structure of the semiconductor device which concerns on the Example of this invention. The top view which shows the structure of the semiconductor substrate surface under the conductor pad of the semiconductor device which concerns on the Example of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the Example of this invention. The top view which shows the structure of the semiconductor substrate surface under the conductor pad of the semiconductor device which concerns on the modification of the Example of this invention.

Explanation of symbols

100 Semiconductor substrate 101 Field layer
102 Element formation region
103 203 303 Dummy active area
104 Substrate potential extraction area
105 Gate insulation film
106 Gate electrode
107 Gate sidewall insulating film
108 Silicide layer
109 Shield insulation film
110 Shield layer
111 Interlayer insulation layer
112 Wiring layer
113 Contact plug
114 Conductive pad 115 Groove 116 Insulating film 117 Conductive layer

Claims (6)

A semiconductor substrate;
A dummy active layer formed on the surface of the semiconductor substrate;
A shield insulating film formed on the dummy active layer;
A shield layer formed on the shield insulating film;
An interlayer insulating layer formed on the semiconductor substrate so as to cover the shield insulating film and the shield layer;
A conductor pad formed on the interlayer insulating layer so as to be located above the shield layer;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein a field layer is further formed on the surface of the semiconductor substrate, and the shield insulating film is formed on the dummy active layer and the field layer. The semiconductor device according to claim 1, wherein the semiconductor substrate and the shield layer are at a ground potential. 4. The semiconductor device according to claim 1, wherein the shield layer is a polysilicon layer, and has a silicide layer on a surface thereof. 5. The semiconductor device according to claim 2, wherein the surface of the field layer under the shield insulating film is partitioned into a short shape having a side of 30 nm or more and 60 nm or less by the dummy active layer. . Etching a portion of the semiconductor substrate to form a groove in the semiconductor substrate surface;
Forming a field layer on the semiconductor substrate and in the trench;
Polishing and removing the field layer outside the groove to expose the semiconductor substrate, and forming an element formation region and a dummy active layer on the semiconductor substrate surface,
Implanting impurity ions into the element formation region and the dummy active layer;
Forming an insulating film on the semiconductor substrate including the element formation region and the dummy active layer formation region;
Forming a conductive layer on the insulating film;
Etching the conductive layer to form a gate electrode on the insulating film located on the element formation region and a shield layer on the insulating film located on the dummy active layer;
Etching the insulating film using the gate electrode and the shield layer as a mask, forming a gate insulating film under the gate electrode, and forming a shield insulating film under the shield layer;
Forming an interlayer insulating layer on the semiconductor substrate so as to cover the gate electrode and the shield layer;
Forming a conductive pad on the interlayer insulating layer so as to be located above the shield layer;
A method for manufacturing a semiconductor device, comprising:

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