JP2008310112A - Driving control circuit device for flat panel display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technique relating to a PDP device etc., for materializing efficient processing etc. of a control circuit including processing between a control circuit (waveform generating circuit section) and a nonvolatile memory (waveform ROM). <P>SOLUTION: A control circuit of the PDP device uses an SFM (serial flash memory) 130 as the nonvolatile memory, the SFM 130 is stored with waveform decode data (D1) 51 and a waveform decode address set (D2) 52 as a first waveform. An LSI (waveform generating circuit LSI) 120 stores data (d1) from the waveform decode data (D1) 51 into a first SRAM 21 of a built-in SRAM part, and stores data (d2) of one readout cycle (for example, 1SF) selected from the waveform decode address set (D2) 52 into a second SRAM 22. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a flat panel display (planar panel display device) such as a display device (plasma display device: PDP device) including a plasma display panel (PDP), and in particular, generates a waveform or the like for driving the flat panel display. The present invention relates to a drive control circuit device (IC or the like).

  A conventional PDP device has a PDP drive control circuit (abbreviated as a control circuit) using an external nonvolatile memory. In a conventional control circuit, a parallel flash having a parallel I / F (interface) is used as an external nonvolatile memory (also referred to as a waveform ROM) in which waveform data and the like (first waveform) necessary for drive control is stored. A memory (abbreviated as PFM) was employed. In the control circuit, the drive waveform stored in the PFM and the waveform data (first waveform) related to the generation are always read out with a continuous clock, and the high voltage circuit (drive) is provided through the waveform generation circuit (provided in the control circuit). The PDP is driven to display. The first waveform is, for example, an on / off control signal for a control switch of the drive circuit. Further, the control circuit does not have a buffer SRAM (a volatile memory for temporarily storing waveform data read from the PFM).

  A control circuit and a drive circuit (high voltage circuit) connected to the panel (PDP) are considered separately. By controlling the drive circuit with a drive control signal (signal generated based on the first waveform (second waveform)) from the control circuit, and applying a drive waveform (voltage) from the drive circuit to the PDP electrode The PDP display is driven.

Japanese Unexamined Patent Application Publication No. 2004-252017 (Patent Document 1) describes a technical example of signal / data transmission between a display control unit (control circuit) and a drive unit (drive circuit) in a PDP device or the like. Yes. Japanese Patent Application Laid-Open No. 2003-288042 (Patent Document 2) describes a technical example of a control circuit and a waveform generation circuit in a PDP device or the like (a technology for skipping waveform data addresses). Japanese Patent Application Laid-Open No. 2004-7546 (Patent Document 3) describes a technical example of a control circuit and a waveform generation circuit (a technique for extending the output period of waveform data) in a PDP device or the like.
JP 2004-252017 A JP 2003-288042 A JP 2004-7546 A

  The background art has the following problems. As a basic problem, with the refinement of PDP drive control, etc., the amount of drive waveform and waveform data (first waveform) related to its generation increases, and the waveform data (first waveform). It is necessary to increase the speed of control such as reading. Details are as follows.

  (1) The processing speed and efficiency of a control circuit (such as a waveform generation circuit LSI) including processing with an external nonvolatile memory has been limited. For example, since a minimum access time of 55 ns (nanoseconds) is required as the access time of the data bus of the conventional PFM, speeding up of the frequency of the read clock from the PFM and the frequency of the waveform generation circuit clock has been limited.

  (2) Further, since it is a parallel I / F (PFM) related to the data bus, address bus, etc. of the external nonvolatile memory, it requires about 40 control terminals and performs data processing of the memory. The number of terminals of the IC (a memory control IC that is a part of the control circuit) is required, which is one of the causes of cost increase.

  (3) Since the amount of waveform data (first waveform) stored in the external non-volatile memory (PFM) is large, it is necessary to provide a large-capacity PFM. It was.

  The present invention has been made in view of the above problems, and an object thereof relates to a control circuit using an external nonvolatile memory in a flat panel display such as a PDP device, and (1) a control circuit (waveform generation). Circuit) and non-volatile memory (waveform ROM) including processing between the control circuit and the panel drive display, and (2) the number of terminals such as a memory control IC provided in the control circuit. The object is to provide a technology capable of realizing cost reduction by reduction, (3) cost reduction by reducing the capacity of an external nonvolatile memory, and the like.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. In order to achieve the above object, the present invention provides a panel drive control circuit (control circuit) provided in a flat panel display (flat panel display device) such as a PDP device, and includes an external nonvolatile memory (waveform ROM). Using the drive waveform stored in the memory and the waveform data (first waveform) related to the generation, at least the waveform for driving the panel (second waveform) is generated. And having the following configuration.

  In the control circuit of the present invention, a serial I / F configuration is adopted as an I / F between the external nonvolatile memory (ROM) and the control circuit (including at least the waveform generation circuit unit that performs the above processing). That is, as the memory, a serial flash memory (abbreviated as SFM) is provided instead of the conventional PFM. In addition, in this control circuit, in response to the serial I / F configuration, the nonvolatile memory (SFM) is assumed to correspond to the first waveform, and the drive waveform decode data and the data (from the drive waveform decode data) And address data for reading out the pattern every predetermined unit. In addition, in this control circuit, as a built-in volatile memory, a first volatile memory that stores drive waveform decode data as first data, and a predetermined set number of address data as one set with one read cycle as one set. A second volatile memory storing only the first volatile memory. In the present control circuit (waveform generation circuit unit), the stored data is read from the nonvolatile memory (SFM) to the built-in volatile memory as needed, and the data stored in the memory is read to store the second data. Is generated and output to the drive circuit. With the above configuration, it is possible and effective to employ an SFM in place of the conventional PFM.

  With the above configuration, (1) faster clock frequency such as drive waveform generation clock in SFM and control circuit (waveform generation circuit unit), (2) memory of waveform generation circuit unit by serial I / F (serial data bus, etc.) A reduction in the number of terminals of the control IC and the like, and (3) a reduction in capacity by devising the format of the data stored in the SFM (first waveform) are realized.

  The configuration of this drive control circuit is, for example, as follows. In the present device, the drive waveform and waveform data related to the generation thereof are stored in the nonvolatile memory as a first waveform for each cycle composed of a plurality of clock cycles, and stored in the nonvolatile memory. 2 is used to generate a second waveform for driving the panel. As the first data (d1), a predetermined period (for example, 1) is selected from all the waveform groups for driving. A first volatile memory (SRAM or the like) that stores drive waveform decode data (D1) obtained by extracting a waveform group pattern for each clock cycle), and drive waveform decode data (D2) as second data (d2). The decode address for reading data (pattern (waveform group)) from D1) is set to the decode address set (D2) only for a predetermined one read cycle (for example, one subfield). Storing Te comprises a second volatile memory (SRAM, etc.), the. As a result, the decode data of the first volatile memory is read from the decode address of the second volatile memory, and a second waveform is generated and output. The one read cycle is a reset period, an address period, a sustain period, or the like in one or a plurality of fields or subfields or subfields.

  In the present apparatus, for example, all of the non-volatile memory used for panel drive control as drive waveform decode data (D1) of the first waveform, with one clock cycle of the first waveform as one unit. The data covering the waveform data unit is stored in advance. In other words, the drive waveform decode data (D1) is obtained by analyzing and extracting a pattern of waveform groups (waveform combinations) every predetermined period (for example, one clock cycle) from all waveform groups. Note that “one clock cycle” refers to a cycle for performing a series of processes such as reading a decode address from the memory, generating a drive waveform (second waveform), and outputting the drive waveform (high voltage circuit). Yes. Further, in the present apparatus, the decoding addresses for one set (decoding address set (D2)) as one set of decoding addresses are stored in the nonvolatile memory as many as the number of sets (types) used for panel drive control. Stored in advance.

  In this apparatus, for example, the drive waveform decode data stored in the non-volatile memory are all stored as first data in the first volatile memory immediately after the activation of the system, and thereafter the first data is stored as needed. A refresh operation is performed on the first data in one volatile memory. In the present apparatus, one read cycle of the decode address stored in the nonvolatile memory is stored in the second volatile memory immediately after the system is started and after the decode data is stored.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. The present invention relates to a control circuit using an external nonvolatile memory in a flat panel display such as a PDP device, and (1) processing efficiency of the control circuit including processing between the control circuit and the nonvolatile memory. And more efficient panel drive display, (2) Cost reduction by reducing the number of terminals such as memory control ICs in the control circuit, (3) Cost reduction by reducing the capacity of external nonvolatile memory, etc. it can.

  In particular, in the above (1), the processing speed of the control circuit can be increased by increasing the clock frequency. As a result, for example, it is possible to increase the brightness of the PDP display by allocating the time allowed for the address operation in the subfield, and allocating the time allowed for the address operation period to the sustain operation period.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

<Prerequisite technology>
In order to explain the embodiment of the present invention in an easy-to-understand manner with reference to FIG. 16, the prior art (premise technique) for the embodiment of the present invention will be briefly described. 9 to 11 and the like also relate to the prior art.

  In FIG. 16, in a control circuit unit 900 of a conventional PDP device, an LSI (waveform generation circuit LSI) 920 and a PFM 930 are connected by a parallel I / F (for example, a parallel data bus has 16 bits). In the PFM 930, waveform data (D) 950 (first waveform) is stored (corresponding to FIG. 8). The LSI 920 includes a shift register (register array) 90 and a waveform generation circuit 93. The operation of the shift register 90 is the same as that of the prior art disclosed in Patent Document 1 and the like and will not be described.

  With the internal clock of the LSI 920, the waveform data (D) 950 in the PFM 930 is selected for each SF, and is read out to the shift register (register array) 90 one cycle (one step) at a time. The waveform (second waveform) generated in 93 is output to each driver (high voltage circuit). A drive waveform is output (applied) to the PDP electrode when each control switch in each driver is on / off controlled by the output waveform (second waveform).

  In the above prior art, as the timing control, the waveform data (D) 950 is always read by accessing the PFM 930 in each SF of the field. The access time of the PFM 930 is at least about 55 ns even at high speed. For this reason, in the above prior art, the clock speed in the control of the LSI 920 and the parallel I / F is limited, and there has been a problem in speeding up the reading of the waveform data (D) 950 and the waveform generation output.

  For example, the conventional PFM 930 has 40 control terminals (address input, data input / output, write enable, output enable, chip enable, etc.). Forty terminals are also required at the terminals of the memory control IC or the like on the LSI 920 side. Such a large number of terminals increases the cost.

<This embodiment>
Based on the above, a PDP apparatus according to an embodiment of the present invention will be described with reference to FIGS. In the present embodiment, as shown in FIG. 4 and the like, waveform data (first waveform (S1)) is stored in waveform decode data (D1) 51 and waveform decode address set (D2) 52 in SFM 130. The LSI 120 stores the waveform data as needed from the SFM 130 to the built-in SRAM unit 20 (M1, M2) and stores it, and generates the second waveform (S2) from the waveform generation circuit 23. Output.

<PDP device>
In FIG. 1, the whole structure of the PDP apparatus of this Embodiment is shown. The PDP device includes a control circuit unit 100, a drive circuit unit (high voltage circuit unit) 150, and a PDP 10. The drive circuit unit 150 (151 to 153) is controlled from the control circuit unit 100. The drive circuit unit (high voltage circuit unit) 150 includes an X drive circuit 151, a Y drive circuit 152, and an address drive circuit 153. The X drive circuit 151 drives (sustain drive) the group of X electrodes (sustain electrodes) 31 of the PDP 10. The Y drive circuit 152 drives (scan drive and sustain drive) the 32 groups of Y electrodes (scan electrodes) of the PDP 10. The address drive circuit 153 drives (address drive) the group of address electrodes 33 of the PDP 10. The PDP 10 has a structure in which a display cell is configured by, for example, an intersection of a pair of an X electrode 31 and a Y electrode 32 extending in the horizontal direction and an address electrode 33 extending in the vertical direction. A pixel is composed of a set of display cells of R, G, and B colors. A display area (screen) is constituted by a matrix of display cells (pixels).

<Field and subfield>
In FIG. 2, the field and SF configuration (drive sequence) will be described as the basis of drive control of the PDP 10 by the subfield (SF) method. The field (F) is a unit associated with the display area of the PDP 10, the video vertical period (vertical synchronization signal: VS), and the image frames constituting the video. The vertical period is 1/60 seconds, for example. The field (F) is composed of a plurality (M) of SFs (SF1 to SFM) that are temporally divided for gradation expression. M is, for example, 8 to 10. The SF (SF1 to SFM) is configured to have, for example, a reset period (Tr) 71, an address period (Ta) 72, and a sustain period (Ts) 73 in order. Each SF of the field (F) is given a predetermined weight related to the luminance (Ts73). For example, in the field (F), the weights are arranged in order from the lower SF. The gradation of the pixels of the image frame is expressed by a step of selectively combining on / off of SF (SF1 to SFM) for each display cell.

  In Tr71, a reset operation for adjusting the charge state of the SF cell group is performed. In the next Ta72, an address operation for selecting ON / OFF in the SF cell group is performed. In the next Ts 73, a sustain operation is performed in which a sustain discharge is generated in the cell selected by the immediately preceding Ta 72 to emit light by repeatedly applying a sustain pulse to the pair of the X electrode 31 and the Y electrode 32.

  In the system of the present embodiment, one read cycle serving as a control unit is, for example, 1 SF period.

<Control circuit section (overall)>
FIG. 3 shows a block configuration (basic configuration including a signal processing circuit) of the control circuit unit 100 of the PDP apparatus according to the present embodiment.

  The control circuit unit 100 includes a signal processing unit (signal processing circuit) 110, an LSI (waveform generation circuit LSI) 120, and an SFM (serial flash memory) 130. The characteristic part (waveform generation circuit unit) is mounted as an LSI (waveform generation circuit LSI) 120. This LSI 120 is connected to a serial flash memory (SFM) 130 via a serial I / F. The SFM 130 is an external nonvolatile memory for the waveform generation circuit LSI120. A known signal processing unit 110 or the like is connected to the LSI 120.

  The signal processing unit 110 includes a timing control unit 111, a multi-gradation processing unit 112, and a frame memory 113. The multi-gradation processing unit 112 performs A / D conversion, halftone generation processing, SF conversion processing, and the like based on the input video signal (DATA) to generate display data (SF data). Etc. The SF data is data representing ON / OFF of each cell of each SF in the field. The timing control unit 111 generates a signal (T) for timing control of PDP drive display based on the input clock (CLK), vertical synchronization signal (VS), horizontal synchronization signal (HS), and the like. And output to each unit such as the LSI 120 and the drive circuit unit 150. For example, the signal processing unit 110 and the waveform generation circuit LSI 120 can be configured integrally.

  In the SFM 130, drive waveforms and waveform data related to the generation thereof (first waveform: S1) are stored in advance in the form of waveform decode data (D1) 51 and waveform decode address set (D2) 52. Yes. The LSI 120 includes a waveform generation circuit 23 and a first SRAM (M1) 21 and a second SRAM (M2) 22 as built-in SRAM units. The control circuit unit 100 generates a drive control signal (second waveform: S2) based on the first waveform (S1) and outputs the drive control signal to the drive circuit unit 150. The drive circuit unit 150 generates a drive waveform according to the second waveform (S2) and outputs (applies) to the electrodes (31, 32, 33) of the PDP 10. The second waveform is, for example, a signal for on / off control of a switch element (for example, an LC resonance control switch or a voltage clamp control switch) such as an FET provided in the drive circuit.

  In the SFM 130, for example, there are six control terminals (signal data input, signal data output, serial clock, hold signal, etc.). Since this is less than the conventional PFM 930, the cost can be reduced.

<Control circuit section (characteristic section)>
FIG. 4 shows a partial block configuration of a control circuit unit (control circuit) 100, which is a characteristic system of the present embodiment.

  The SFM 130 stores waveform decode data (D1) 51 and a waveform decode address set (D2) 52 (for N numbers). These data (D1, D2) are configured in advance at the stage of development / manufacturing and the like and recorded in the SFM 130. As the waveform decode address set (D2) 52, one read cycle is set as one set (decode address set), and the number of sets (N) of decode addresses used for drive control are stored in advance.

  The LSI 120 mainly includes a waveform generation circuit 23 and further includes a first SRAM (M1) 21 and a second SRAM (M2) 22 which are built-in volatile memories. The first SRAM (M1) 21 is for storing waveform decode data (D1). The second SRAM (M2) 22 is for storing the waveform decode address set (D2). Each SRAM (M1, M2) is connected to the SFM 130 via a serial I / F (serial data bus or the like).

  The first SRAM (M1) 21 stores the waveform decode data (first data: d1) read from the waveform decode data (D1) 51 in the SFM 130 and transferred as in the operation C. The second SRAM (M2) 22 stores the address data (second data: d2) selected and transferred from the waveform decode address set (D2) 52 in the SFM 130 as in the operation A. The waveform generation circuit 23 is connected to each high voltage circuit (X drive circuit 151, Y drive circuit 152, address drive circuit 153). As in operation B, the waveform generation circuit 23 performs read control of each SRAM (M1, M2).

<System operation>
In FIG. 4, the main operation in this system is as follows. Note that one read cycle is 1 SF. In this system, the LSI 120 transfers and stores each data (D1, D2) in the SFM 130 to each SRAM (M1, M2) in the LSI 120 in operations A and C, and passes through the waveform generation circuit 23 in operation B. A drive control signal (second waveform) is generated and output to the drive circuit unit 150. In operation C, the LSI 120 reads out, transfers, and stores the waveform decode data (D1) 51 in the SFM 130 to the first SRAM (M1) 21 (stored as first data (d1) in M1). In the operation A, the LSI 120 selects the waveform decode address set (D2) 52 in the SFM 130 for a predetermined unit (set), reads out the data to the second SRAM (M2) 22 and stores it (the second data in M2). (Stored as (d2)). In operation B, the waveform generation circuit 23 reads the data (d1, d2) of each SRAM (M1, M2), generates a second waveform, and outputs it to the drive circuit unit 150.

  The LSI 120 simultaneously loads the waveform decode data (D1) 51 of the SFM 130 into the first SRAM (M1) 21 before starting driving at the time of system startup, and thereafter, the refresh operation for the first SRAM (M1) 21 (SRAM compatible) I do. Further, for the waveform decode address set (D2) 52, the LSI 120 selects data (set) for a predetermined one read cycle (1SF) at the start timing of each SF of the field, and the second SRAM (M2) 22

<Timing>
The main operation timing in this system will be described with reference to FIGS.

  FIG. 5 shows a timing chart (schematic) of the operation immediately after startup in the present system (LSI 120). Data (A to C) in FIG. 5 corresponds to each operation (A to C) in FIG. From above, there are signals such as VS (vertical synchronization signal), SF switching, T1: SFM-LSI (SRAM writing), and T2: SRAM reading. VS indicates the timing of the field. SF switching indicates the timing of each SF in the field. T1 indicates the timing of writing data (D1, D2) from the SFM 130 to the LSI 120 (built-in SRAM unit 20). T2 indicates the timing of reading data (d1, d2) from the built-in SRAM unit 20 (M1, M2) in the LSI 120. Each operation subject is the LSI 120.

  At T1, immediately after the system is started, in operation C, the waveform decode data (D1) 51 is simultaneously read from the SFM 130 to the first SRAM (M1) 21 and stored as d1. Subsequently, in operation A, the waveform decode address set (D2) 52 is read from the SFM 130 to the second SRAM (M2) 22 for one read cycle (1SF) and stored as d2. On the other hand, in T2, along with the operation A, in the operation B, the waveform generation circuit 23 uses the waveform decode address set (d2) of the second SRAM (M2) 22 and the waveform decode data (1) of the first SRAM (M1) 21 ( d2) is read and input to generate and output a second waveform. More specifically, an address is input from the waveform generation circuit 23 to the A terminal of the second SRAM (M2) 22, and an address data output from the Q terminal of the second SRAM (M2) 22 is input to the A terminal of the first SRAM (M1) 21. Then, the corresponding decode data is read from the Q terminal of the first SRAM (M1) 21 and input to the waveform generation circuit 23, and a second waveform is generated and output by the input decode data.

  Similarly, FIG. 6 shows a normal operation in the present system (LSI 120). At T1, the LSI 120 reads the waveform decode address set (D2) 52 from the SFM 130 to the second SRAM (M2) 22 for one read cycle (1SF) and stores it as d2 at operation A at the beginning of each SF in the field. Subsequently, in operation C, the SFM 130 is refreshed. If transfer is completed in operation C, transfer is not performed. At T2, the LSI 120 performs the operation B in the same manner as described above along with the operation A in each SF.

  FIG. 7 shows an enlarged portion including a portion indicated by a between the operations B (data B) in FIGS. 5 and 6. At this location, after the completion of one SRAM write cycle (c1) of T1 operation A (for example, a data write cycle for the SRAM1 address), control is performed so that SRAM read of operation B of T2 is started. c2 is one SRAM read cycle (for example, a data read cycle for one SRAM address). During the WAIT period, the last waveform data of the previous SF in the waveform generation circuit 23 is output. In T1 and T2, the write cycle (c1) is configured to be shorter than the read cycle (c2) (c1 <c2). This prevents the T2 read operation from overtaking the T1 write operation.

<Waveform data>
In FIG. 8, the waveform data (D1, D2) stored in the SFM 130 of the present embodiment is shown in comparison with the waveform data (D) stored in the conventional PFM 930. In the conventional PFM 930, a drive waveform and waveform data (D) 950 relating to the generation thereof are sequentially stored for each waveform data for one read cycle (for example, 1SF). For convenience, data for one read cycle (1SF) is indicated by U (U1 to Uz). For example, U1: waveform A data, U2: waveform B data, and so on are stored. The size of the data (U) for one read cycle is such that the number of bits of the waveform (control switch) necessary for all drive control is n, and the number of clock cycles (number of steps) in one read cycle (1SF) is m. For example, (n × m) bits. The total size of the waveform data (D) 950 stored in the PFM 930 is (n × m × z) bits, where z is the number of data (U) for one read cycle.

  On the other hand, the SFM 130 is divided into a waveform decode data (D1) 51 and a waveform decode address set (D2) 52 (N number) as the drive waveform and waveform data (first waveform) related to the generation. Stored in the format. This data format is a data format in which the total capacity is reduced by compressing the conventional waveform data (D) 950 format. On the upper side, the waveform decode data (D1) 51 is stored, and subsequently, on the lower side, as the decode address set (D2) 52, the waveform decode address (AS) for each set is in order AS1: waveform A decode address data. AS2: Waveform B decode address data is stored.

  The waveform decode data (D1) 51 is obtained by analyzing and extracting a waveform group pattern (waveform combination) in a predetermined unit (every clock cycle) from a waveform necessary for full drive control. The size of the waveform decode data (D1) 51 is the number of waveform group units (in other words, patterns) in units of one clock cycle in n, where n is the number of bits of the waveform (control switch) necessary for full drive control. If (waveform unit number) is p, it is (n × p) bits. p is not m × z, but is a number close to m. This is because the total waveform data amount is compressed as the same pattern increases in all SF waveforms, and the probability that the same pattern actually exists in each main process such as Tr 71, Ta 72, Ts 73 of SF is high.

  The waveform decode address set (D2) 52 (for N numbers) is address data for referring to and reading the waveform decode data (D1) 51. Note that AS indicates a set of decode addresses (waveform decode address set) for referring to a waveform of a predetermined one read cycle. For example, AS1 is a decode address set of waveform A. As the waveform decode address set (D2) 52, the number of sets (N) corresponding to necessary waveforms (for example, waveform A to waveform Z) is stored. The size of the waveform decode address set (D2) 52 is as follows. If the number of clock cycles (number of steps) in one set (one read cycle) is m and the number of bits in the address is a, the size in one set (AS) , (M × a) bits, and (m × a × N) bits in the whole (N sets). a is the number of bits after binary conversion of p.

  The total size of the data (D1, D2) stored in the SFM 130 is (n × p) + (m × a × N) bits. This is smaller than the size ((n × m × z) bits) of the waveform data (D) 950 stored in the PFM 930. This method is effective for the above reason (the reason why p is a number close to m). The numerical example is as follows. When the number of control bits n is large, for example, when n = 32, m = 1024, p = m, a = 10, and N = z = 32, the size of the storage data of the SFM 130 is 135168 bits and the storage data of the PFM 930 Is 327680 bits, and the data compression effect is exhibited.

<PFM waveform data (D)>
The configuration of the waveform data (D, D1, D2) in FIG. 8 will be supplemented using FIGS. First, the waveform data (D) 950 stored in the PFM 930 by the PDP apparatus of the prior art, which is the basis for creating the waveform data (D1, D2) of the present embodiment, will be described with reference to FIGS. An external PFM 930 for an LSI of a conventional control circuit stores, as waveform data (D) 950, a drive waveform and waveform data relating to its generation (first waveform) for each cycle composed of a plurality of clock cycles. ing.

  FIG. 9 shows a waveform A which is an example of a conventional necessary waveform. Waveform A is one read cycle (in the case of 1SF). From the top, PA (address electrode 33 drive waveform), PX (X electrode 13 drive waveform), PY (Y electrode 32 drive waveform) drive waveforms, and then control of the control switch SW for generating these drive waveforms. , The SW generation signal (SW-SW), the PY generation SW (PY-SW), and the PX generation SW (PX-SW). One clock cycle (referred to as 1C) of the waveform is indicated by a vertical line interval. A drive waveform such as PA corresponds to the second waveform output from the drive circuit unit 150. The switch control waveform (SW control signal) is a waveform for controlling switching of each SW on (1) / off (0), and corresponds to the first waveform output by the control circuit unit 100. The control switches SW are, for example, ten SW0 to SW9 (n = 10).

  The shape of the drive waveform is an example, but for example, a PA has a plurality of address pulses 301 applied in an address period (Ta) 72. PX and PY have a reset pulse 302 applied in the reset period (Tr) 71, a scan pulse 303 applied in the address period (Ta) 72, a sustain pulse 304 applied in the sustain period (Ts) 73, and the like.

  Similarly, a conventional waveform B is shown in FIG. This waveform B has a configuration in which only the portion B1 is different from the corresponding portion (A1) of the waveform A.

  Next, FIG. 11A shows an example of waveform data (D) stored in the PFM 930 corresponding to the waveform A in FIG. Data for one read cycle (1SF) corresponding to the waveform A is sequentially stored for each 1C (for each row). In this example, the bit for each column corresponds to the control switch SW (SW0 to SW9) of the drive circuit unit 150, and data for one clock cycle (1C) of the waveform A is shown for each row. A plurality of continuous rows store data for one read cycle (cycle (step) used in 1SF). The A1 data in some rows after the second row is data corresponding to the A1 portion in FIG.

  Similarly, FIG. 11B shows an example of waveform data (D) stored in the PFM 930 corresponding to the waveform B in FIG. FIG. 11A and FIG. 11B are based on the same storage method. In this example, B1 data in some rows after the second row is data corresponding to the B1 portion of FIG. The data other than B1 data is the same as the stored data of waveform A in FIG.

  As shown in FIGS. 9 to 11 above, in the conventional system, there are waveforms (waveforms A and B) and waveform data (D) that differ only in part among the waveforms for one read cycle (1SF). However, they are newly stored in different address areas of the PFM 930 as data of different waveforms (sets). Therefore, the amount of stored data and the required capacity in the PFM 930 are large.

<SFM waveform data (D1, D2)>
With respect to the configuration of the waveform data (D) 950 and the like, waveform data (D1, D2) and the like stored in the SFM 130 in the system of the present embodiment will be described next with reference to FIGS. The SFM 130 stores waveform data (D1, D2) created based on the waveform data (D) 950.

  At the stage of development and manufacturing of this PDP device, the conventional waveform data (D) 950 (eg, waveform data of the waveforms A and B) is used for drive control with one clock cycle (1C) as one unit. Decoded data (corresponding to D1) covering all waveform data units to be generated is created. A decode address (corresponding to D2) for reading one unit (for 1C), a pattern (predetermined waveform), a waveform for one read cycle (1SF), and the like from the decode data (D1) is the waveform described above. It is created in the form defined for each unit. The waveform data (D) 950 defined for each conventional SF is replaced with a waveform decode address set (D2) 52.

  12, in this embodiment, for example, the waveform A and B corresponding to the waveform data of the conventional waveform A as shown in FIG. 9 and the waveform data of the conventional waveform B as shown in FIG. Pattern decode data (corresponding to a part of D1) is created. One row is data (1 unit) for 1C. This decoded data includes both the data of the A1 and B1 parts as being configurable. A decode address (indicated by A) is assigned corresponding to each row (one unit) in FIG. The number of bits (a) of the decode address (A) is, for example, 5 bits according to the number of waveform units (number of rows).

  Further, as shown in FIGS. 13A and 13B, waveform A decode address data (set) and waveform B decode address data (set) based on the decode data (corresponding to waveforms A and B) of FIG. Is created. One line represents the data of the decode address (A) for 1C of the waveform. A plurality of rows represent data for one read cycle (the number of cycles used in one SF), that is, one set. In the configuration of the waveform decode address data set (D2), one unit of data from the data group of FIG. 12 may be designated and arranged for each cycle (step) constituting the target waveform (SF).

  For example, the signal data of SW0 to SW9 in 1C (1 unit) is “0, 0, 0, 0, 1, 0, 0, 0, 0, 1” in the first row (address “00000”). It is. The waveform decode data (D1) 51 does not include data having the same contents (the same data is integrated as one unit). By using one or more such units (number of waveform units: p) by the decode address (arranged on the time axis), a predetermined waveform (pattern) and a waveform of one read cycle are configured. The storage data of the PFM 130 as shown in FIG. 8 is configured by configuring in the same manner as described above with the waveforms (for example, waveform A to waveform Z) necessary for all drive control.

<Second waveform (drive control signal)>
The second waveform (drive control signal) and the like will be supplemented with reference to FIGS. As an example of the drive waveform and the switch control for generating the drive waveform in FIG. 9 and the like, the case of the PX sustain pulse 304 and the X drive circuit 151 will be described. FIG. 14 shows a configuration example of the X sustain pulse generation circuit in the X drive circuit 151. FIG. 15 shows an example (part) of switch control corresponding to FIG.

  In FIG. 14, an X sustain pulse generation circuit 400 is connected to the X electrode 31 of the display cell (capacitance Cc) of the PDP 10, and generates and applies an X sustain pulse to the X electrode 31. The X sustain pulse generation circuit 400 includes a Vs (sustain voltage) clamp circuit 420 to which a power recovery circuit 410 is connected. The power recovery circuit 410 includes coils (L1, L2) connected to the capacitor Cc and switches (401, 402) for LC resonance control. The Vs clamp circuit 420 includes switches (403, 404) for Vs clamp control, and is connected to a Vs power supply (+ Vs, −Vs).

  The switches (401, 402) for LC resonance control include a first switch (SW1-1) 401 for LC resonance up (LU) control and a second switch for LC resonance down (LD) control. (SW1-2) 402. The switches (403, 404) for Vs clamp control are a first switch (SW2-1) 403 for Vs clamp up (CU) control and a second switch for Vs clamp down (CD) control. (SW2-2) 404. Each switch (401-404) is comprised including switch elements (411-414), such as FET. LU, LD, CU, and CD in FIG. 14 also indicate control inputs to the switch elements (411 to 414).

  In FIG. 15, from the LSI 920 to the X drive circuit 151, a switch control signal for controlling the X sustain pulse, for example, a control input (LU) to the switch (SW1-1) 401 for LU resonance up control, and Vs clamp-up control. The control input (CU) to the switch element (SW2-1) 403 is input. As a result, the X sustain pulse generation circuit 400 performs on / off control of the corresponding switches (401, 402) and outputs the sustain pulse 304 (rising portion). t1 and t2 indicate timing. From the off (0) state of the LU and CU, the LU is turned on (1) at timing t1. Then, the waveform rises with a curve in which the voltage gently changes due to the LC resonance action (the coil L1 and the capacitance Cc). Next, at timing t2, the CU is turned on (1). Then, due to the Vs clamping action, for example, the waveform suddenly rises from the state of the voltage Vi to Vs.

  As described above, according to the present embodiment, the control circuit unit 100 adopts the serial I / F SFM 130 and the configuration (data of the waveform decode data (D1) 51 and the waveform decode address set (D2) 52. (1) Higher clock frequency between the SFM 130 and the control circuit unit 100 (waveform generation circuit LSI120), and (2) Waveform generation by serial I / F, depending on the configuration of the built-in SRAM unit (M1, M2), etc. There are effects such as a reduction in the number of terminals of the memory control IC and the like of the circuit LSI 120, and (3) a reduction in the capacity of the SFM 130 and stored data (D1, D2).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is applicable to a flat panel display device such as a PDP device.

It is a figure which shows the whole structure of the PDP apparatus (flat panel display apparatus) which is one embodiment of this invention. It is a figure which shows the field by a subfield method, and a subfield structure (driving sequence) in the PDP apparatus of one embodiment of this invention. It is a figure which shows the whole block structure of the control circuit part in the PDP apparatus of one embodiment of this invention. It is a figure which shows the block configuration of the characteristic part of a control circuit part in the PDP apparatus of one embodiment of this invention. It is a figure which shows the operation | movement timing immediately after the system starting of the control circuit part in the PDP apparatus of one embodiment of this invention. It is a figure which shows the operation timing at the time of normal operation of the control circuit part in the PDP apparatus of one embodiment of this invention. It is a figure which shows the enlarged part of a location of the operation timing of a control circuit part in the PDP apparatus of one embodiment of this invention. It is a figure which compares the waveform data stored in SFM with the waveform data stored in the conventional PFM in the PDP apparatus of one embodiment of this invention. It is a figure which shows the example (waveform A) of the conventional waveform used as the origin which produces the waveform data in the PDP apparatus of one embodiment of this invention. It is a figure which shows the example (waveform B) of the conventional waveform used as the origin which produces the waveform data in the PDP apparatus of one embodiment of this invention. (A) is a figure which shows the example of the waveform data in the case of being stored in the conventional PFM regarding the waveform A in the PDP apparatus of one embodiment of this invention, (b) is the conventional PFM regarding the waveform B It is a figure which shows the example of the waveform data in the case of storing. It is a figure which shows the example of the decoding data produced from the waveform data of the waveform A and the waveform B in the PDP apparatus of one embodiment of this invention. In the PDP device according to the embodiment of the present invention, (a) shows an example of decode address data (set) of waveform A, and (b) shows an example of decode address data (set) of waveform B. It is. It is a figure which shows the structural example of the X sustain pulse generation circuit of the X drive circuit in the PDP apparatus of one embodiment of this invention. It is a figure which shows the switch control example of X sustain pulse (part) and the X sustain pulse generation circuit in the PDP apparatus of one embodiment of this invention. It is a figure which shows the structure of the control circuit part in the PDP apparatus of a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... PDP, 20 ... Built-in SRAM part, 21 ... 1st SRAM (M1), 22 ... 2nd SRAM (M2), 23, 93 ... Waveform generation circuit, 31 ... X electrode, 32 ... Y electrode, 33 ... Address electrode, 51 ... waveform decode data (D1), 52 ... waveform decode address set (D2), 90 ... shift register (register array), 100, 900 ... control circuit unit, 110 ... signal processing unit, 111 ... timing control unit, 112 ... many Gradation processing section 113 113 frame memory 120 920 LSI (waveform generation circuit LSI) 130 serial flash memory (SFM) 150 drive circuit 151 151 X drive circuit 152 Y drive circuit 153: Address drive circuit, 930: Parallel flash memory (PFM), 950: Waveform data (D), S1: First waveform Drive waveform and waveform data) related to its occurrence, S2 ... second waveform (drive control signal).

Claims (10)

A drive control circuit device provided in a flat panel display device, including a waveform generation circuit unit that generates a waveform for driving a panel,
In the external nonvolatile memory, the drive waveform and waveform data related to the generation thereof are stored as a first waveform for each cycle composed of a plurality of clock cycles, and stored in the nonvolatile memory. 1 is used to generate a second waveform for driving the panel,
A built-in first volatile memory that stores drive waveform decode data, which is data covering all waveform data units used for panel drive control, as first data;
A built-in second volatile memory that stores data of a decode address for reading desired data from the drive waveform decode data as second data only for a predetermined read cycle. A drive control circuit device for a flat panel display device. The drive control circuit device according to claim 1,
The drive control circuit device for a flat panel display device, wherein the nonvolatile memory is a serial flash memory connected to the first and second volatile memories through a serial interface. The drive control circuit device according to claim 1,
In the nonvolatile memory, data covering all waveform data units used for panel drive control is stored in advance as the drive waveform decode data, with one clock cycle of the first waveform as one unit. A drive control circuit device for a flat panel display device. The drive control circuit device according to claim 1,
A flat panel display device, wherein data for the number of sets used for panel drive control is stored in advance in the nonvolatile memory as data of the decode address, with one read cycle as one set. Drive control circuit device. The drive control circuit device according to claim 3,
The drive waveform decode data stored in the non-volatile memory are all stored as the first data in the first volatile memory immediately after starting the system, and thereafter the first data is stored as needed. A drive control circuit device for a flat panel display device, wherein a refresh operation is performed on first data in a volatile memory. The drive control circuit device according to claim 1,
In the nonvolatile memory, data covering all waveform data units used for panel drive control is stored in advance as the drive waveform decode data, with one clock cycle of the first waveform as one unit. ,
In the nonvolatile memory, data for the set number used for panel drive control is stored in advance as one set for one read cycle as data of the decode address,
The drive waveform decode data stored in the non-volatile memory are all stored as the first data in the first volatile memory immediately after starting the system, and thereafter the first data is stored as needed. A refresh operation is performed on the first data in the volatile memory;
One set of the decode address stored in the non-volatile memory is stored in the second volatile memory immediately after startup of the system and after the drive waveform decode data is stored. A drive control circuit device for a flat panel display device. The drive control circuit device according to claim 4,
A drive control circuit for a flat panel display device, wherein one set of the decode address stored in the nonvolatile memory is stored in the second volatile memory when the read cycle is switched apparatus. The drive control circuit device according to claim 4,
A flat panel display device comprising: a set selected for each read cycle from a plurality of sets of the decode addresses stored in the nonvolatile memory; and a set stored in the second volatile memory. Drive control circuit device. In the drive control circuit device according to any one of claims 6, 7, and 8,
In the waveform generation circuit unit that generates the second waveform based on each data stored in the first and second volatile memories,
When storing one set of the decode address in the second volatile memory, the stored decode address is read out immediately after storing one clock cycle of the decode address, and the first address is read by the decode address. A drive control circuit device for a flat panel display device, wherein the second waveform is generated with reference to the drive waveform decode data stored in a volatile memory of the flat panel display. In the drive control circuit device according to any one of claims 6, 7, and 8,
A drive control circuit device for a flat panel display device, wherein a write cycle of a circuit of the second volatile memory storing the decode address is no longer than a read cycle of the decode address for the circuit.

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