JP6079162B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device that performs gradation display by driving a liquid crystal pixel based on gradation data of a plurality of bits corresponding to each of the plurality of liquid crystal pixels.

  Conventionally, as this type of apparatus, for example, a technique described in Patent Document 1 shown below is known. In the technique described in this document, pixel data for one horizontal line is compared with the output of the counter, and the analog ramp waveform is sampled at the timing when both coincide. The analog voltage of the sampled analog ramp waveform is supplied to the corresponding liquid crystal pixel, the liquid crystal pixel is driven, and the liquid crystal pixel is displayed in gradation based on each pixel data.

JP-A-6-178238

  In the conventional technique, it is necessary to sample the analog ramp waveform by comparing the pixel data representing the number of gradations with the counter output within one horizontal scanning period. For this reason, as the number of gradations increases, the number of comparisons with the counter output increases, and the time required for one comparison becomes shorter. That is, the time for sampling the analog ramp waveform per gradation within one horizontal scanning period is shortened.

  On the other hand, the sampled analog voltage is selectively supplied to the corresponding liquid crystal pixel via the switch element and then cut off. If there are many liquid crystal pixels to which the sampled analog voltage is supplied, more switch elements are cut off after the supply. When many switch elements are cut off at the same time, the switching noise increases, and the analog noise may be disturbed by the switching noise.

  When the analog ramp waveform is disturbed and the time for sampling the analog ramp waveform per gradation is shortened, the analog ramp waveform of the next gradation must be sampled before the disturbance of the analog ramp waveform is settled. Disappear. That is, the analog ramp waveform is sampled in a state where the analog ramp waveform is disturbed.

  In such a case, an analog voltage having a voltage value different from the normal voltage value is sampled and supplied to the liquid crystal pixel. This makes it difficult to display fine gradations based on the pixel data representing the number of gradations, and the gradation display may be deteriorated.

  An object of the present invention is to provide a liquid crystal display device in which the degradation of gradation display is suppressed and the image quality of gradation display is improved.

In the present invention, a liquid crystal pixel (113) is arranged at each of a plurality of intersections where a plurality of column data lines (D) and a plurality of row scanning lines (G) intersect, and each liquid crystal pixel (113) is provided. A display unit (11) for supplying gradation drive voltage to each liquid crystal pixel to drive each liquid crystal pixel based on the corresponding multi-bit gradation data (DL) to display an image of one frame in gradation; A horizontal scanning circuit (13) that selectively outputs gradation drive voltages to a plurality of column data lines in units of one horizontal scanning period, and a plurality of row scanning lines are sequentially selected one by one in units of one horizontal scanning period. And a vertical scanning circuit (12) for outputting a row selection signal. The horizontal scanning circuit sequentially stores gradation data corresponding to each liquid crystal pixel in one horizontal scanning period, and stores the gradation data in the shift register. The grayscale data held for one horizontal scanning period H circuit (132), a counter circuit (133) that counts up the same count value as the number of gradations that can be displayed with gradation data in one horizontal scanning period, and gradation data corresponding to each liquid crystal pixel, The comparator circuit (134) that compares the gradation data held in the latch circuit with the count value of the counter circuit and outputs a coincidence pulse signal when the count value matches the gradation data, and the period of one horizontal scanning period In the liquid crystal pixel , an analog signal is selected from a plurality of identical analog signals, which are sweep signals that change in a direction in which the voltage increases from a black display voltage level to a white display voltage level, and is selected based on a coincidence pulse signal. The selected analog signal is sampled, and the voltage of the sampled analog signal is applied to the liquid crystal pixel via the column data line as a gradation drive voltage. A liquid crystal display comprising: a circuit (136); and the selection circuit is different in an analog signal selected by gradation data of j gradation and an analog signal selected by gradation data of (j + 1) gradation. Providing equipment.

  According to the liquid crystal display device of the present invention, it is possible to provide a liquid crystal display device that suppresses deterioration of gradation display and improves the image quality of gradation display.

It is a figure which shows the structure of the liquid crystal display device which concerns on 1st Embodiment of this invention. It is a figure which shows one structure of a selection circuit. It is a figure which shows one structure of an analog signal generation circuit. 3 is a timing chart of the liquid crystal display device according to the first embodiment of the present invention. It is a figure which shows the mode of the analog signal selected by j gradation and (j + 1) gradation display, and the switching noise of an analog signal.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

(First embodiment)
With reference to FIG. 1, the structure of the liquid crystal display device which concerns on 1st Embodiment of this invention is demonstrated. In FIG. 1, the liquid crystal display device includes a display unit 11, a vertical scanning circuit 12, and a horizontal scanning circuit 13.

  The display unit 11 includes a plurality of (x × y) pieces arranged in a matrix at each intersection of the x column data lines D (D1 to Dx) and the y row scanning lines G (G1 to Gy). A pixel circuit 111 is provided.

  Since each pixel circuit 111 has the same configuration, for example, the pixel circuit 111 in the first row and the first column with x = 1 and y = 1 represents the pixel circuit 111 with a pixel selection transistor 112 and a liquid crystal pixel 113. .

  The pixel selection transistor 112 is composed of, for example, a thin film transistor. The pixel selection transistor 112 has a gate terminal connected to the row scanning line G1, and is subjected to switching control based on a row selection signal supplied to the row scanning line G1. The pixel selection transistor 112 has a drain terminal connected to the column data line D1, and controls application of a grayscale driving voltage of an analog voltage supplied to the column data line D1 to the liquid crystal pixel 113.

  The liquid crystal pixel 113 is connected to the source terminal of the pixel selection transistor 112 and is applied with a gradation drive voltage supplied via the pixel selection transistor 112. The liquid crystal pixel 113 is driven based on the applied gradation driving voltage, and gradation is displayed according to the voltage value of the gradation driving voltage.

  In the display unit 11, a plurality of liquid crystal pixels 113 are driven based on a plurality of bits of gradation data corresponding to each liquid crystal pixel 113, and one frame image is displayed in gradation.

  The vertical scanning circuit 12 is connected to a plurality of row scanning lines G1 to Gy. The vertical scanning circuit 12 sequentially supplies row selection signals to the row scanning lines G in units of one horizontal scanning period, for example, sequentially from the row scanning lines G1 to Gy based on the horizontal synchronization signal HD.

  The horizontal scanning circuit 13 is connected to a plurality of column data lines D1 to Dx. The horizontal scanning circuit 13 selectively outputs a gradation driving voltage for gradation driving the liquid crystal pixels 113 corresponding to each liquid crystal pixel 113 to the column data line D in units of one horizontal scanning period. The gradation drive voltage is an analog voltage obtained by sampling the analog signal VREF.

  The horizontal scanning circuit 13 includes a shift register 131, a latch circuit 132, a counter circuit 133, a comparator circuit 134 (134-1 to 134-x), a level shifter circuit 135, and a selection circuit 136 (136-1 to 136-x).

  The shift register 131 receives the shift clock signal SCLK and n-bit gradation data DL (i (i = 1 to x)). The shift register 131 sequentially inputs n-bit gradation data corresponding to the x liquid crystal pixels 113 corresponding to one row scanning line G in units of one horizontal scanning period based on the shift clock signal SCLK.

The gradation data corresponding to each liquid crystal pixel 113 is composed of n bits. For example, when n = 12 bits, gradation display can be performed with ²ⁿ 4096 gradations per liquid crystal pixel 113. The shift register 131 sequentially inputs n-bit gradation data in parallel and shifts the data. For example, when the display unit 11 corresponds to full high-definition and x = 1920, the shift register 131 inputs n-bit gradation data corresponding to each of the 1920 liquid crystal pixels 113 in one horizontal scanning period. And shift.

  The latch circuit 132 receives the latch signal SL generated within one horizontal blanking period and the gradation data that is input and shifted to the shift register 131 during one horizontal scanning period. Based on the latch signal SL, the latch circuit 132 takes in the gradation data that is input to the shift register 131 and shifted in one horizontal scanning period. The latch circuit 132 holds n-bit gradation data corresponding to each of the acquired x liquid crystal pixels 113 for the next one horizontal scanning period.

The counter circuit 133 is composed of an n-bit counter circuit, and sequentially counts up the n-bit count value QD based on the counter clock signal CCLK. The counter clock signal CCLK is given to the counter circuit 133 from the outside of the liquid crystal display device. Thus, the counter circuit 133 outputs the ^{2 n} of the count value ^{QD (0~ (2 n -1)} ) every horizontal scanning period. Therefore, the counter circuit 133 outputs a count value having the same number of gradations as that of the n-bit gradation data and supplies the count value to the comparator circuit 134.

  The x comparator circuits 134 (134-1 to 134-x) are provided corresponding to the x liquid crystal pixels 113 corresponding to the x column data lines D, respectively. The comparator circuits 134 are all configured in the same manner, compare n-bit data for each bit, and output a coincidence pulse signal AP (i (i = 1 to x)) when all the n-bit data match. .

  For example, when the comparator circuit 134-1 corresponding to the column data line D1 of the first column is represented, the comparator circuit 134-1 includes the n-bit gradation data of the liquid crystal pixel 113 corresponding to the column data line D1, and the counter circuit 133. The n-bit count value given by is input. The comparator circuit 134-1 compares the n-bit gradation data with the n-bit count value, and outputs a coincidence pulse signal AP (1) to the level shifter circuit 135 when they match.

  The level shifter circuit 135 inputs the lower k (n> k) bit gradation data DL among the n bit gradation data latched by the latch circuit 132. The level shifter circuit 135 boosts the voltage level of the input lower-order k-bit gradation data to generate a selection signal SDL (i (i = 1 to x)). Here, the lower-order k-bit gradation data is, for example, a voltage level whose upper limit is about 3.3V. On the other hand, the selection signal SDL has a voltage level whose upper limit is about 15V, for example. The boosted selection signal SDL is applied to the corresponding selection circuit 136.

  The level shifter circuit 135 receives the coincidence pulse signal AP output from the comparator circuit 134. The level shifter circuit 135 boosts the voltage level of the input coincidence pulse signal AP. Here, the coincidence pulse signal AP has a voltage level of, for example, an upper limit of about 3.3V before boosting, and has an upper limit of, for example, a voltage level of about 15V after boosting. The boosted coincidence pulse signal AP is supplied to the corresponding selection circuit 136.

X selection circuits 136 (136-1 to 136-x) are provided corresponding to x column data lines D, respectively, and are connected to the corresponding column data lines D. Selection circuit 136 are all constructed similarly, type ^{2 k} pieces of analog signals VREF (1 to 2 ^k), selects one of the analog signal VREF of them.

2 ^k-number of the analog signal VREF is supplied from the outside of the liquid crystal display device. Thereby, it is not necessary to mount the configuration for generating the analog signal VREF in the liquid crystal display device, and the configuration of the liquid crystal display device can be reduced in size. When a configuration for generating the analog signal VREF is provided outside, the analog signal VREF having an arbitrary waveform can be easily generated and supplied to the present liquid crystal display device.

The selection circuit 136 samples the selected analog signal VREF, and applies the voltage of the sampled analog signal VREF to the corresponding column data line D as the gradation drive voltage VID (i (i = 1 to x)). For example, when the selection circuit 136-1 corresponding to the first column data line D 1 is represented, the selection circuit 136-1 receives the selection signal SDL (1) and the coincidence pulse signal AP (1) given from the level shifter circuit 135. input. The selection circuit 136-1
To enter the 2 ^k number of analog signal VREF.

Here, k is the same as the number of bits k of the selection signal SDL input to the selection circuit 136-1. The 2 ^k analog signals VREF are all composed of signals having the same waveform. The analog signal VREF is composed of a ramp waveform of a periodic sweep signal that changes in a direction in which the voltage increases from a black display voltage level to a white display voltage level in the liquid crystal pixel 113 in one horizontal scanning period.

The selection circuit 136-1 selects one analog signal VREF from 2 ^k analog signals VREF based on the selection signal SDL. The selection circuit 136-1 samples the analog signal VREF selected based on the coincidence pulse signal AP (1), and outputs the sampled analog signal VREF to the corresponding column data line D1 as the gradation drive voltage VID (1). To do.

  The selection circuit 136 is configured as shown in FIG. 2, for example. In FIG. 2, the selection circuit 136 includes a first switch circuit 21, a second switch circuit 22, and a decoder circuit 23.

The first switch circuit 21 receives 2 ^k analog signals VREF. The first switch circuit 21 selects one analog signal VREF from the 2 ^k analog signals VREF input based on the decode selection signal supplied from the decoder circuit 23. The first switch circuit 21 provides the selected analog signal VREF to the second switch circuit 22.

  The second switch circuit 22 is connected between the first switch circuit 21 and the corresponding column data line D. The second switch circuit 22 controls conduction between the first switch circuit 21 and the column data line D based on the coincidence pulse signal AP. The second switch circuit 22 brings the first switch circuit 21 and the column data line D into a conductive state only when the coincidence pulse signal AP is given.

  The second switch circuit 22 receives the analog signal VREF selected by the first switch circuit 21. The second switch circuit 22 outputs the input analog signal VREF to the column data line D only when the coincidence pulse signal AP is given. Thereby, the analog signal VREF is sampled based on the coincidence pulse signal AP, and the voltage of the sampled analog signal VREF is output to the corresponding column data line D as the gradation drive voltage VID.

  The first switch circuit 21 and the second switch circuit 22 are composed of, for example, bipolar transistors.

The decoder circuit 23 receives the k-bit selection signal SDL supplied from the level shifter circuit 135. The decoder circuit 23 decodes the k-bit selection signal SDL and generates a decode selection signal for selecting any one of the 2 ^k analog signals VREF. The decoder circuit 23 outputs the generated decode selection signal to the first switch circuit 21.

  By adopting the configuration as shown in FIG. 2, it is possible to provide a small and simple selection circuit 136.

  In the configuration of the selection circuit 136 shown in FIG. 2, two switch circuits of the first switch circuit 21 and the second switch circuit 22 are used. On the other hand, the selection circuit 136 can be configured by one switch circuit instead of these two switch circuits. In such a case, the logical product of each decode selection signal of the decoder circuit 23 and the coincidence pulse signal AP is calculated by the logical product circuit. Based on the calculation result of the logical product, the analog signal VREF is selected by one switch circuit, and the selected analog signal VREF is sampled.

  By adopting such a configuration, it is possible to provide a selection circuit 136 that is much smaller and simpler than the configuration shown in FIG.

The 2 ^k analog signals VREF are supplied to each selection circuit 136 from the outside of the liquid crystal display device, and can be generated by, for example, the analog signal generation unit 14 provided outside the liquid crystal display device. The analog signal generator 14 may be included in the liquid crystal display device.

  The analog signal generation unit 14 includes a timing generation circuit 141 and an analog signal generation circuit 142.

  The timing generation circuit 141 is supplied with a horizontal synchronizing signal HD and a vertical synchronizing signal VD synchronized with the n-bit gradation data DL. The timing generation circuit 141 generates a counter clock signal CCLK based on the horizontal synchronization signal HD and the vertical synchronization signal VD. The timing generation circuit 141 supplies the counter clock signal CCLK to the counter circuit 133 and the analog signal generation circuit 142. The timing generation circuit 141 gives the horizontal synchronization signal HD and the vertical synchronization signal VD to the vertical scanning circuit 12.

The analog signal generation circuit 142 generates 2 ^k analog signals VREF having a ramp waveform based on the counter clock signal CCLK.

  The analog signal generation circuit 142 is configured as shown in FIG. 3, for example. In FIG. 3, the analog signal generation circuit 142 includes an address generation unit 31 and an analog signal generation unit 32.

  The address generator 31 is supplied with a counter clock signal CCLK and a counter reset signal CR. The address generator 31 resets the count value with the counter reset signal CR. The count value is reset within one horizontal blanking period. The address generation unit 31 counts up the counter clock signal CCLK after the count value is reset. The address generation unit 31 sequentially provides the counted up count value to the analog signal generation unit 32 as an LUT address.

The analog signal generator 32 includes 2 ^k look-up tables (LUTs) 321 (321-1 to 321-2 ^k ) and 2 ^k DA (digital / analog) converters 322 (321-1 to 321-1). 321-2 ^k ).
All the 2 ^k LUTs 321 have the same configuration. The LUT 321 stores digital data when the analog signal VREF constituting the ramp waveform is generated based on the digital data. The LUT 321 is configured by a storage device, for example, a RAM. This RAM is composed of a dual port having two systems of address ports and data ports. Note that the LUT 321 may be constituted by a ROM when rewriting of stored digital data is not necessary.

  The LUT 321 is connected to the external bus EB. The external bus EB transfers signals exchanged with an external device such as the liquid crystal display device by an MPU (micro processor unit) (not shown) provided outside the liquid crystal display device.

The LUT 321 is given a write address and digital data common to all the LUTs 321 from the MPU via the external bus EB. Also, the LUT 321 is supplied with a write enable signal WE (1 to 2 ^k ) corresponding to each LUT 321 from the MPU via the external bus EB. The write enable signal WE causes the LUT 321 to be in a writable state, and sequentially writes and stores digital data at addresses corresponding to the write address signal.

  Since the LUT 321 is provided with individual write enable signals WE corresponding to the respective LUTs 321, writing can be performed independently of each other. Thereby, each LUT 321 can write and store arbitrary digital data at an arbitrary address.

  The LUT 321 receives the LUT address generated by the address generator 31 and reads stored digital data based on the LUT address. That is, in each LUT 321, the same digital data is read based on the LUT address common to each LUT 321.

The 2 ^k DA converters 322 all have the same configuration, and convert digital data into an analog signal VREF. The DA converter 322 is provided in one-to-one correspondence with each LUT 321. The DA converter 322 is supplied with the digital data read from the LUT 321. The DA converter 322 converts the given digital data into an analog signal VREF constituting a ramp waveform. As a result, 2 ^k DA converters 322 generate 2 ^k analog signals VREF having a ramp waveform.

  Each DA converter 322 may be connected to a buffer circuit using an operational amplifier or the like at its output so as to buffer between the DA converter 322, the selection circuit 136, and the column data line D.

  By adopting the configuration shown in FIG. 3, it is possible to provide an analog signal generation circuit 142 that can easily generate an analog signal VREF having an arbitrary waveform.

  The analog signal generator 14 having the configuration shown in FIG. 3 employs a configuration that generates the analog signal VREF based on digital data. However, the analog signal generator 14 may generate an analog signal VREF having an arbitrary waveform in one horizontal scanning period. For example, the configuration is not limited to that shown in FIG.

  Next, the operation of the liquid crystal display device of the first embodiment will be described with reference to the timing chart of FIG.

  The n-bit gradation data DL shown in FIG. 4B synchronized with the horizontal synchronizing signal HD shown in FIG. 4A is input to the shift register 131 in parallel. The n-bit gradation data DL is shifted based on the shift clock signal SCLK shown in FIG. As a result, the n-bit gradation data DL corresponding to one horizontal line, that is, x liquid crystal pixels 113 corresponding to x column data lines D are sequentially shifted and stored in the shift register 131.

  After the grayscale data DL for one horizontal line is stored in the shift register 131, the latch signal SL is given to the latch circuit 132. As a result, the gradation data DL stored in the shift register 131 is latched by the latch circuit 132 and held for one horizontal scanning period. FIG. 4D schematically shows the gradation data DL held in the latch circuit 132 during one horizontal scanning period.

  The n-bit gradation data corresponding to each liquid crystal pixel 113 held in the latch circuit 132 is supplied to the comparator circuit 134 corresponding to each column data line D. For example, n-bit gradation data DL (1) corresponding to the liquid crystal pixel 113 in the first row and first column is supplied to the comparator circuit 134-1.

On the other hand, the counter clock signal CCLK shown in FIG. 4E synchronized with the horizontal synchronizing signal HD is supplied to the counter circuit 133. As a result, the counter clock signal CCLK is counted up by the n-bit counter circuit 133, and the n-bit count value QD is sequentially output from the counter circuit 133. That is, as shown in FIG. 4 (f), a count value QD of 0 to (2 ⁿ −1) is sequentially output from the counter circuit 133. The n-bit count value QD sequentially output from the counter circuit 133 is given to each comparator circuit 134 in common.

  The n-bit counter value QD and the n-bit gradation data DL are compared by the comparator circuit 134. That is, the n-bit counter value QD and the n-bit gradation data DL corresponding to each liquid crystal pixel 113 for one horizontal line are compared during one horizontal scanning period. If they match as a result of the comparison, a coincidence pulse signal AP as shown in FIG.

  The gradation data DL corresponding to one liquid crystal pixel 113 is composed of n bits, and the counter value QD is also n bits. Thus, the count value QD can be compared with all the n-bit gradation data DL corresponding to each liquid crystal pixel 113 for one horizontal line within one cycle of the counter circuit 133, that is, one horizontal scanning period. it can. Therefore, the coincidence pulse signal AP is output corresponding to any one of the n-bit gradation data DL.

  The coincidence pulse signal AP output from the comparator circuit 134 is given to the level shifter circuit 135 and boosted. The boosted coincidence pulse signal AP is supplied to the corresponding selection circuit 136.

  On the other hand, of the n-bit gradation data DL latched by the latch circuit 132, the lower-order k (k <n) -bit gradation data DL is given to the level shifter circuit 135 to be boosted. The boosted lower k-bit gradation data DL is supplied to the corresponding selection circuit 136.

Each selection circuit 136 is commonly supplied with 2 ^k analog signals VREF having a ramp waveform as shown in FIG. 4H, for example, in synchronization with the horizontal synchronization signal HD. One of the 2 ^k analog signals VREF is selected according to the decoding result of the lower-order k-bit gradation data DL.

Here, selection of the analog signal VREF based on the gradation data DL will be described with n = 4 bits and k = 2 bits, for example. Since n = 4 bits, it is possible to display 16 gradation levels from 1 gradation to 16 gradations. Since k = 2 bits, 2 ^k = 4 analog signals VREF (1 to 4) are prepared.

  First, in one gradation of n = “0000”, the analog signal VREF (1) is selected based on k = “00” in the lower 2 bits of n. In the two gradations of n = “0001”, the analog signal VREF (2) is selected based on k = “01” in the lower 2 bits of n. In the three gradations of n = “0010”, the analog signal VREF (3) is selected based on k = “10” of the lower 2 bits of n. In the four gradations of n = “0011”, the analog signal VREF (4) is selected based on k = “11” of the lower 2 bits of n.

  Then, in the five gradations of n = “0100”, the analog signal VREF (1) is selected based on k = “00” in the lower 2 bits of n. That is, for the five gradations where n = “0100”, the same analog signal VREF (1) as that selected for one gradation where n = “0000” is selected.

  Therefore, the analog signal VREF (1) selected by the gradation data DL (1) corresponding to one gradation among the four analog signals VREF is the gradation data DL (5 corresponding to 5 gradations. ) Is selected. Similarly, the analog signal VREF (1) is also selected by gradation data DL (9) corresponding to 9 gradations and gradation data DL (13) corresponding to 13 gradations.

  Further, the analog signal VREF (2) selected by the gradation data DL (2) corresponding to 2 gradations is selected by the gradation data DL (6) corresponding to 6 gradations. Similarly, the analog signal VREF (2) is also selected by gradation data DL (10) corresponding to 10 gradations and gradation data DL (14) corresponding to 14 gradations.

  The analog signal VREF (3) selected by the gradation data DL (3) corresponding to the three gradations is selected by the gradation data DL (7) corresponding to the seven gradations. Similarly, the analog signal VREF (3) is also selected by gradation data DL (11) corresponding to 11 gradations and gradation data DL (15) corresponding to 15 gradations.

  The analog signal VREF (4) selected by the gradation data DL (4) corresponding to the 4 gradations is selected by the gradation data DL (8) corresponding to the 8 gradations. Similarly, the analog signal VREF (4) is also selected by gradation data DL (12) corresponding to 12 gradations and gradation data DL (16) corresponding to 16 gradations.

As described above, one of the four analog signals VREF (1 to 4) is selected every four gradations. That is, the analog signal VREF selected by the gradation data DL (j) corresponding to the j (j = 1 to 2 ⁿ −1) gradation and the gradation data DL (j + 1) corresponding to the (j + 1) gradation. Means that a different analog signal VREF is selected.

  The analog signal VREF selected in this way is sampled by the coincidence pulse signal AP supplied to the selection circuit 136. The sampled voltage of the analog signal VREF becomes a gradation drive voltage corresponding to the gradation data DL.

  When sampling starts when the coincidence pulse signal AP rises from the low level to the high level, the output terminal of the selection circuit 136 that outputs the gradation drive voltage to the column data line D is connected to the column data line D. As a result, a capacitive load such as the capacitance of one column data line D or the drain capacitance of the pixel selection transistor 112 connected to the column data line D is connected to the selection circuit 136. This capacity load increases as the number of row scanning lines increases.

  As described above, when the coincidence pulse signal AP rises and sampling is started, the capacitive load as described above is connected to the selection circuit 136. Thereby, the voltage of the analog signal VREF at the start of sampling slightly decreases as shown in the enlarged view of the analog signal VREF having a ramp waveform in FIG. In the enlarged view, the original waveform change of the analog signal VREF is indicated by a broken line.

  Thereafter, when the coincidence pulse signal AP falls from the high level to the low level and the sampling of the analog signal VREF is completed, the output terminal of the selection circuit 136 and the column data line D are cut off. This may cause switching noise in the analog signal VREF. When switching noise is generated, the analog signal VREF having a ramp waveform is disturbed as compared with an original waveform in which no switching noise is generated, as indicated by a broken line in the enlarged view of FIG.

  In the present invention, in order to avoid the influence of the disturbance of the analog signal VREF, the gradation data DL (j) corresponding to the j gradation and the gradation data corresponding to the (j + 1) gradation as described above. A technical feature is adopted in which an analog signal VREF different from DL (j + 1) is selected.

  That is, even if the sampling of the analog signal VREF is finished this time and switching noise is generated, the analog signal VREF in which switching noise is generated is not used for the next sampling. For the next sampling, the analog signal VREF that has been sampled before this time and that does not generate switching noise is selected.

  For example, as shown in FIG. 5, in the sampling in the grayscale data DL (j) of j grayscale, the analog signal VREF is sampled in the sampling period Tj in which no switching noise is generated. When sampling is completed, the analog signal VREF is disturbed by switching noise.

  Subsequently, in the sampling of the gradation data DL (j + 1) of the (j + 1) gradation, the analog signal VREF which is used in the gradation data DL (j) of the j gradation and is disturbed by the switching noise is not sampled. That is, an analog signal VREF that is not disturbed by switching noise of a signal different from the analog signal VREF sampled by the j-gradation gradation data DL (j) is selected and sampled. Therefore, in the sampling in the gradation data DL (j + 1) of the (j + 1) gradation, the analog signal VREF is sampled in the sampling period T (j + 1) in which no switching noise is generated.

  As described above, the gradation data DL (j) of j gradation and the gradation data DL (j + 1) of (j + 1) gradation are obtained from the analog signal VREF in the continuous sampling period Tj and the sampling period T (j + 1). Sampling. However, different grayscale data DL (j) and (j + 1) grayscale data DL (j + 1) are sampled with different analog signals VREF.

  For this reason, even if switching noise occurs at the end of sampling in the gradation data DL (j) of j gradation, the original switching noise does not occur in the gradation data DL (j + 1) of (j + 1) gradation. The waveform analog signal VREF can be sampled. As a result, the analog signal VREF can be sampled in any grayscale data DL without being affected by the switching noise accompanying the sampling operation of the analog signal VREF.

  As will be described later, by determining the number of analog signals VREF given to the selection circuit 136 according to the sampling time, the number of gradations, and the like, it is possible to select the original analog signal VREF that has not been switched. Become.

  The sampled analog signal VREF is given to the column data line D corresponding to the selection circuit 136 as the gradation drive voltage VID. All the n-bit gradation data DL for one horizontal line is compared with the n-bit count value QD within one horizontal scanning period. As a result, the grayscale driving voltage VID obtained by sampling the selected analog signal VREF is applied to all the x column data lines D within one horizontal scanning period.

  The gradation drive voltage applied to the column data line D is applied to the liquid crystal pixel 113 through the pixel selection transistor 112 connected to the row scanning line G to which the row selection signal is output from the vertical scanning circuit 12 and being in a conductive state. It is done. Thereby, the liquid crystal pixel 113 is driven by being applied with the voltage of the analog signal VREF sampled by the coincidence pulse signal AP, and gradation is displayed according to the applied voltage value.

  Such an operation in one horizontal scanning period is sequentially performed on each of the y row scanning lines G. As a result, all the liquid crystal pixels 113 of the display unit 11 are driven, and one frame image is displayed in gradation according to n-bit gradation data corresponding to each liquid crystal pixel 113.

  Here, the sampling period and switching noise of the analog signal VREF will be described by taking, for example, display in progressive full high-definition with a frame rate of 60 Hz.

  The video effective period TH in one horizontal scanning period in the full high vision is about 14.8 μsec. When the number of gradations is 12 bits and the number is 4096 gradations, the sampling period of the analog signal VREF is expressed by the following equation (1).

Image effective period TH in one horizontal scanning period / number of gradations = 14.8 / 4096 = about 3.6 nsec (1)
Here, for example, in one horizontal scanning period, the number of liquid crystal pixels 113 displaying 2048 gradations is 960, and the number of liquid crystal pixels 113 displaying 2049 gradations is 960. In such a case, when the sampling of the analog signal VREF corresponding to the liquid crystal pixel 113 displaying 2048 gradations is completed, the 960 pixel selection transistors 112 are simultaneously turned from a conductive state to a non-conductive state. At this time, as described above, switching noise may occur in the analog signal VREF.

  A general-purpose drive circuit that can drive a capacitive load generally used as an output circuit that outputs an analog signal VREF has a 3% settling time of about 20 nsec. For this reason, in the conventional case where one analog signal VREF is sampled in all gradation displays, it is necessary to provide a period of about 20 nsec from the end of the current sampling to the start of the next sampling. That is, it is necessary to provide a period of about 20 nsec between the sampling of the analog signal VREF for the current 2048 gradation display and the next 2049 gradation display. Thereby, it becomes possible to avoid the influence of the switching noise of the analog signal VREF.

  On the other hand, the sampling period of the analog signal VREF in full high vision is about 3.6 nsec as described above. That is, after the sampling of the current analog signal VREF is completed, the next sampling is started without leaving a period of about 20 nsec. Therefore, in the sampling of the analog signal VREF in the display of 2049 gradations, the analog signal VREF in a state disturbed by the switching noise generated at the end of the sampling of the analog signal VREF in the display of 2048 gradations is sampled.

  As a result, an analog voltage having a voltage value different from the normal voltage value is sampled, so that fine gradation display based on the gradation data becomes difficult, and the gradation display may be deteriorated.

  On the other hand, in the first embodiment, a plurality of analog signals VREF to be sampled are prepared, and as shown in FIG. 5, j gradation data DL (j) and (j + 1) gradation data. In DL (j + 1), different analog signals VREF are sampled. Thereby, in the sampling of the analog signal VREF in the above-described full high vision, different analog signals VREF are sampled in sampling in 2048 gradation display and sampling in 2049 gradation display.

  That is, in the sampling in the display of 2049 gradations, the analog signal VREF having an original waveform which is different from the analog signal VREF sampled in the display of 2048 gradations and does not generate switching noise can be sampled. As a result, a normal analog voltage value based on the gradation data can be given to the liquid crystal pixel 113. As a result, fine gradation display based on gradation data is possible, and the image quality of gradation display can be improved.

For example, in the above-described high-definition display, in order to select and sample the analog signal VREF in which switching noise is not generated in j gradation display and (j + 1) gradation display, at least k = 4 and 2 ^k = 8 analog signals VREF may be prepared.

DESCRIPTION OF SYMBOLS 11 ... Display part 12 ... Vertical scanning circuit 13 ... Horizontal scanning circuit 14 ... Analog signal generation part 21 ... 1st switch circuit 22 ... 2nd switch circuit 23 ... Decoder circuit 31 ... Address generation part 32 ... Analog signal generation part 111 ... Pixel Circuit 112 ... Pixel selection transistor 113 ... Liquid crystal pixel 131 ... Shift register 132 ... Latch circuit 133 ... Counter circuit 134 ... Comparator circuit 135 ... Level shifter circuit 136 ... Selection circuit 141 ... Timing generation circuit 142 ... Analog signal generation circuit 321 ... LUT
322 ... DA converter D ... Column data line G ... Row scanning line

Claims (4)

A liquid crystal pixel is disposed at each of a plurality of intersections where a plurality of column data lines and a plurality of row scanning lines intersect, and each of the liquid crystals is based on a plurality of bits of gradation data corresponding to each of the liquid crystal pixels. A display unit for supplying gradation driving voltage to the pixels to drive each of the liquid crystal pixels, and displaying an image of one frame in gradation;
A horizontal scanning circuit that selectively outputs a gradation driving voltage to the plurality of column data lines in units of one horizontal scanning period;
A vertical scanning circuit that outputs a row selection signal for sequentially selecting the plurality of row scanning lines one by one in units of one horizontal scanning period;
The horizontal scanning circuit includes:
A shift register for sequentially storing gradation data corresponding to each liquid crystal pixel in one horizontal scanning period;
A latch circuit for holding the gradation data stored in the shift register for one horizontal scanning period;
A counter circuit that counts up the same count value as the number of gradations that can be displayed by gradation data in one horizontal scanning period;
For each gradation data corresponding to each liquid crystal pixel, the gradation data held in the latch circuit is compared with the count value of the counter circuit, and when the count value and the gradation data match, a coincidence pulse signal is generated. A comparator circuit to output,
An analog signal is selected from a plurality of identical analog signals, which are sweep signals that change in a direction in which the voltage increases from a black display voltage level to a white display voltage level in the liquid crystal pixel in one horizontal scanning period, and the match A selection circuit that samples the selected analog signal based on a pulse signal and applies the voltage of the sampled analog signal to the liquid crystal pixel via the column data line as a gradation drive voltage;
The liquid crystal display device, wherein the selection circuit is configured such that the analog signal selected by gradation data of j gradation and the analog signal selected by gradation data of (j + 1) gradation are different. The liquid crystal display device according to claim 1, wherein the analog signal is given from outside the liquid crystal display device. The selection circuit includes:
A first switch circuit that selects one of the plurality of analog signals based on a decode selection signal;
A second switch circuit that samples an analog signal selected by the first switch circuit based on a coincidence pulse signal, and outputs a voltage of the sampled analog signal to the column data line as a gradation drive voltage;
A decoder circuit that decodes a part of bits of the gradation data among the plurality of bits of gradation data, generates a decode selection signal for selecting an analog signal, and applies the generated decode selection signal to the first switch circuit; The liquid crystal display device according to claim 1, further comprising a liquid crystal display device. The analog signal is generated by an analog signal generation circuit including an analog signal generation unit and an address generation unit,
The analog signal generation unit includes a plurality of look-up tables corresponding to a plurality of analog signals, and a plurality of DA converters corresponding to the plurality of look-up tables,
Each look-up table stores digital data corresponding to an analog signal when generating an analog signal from digital data by digital / analog conversion, and stores the digital data based on an address given from the address generation unit Data is read,
Each DA converter converts the digital data read from the look-up table into an analog signal to generate an analog signal to be given to the selection circuit,
The said address generation part produces | generates the address which designates the digital data read from each said look-up table, and gives it to each said look-up table, The any one of Claims 1-3 characterized by the above-mentioned. The liquid crystal display device described.

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