JPH11296130A - Driving device of display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the PDP driving device, which simultaneously displays an animation and a still picture, by employing two memories which alternatively conduct the writing and the reading of pixel data. SOLUTION: The device has two memories 41 and 42, which store pixel data, and a memory control means 7 which controls the writing and the reading in and from the memories 41 and 42. In each memory, a storage region is assigned for the plural pixels which are displayed on one screen. The means 7 displays an animation by conducting the rewriting of pixel data in the prescribed storage region among the storage regions of each memory and the pixel data for a still picture are stored in the storage region in which no rewriting is conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a driving apparatus for a display panel such as a plasma display panel (PDP).

[0002]

2. Description of the Related Art In a display device of a matrix display system such as a PDP, halftone display is performed by using a subfield method. Therefore, two field memories are used as display memories, and one field read from one memory is used. During the display based on the pixel data of, the pixel data of the next one field is written to the other memory, and after the reading of the pixel data from one memory is completed, the pixel data is read from the other memory and displayed. The operation of writing the next pixel data to one memory at the same time is repeated. That is, the display is performed by switching the memory on the reading side and the memory on the writing side for each field.

[0003]

As described above, it is necessary to switch the memory on the reading side and the memory on the writing side for each field for displaying a moving image, but this switching is stopped for displaying a still image. There is a need to. Therefore, in order to simultaneously display a moving image and a still image on a screen, a memory for multi-screen processing and its control circuit are required in addition to the above-mentioned memory, and there has been a problem that the overall price is high.

An object of the present invention is to solve the above-mentioned problems and to provide a low-cost display panel driving device capable of simultaneously displaying a moving image and a still image while suppressing an increase in memory capacity. is there.

[0005]

A display panel driving apparatus according to the present invention includes an A / D converter for sampling a video signal to obtain pixel data corresponding to each pixel, and a first memory for storing the pixel data. And a second memory, and controlling writing and reading of the first and second memories to write the pixel data to the first and second memories, and store the written pixel data in the first and second memories. And a display driving means for driving a display panel based on pixel data read from the first and second memories, the display control means comprising: Each of the memories has a plurality of storage areas allocated to a plurality of pixels displayed in one screen, and the memory control means stores the first and second memories. It is intended to rewrite the pixel data to a predetermined storage area of the plurality of storage areas of.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A display panel driving apparatus according to an embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a configuration of a plasma display device capable of color display provided with a driving device according to the present invention.

In FIG. 1, an A / D converter 1 samples an input video signal in accordance with a clock signal CK 1 of a predetermined frequency supplied from a control circuit 2, thereby obtaining pixel data D for each pixel. And sequentially supplies them to the image data processing circuit 3. The image data processing circuit 3 receives the clock signal C supplied from the control circuit 2.
It is composed of, for example, a false contour processing circuit that performs data processing according to K1. This image data processing circuit 3
Generates pseudo-intermediate display by reducing the number of bits of pixel data, and generates and outputs pixel data in which false contours are compensated.

Each of the field memories 41 and 42 has a capacity capable of storing at least one field of pixel data, and switches SW1 and SW2 connected in series.
Are respectively connected to the image data processing circuit 3 via the. Each of the field memories 41 and 42 has the same address configuration as that of the pixels of the plasma display panel 6 forming the screen. Further, the output units of the field memories 41 and 42 are alternately connected to the column electrode driver 5 via the switch SW3.

The switching of the switches SW1, SW2 and SW3 is performed by a control signal from the control circuit 2. The switch SW2 connects the field memories 41 and 42 to the image data processing circuit 3 alternately at each timing of the clock signal CK2 having a predetermined frequency supplied from the control circuit 2. On the other hand, the switch SW3 switches at each timing of the clock signal CK2 supplied from the control circuit 2, and connects the field memories 41 and 42 to the column electrode driver 5 alternately. Then, each switch SW2, SW
Switching of 3 is controlled by the control circuit 2 as follows. That is, for example, when the switch SW2 connects the image data processing circuit 3 to the field memory 41 (the switch contact is a) at the timing of the clock signal CK2, the switch SW3 connects the field memory 42 to the column electrode driver 5 (the switch contact is connected). b). When the switch SW2 connects the image data processing circuit 3 to the field memory 42 (the switch contact is b), the switch SW3 connects the field memory 41 to the column electrode driver 5 (the switch contact is a). . The switching operation of the switch SW1 will be described later.

The column electrode driver 5 separates pixel drive data for one field read from the field memories 41 and 42 into bits, and corresponds to the logical values "1" and "0" of the bits. A pixel data pulse having a voltage value is generated to generate a plasma display panel (P
DP) 6 is applied to the column electrodes. Further, various control signals such as a write enable signal and a read enable signal are input from the memory control means 7 to each of the field memories 41 and 42.

The memory control means 7 controls the addresses of the field memories 41 and 42 in accordance with the output signal from the control circuit 2 and stores the pixel data supplied from the image data processing circuit 3 in each of the field memories 41 and 42. It controls writing and reading. The operating means 8
A moving image / still image mixed mode that enables simultaneous display of moving images and still images on a screen is set and released, and a moving image / still image mixed mode designation signal is supplied to the control circuit 2.

The control circuit 2 includes a memory control means 7,
A / D converter 1, data processing circuit 3, switch SW
1, SW2, SW3, the operating means 8, and the row electrode driver 9, generate the clock signals CK1, CK2, and transmit the generated clock signal CK2 to the memory control circuit 7.
And a reset timing signal, a scan timing signal, a sustain timing signal, and an erase timing signal are generated and supplied to the row electrode driver 9. The clock signal CK2 is generated from the horizontal and vertical synchronization signals of the input video signal and corresponds to one field of pixel data.

The row electrode driver 9 responds to these various timing signals by a reset pulse for initializing a residual charge amount, a scanning pulse for writing pixel data, and a sustain pulse for maintaining a discharge light emitting state. Then, an erase pulse for stopping discharge light emission is generated and applied to the row electrode pair of the PDP 6. At this time, the scanning pulse is applied to the row electrode pairs by sequential scanning.

In the PDP 6, when a scanning pulse is applied from the row electrode driver 9 while a pixel data pulse is applied from the column electrode driver 5, charges corresponding to the applied pixel data pulse are accumulated in the PDP 6. You. At this time, for example, light emission occurs at the intersection of the column electrode to which the pixel data pulse corresponding to the logic “1” is applied and the row electrode pair to which the scanning pulse is applied. The intersection is PD
It corresponds to each pixel on the screen of P6. Thereafter, when the sustain pulse is applied from the row electrode driver 9, the above-described light emitting state is maintained for a time corresponding to the number of pulses to which the sustain pulse is applied.

Further, a switch SW1 and a switch SW3
Is connected to the arithmetic processing circuit 10. The arithmetic processing circuit 10 performs arithmetic processing such as thinning-out processing or reduction processing of a predetermined number of pixels on the number of pixels for one field input via the switch SW3, for example, and outputs the result. FIG.
This will be described with reference to FIGS.

In the "moving image display mode" for displaying an input video signal as a moving image in real time, the control circuit 2 controls one of the memories 41 and 42 according to a vertical / horizontal synchronization signal of the input video signal, that is, a clock CK2. Are alternately set to the write mode and the other to the read mode. The memory control circuit 7 generates write enable signals WR1 and WR2 and read enable signals RD1 and RD2 necessary for writing and reading of the memories 41 and 42 according to the clock CK2 from the control circuit 2, and supplies the signals to the memories. Therefore, 1 is alternately stored in the memories 41 and 42.
Pixel data for the field is written, and the written pixel data is alternately read from the memories 41 and 42. This is shown in FIG.

The moving image display mode is shown in FIGS. 2 (d), (e),
As shown in (f), the control circuit 2 causes the switch S
With W1 connected to contact "b", switch S
W2 is connected to the contact "a" and switch SW3 is connected to the contact "b" to write pixel data to the memory 41 and read pixel data from the memory 42. The length corresponds to the generation cycle of the clock signal CK2. Video display 1
Period (Ia), the memory 42 is connected by connecting the switch SW2 to the contact "b" and connecting the switch SW3 to the contact "a".
, And the "moving image display second period" (Ib) whose length corresponds to the generation cycle of the clock signal CK2 is alternately taken and repeated.

That is, in each moving image display period, an input video signal is sampled by the A / D converter 1 to become pixel data for each pixel. Next, the pixel data is sent to the image data processing circuit 3, where image processing such as false contour processing is performed.
The data is sent to the field memories 41 and 42. For example, time t
Entering the first period of the moving image display at ₀ , the field memory 41
Then, the pixel data A1 for one field is written by the write enable signal WR1 shown in FIG. 2 (g) (see FIG. 2 (h)). On the other hand, the field memory 4
2, the written pixel data is read (not shown). Then, at time t ₁ when the writing of the pixel data to the field memory 41 ends, the moving image display second
Enter the period.

In the second moving image display period, the field memory 41 reads out the read enable signal RD1 (FIG. 2).
The pixel data A1 written by (i) is read and sent to the column electrode driver 5 (see FIG. 2 (j)). On the other hand, in the field memory 42, the pixel data A2 for one field is written by the write enable signal WR2 (see FIG. 2 (k)) (see FIG. 2 (l)).

Next, at time t when the second moving image display period ends.
_{In 2} , when a moving image / still image mixed mode designation signal is input to the control circuit 2 from the operating means 8, the operation enters the “moving image / still image display mode”. In the present embodiment, the “moving image / still image display mode” includes a “still image writing mode” corresponding to a length of time corresponding to two fields of pixel data, and a subsequent “moving image / still image mixed mode”. . The still image writing mode is a mode for writing still images to be displayed in the moving image and still image mixed mode to the field memories 41 and 42.

In the present embodiment, the still image displayed in the moving image and still image mixed mode is the pixel data A2 finally read from the field memory 42 in the moving image display mode. This will be described below. At time t ₂ the still image write mode is started, the still image write mode, the switch SW2 with the switch SW1 is connected to the contact "a" connected to the contact "a", the connection switch SW3 to a contact "b" Is done. At this time, the pixel data A2 read from the field memory 42 by the read enable signal RD2 is supplied to the column electrode driver 5 and, for example, through the arithmetic circuit 10 and the switches SW1 and SW2 as shown in FIG. Write enable signal W
The data is written to the field memory 41 by R1. The method of reducing the pixel data is as follows.
Write to. That is, the arithmetic circuit 10 performs reduction processing by thinning out the number of pixels of input pixel data in the horizontal direction by 1/2, for example, and outputs the result. And
As shown in FIG. 3, the pixel data output from the arithmetic processing circuit 10 is written into a storage area SA1 corresponding to, for example, one half of the storage area of the memory 41 by the address control of the memory control circuit 7. On the other hand, the remaining storage area SA2 of the memory 41 remains without being rewritten.

[0022] At time t ₃ when the writing of pixel data A2 to the memory 41 is completed, the connection switch SW2 is a contact "b" while maintaining the state where the switch SW1 is connected to the contact "a", the switch SW3 is contact The pixel data connected to “a” and read from the field memory 41 is supplied to the column electrode driver 5. Since the address configuration of the memory 41 corresponds to the pixel configuration of the PDP 6, an image corresponding to the pixel data thinned out by half in the right half of the screen is displayed on the PDP 6 as a still image.

On the other hand, the pixel data read from the field memory 41 is written into the field memory 42 via the arithmetic circuit 10 as shown in FIG.
Copied by R2. In this way, pixel data displayed as a still image is written to the memories 41 and 42, respectively.

Next, at time t ₄ when the writing of pixel data into the memory 42 is completed, becomes movies and photos mixed mode, the switch SW1 is switched to the contact "b" by the control circuit 2. The control circuit 2 controls the memories 41 and 4 according to the clock CK2 in the same manner as in the moving image display mode.
One in write mode and the other in read mode,
Set alternately. Therefore, the input video signal is stored in the memory 4
The pixel data and the still image pixel data written alternately in the moving image storage areas 1 and 42 are written in the memory 4.
The data are read alternately from the data 1, 42. That is, FIG.
As shown in (d), (e) and (f), the switch SW2 is connected to the contact “a” and the switch SW3 is connected to the contact “b” to write pixel data to the memory 41 and to store the pixel data from the memory 42. A "mixed display first period" (Ma) whose length corresponds to the generation cycle of the clock signal CK2 for reading data, the switch SW2 is connected to the contact "b", and the switch SW3 is connected to the contact "a". A "mixed display second period" (Mb) whose length corresponds to the generation cycle of the clock signal CK2, in which pixel data is written to the memory 42 and pixel data is read from the memory 41, is taken alternately. repeat. Further, in the moving image / still image mixed mode, in each of the field memories 41 and 42, the writing of the pixel data to the storage area SA1 in which the still image is written is not performed.

That is, in each mixed display period, the input video signal is sent to the frame memories 41 and 42, and is written into only the storage areas SA2 and SA2 of the memories 41 and 42 by the address control of the memory control circuit 7. It is. That is, for example, the mixed display first period is entered at time t ₄ , and the field memory 41 outputs the pixel data C 1 for one field by the write enable signal WR 1.
Is written with the number of pixels in the horizontal direction reduced by the memory control circuit in accordance with the storage area SA2 (see FIG. 3). On the other hand, the written pixel data is read from the field memory 42. At time t ₅ the writing of pixel data in the field memory 41 is completed, into the mixed display the second period.

In the mixed display second period, the read enable signal RD1 (FIG.
The pixel data C1 and the still image A2 written by (i) are read out and sent to the column electrode driver 5. On the other hand, in the field memory 42, the pixel data C2 for one field is written by the memory control circuit 7 with the number of pixels in the horizontal direction reduced according to the storage area SA2 by the write enable signal WR2 (see FIG. 2 (k)). .

As described above, the pixel data to be displayed as a still image is written to both the memories 41 and 42, and the writing of the pixel data thereafter is limited to a predetermined area of the memory, and the written still image pixel data is held. As a result, the screen of the PDP 6 corresponding to such a storage area of the memory becomes a still image, and the other portions can be a moving image corresponding to pixel data that is sequentially input.

Next, a second embodiment of the driving device and its operation will be described with reference to FIGS. The driving device shown in FIG. 4 has a configuration similar to that of the driving device shown in FIG. 1, but has no arithmetic circuit between the switches SW1 and SW3, and pixel data read from the memories 41 and 42 is Direct memory 4 via switches SW1 and SW2
1, 42. The components denoted by the same reference numerals as those in FIG. 1 are the same as those in FIG.

Next, the operation of the driving device of FIG. 4 will be described with reference to FIG. The operation of the driving device in the moving image display mode is the same as that of the driving device shown in FIG. That is, in the “moving image display mode” in which the input video signal is displayed as a moving image in real time, the control circuit 2 sets one of the memories 41 and 42 to the writing mode in accordance with the vertical / horizontal synchronization signal of the input video signal. The other is set to the read mode alternately. The memory control circuit 7 controls the memories 41 and 42 according to the clock CK2 from the control circuit 2.
Write enable signals WR1, WR2 and read enable signals RD1, R
D2 is generated and supplied to each memory. Therefore, memory 4
Pixel data for one field is alternately written to the memory cells 1 and 42, and the written pixel data is alternately read from the memories 41 and 42.

The moving image display modes are shown in FIGS. 5 (d), (e),
As shown in (f), the control circuit 2 causes the switch S
With W1 connected to contact "b", switch S
W2 is connected to the contact "a" and switch SW3 is connected to the contact "b" to write pixel data to the memory 41 and read pixel data from the memory 42. The length corresponds to the generation cycle of the clock signal CK2. Video display 1
Period (Ia), the memory 42 is connected by connecting the switch SW2 to the contact "b" and connecting the switch SW3 to the contact "a".
, And the "moving image display second period" (Ib) whose length corresponds to the generation cycle of the clock signal CK2 is alternately taken and repeated.

That is, in each moving image display period, the input video signal is sampled by the A / D converter 1 to become pixel data for each pixel. Next, the pixel data is sent to the image data processing circuit 3, where image processing such as false contour processing is performed.
The data is sent to the field memories 41 and 42. For example, time t
Entering the first period of the moving image display at ₀ , the field memory 41
Then, writing of the pixel data A1 for one field is performed by the write enable signal WR1 shown in FIG. 5 (g) (see FIG. 5 (h)). On the other hand, the field memory 42
, The written pixel data is read out (not shown). Then, at time t ₁ when the writing of the pixel data into the field memory 41 ends, the moving image display second period starts.

In the moving image display second period, the field memory 41 reads out the read enable signal RD1 (FIG. 5).
The pixel data A1 written in (i) is read out and sent to the column electrode driver 5 (see FIG. 5 (j)). On the other hand, in the field memory 42, the pixel data A2 for one field is written by the write enable signal WR2 (see FIG. 5 (k)) (see FIG. 5 (l)).

Next, at time t when the second moving image display period ends.
_{In 2} , when a moving image / still image mixed mode designation signal is input to the control circuit 2 from the operating means 8, the operation enters the “moving image / still image display mode”. In the present embodiment, the “moving image / still image display mode” includes a “still image writing mode” corresponding to a length of time corresponding to one field of pixel data, and a subsequent “moving image / still image mixed mode”. . The still image writing mode is a mode for leaving still images to be displayed in the moving images and the still image mixed mode in the memories 41 and 42.

In this embodiment, the still image displayed in the moving image and still image mixed mode is a part of the pixel data A2 finally read from the field memory 42 in the moving image display mode. This will be described below. At time t ₂ the still image write mode is started, the still image write mode, the switch SW2 is connected to the contact "a" with the switch SW1 is connected to the contact "a", the switch S
W3 is connected to contact "b". At this time, the pixel data A2 read from the field memory 42 by the read enable signal RD2 is supplied to the column electrode driver 5, and as shown in FIG.
The data is written to the field memory 41 by the write enable signal WR1 via W2. The pixel data supplied from the memory 42 to the memory 41 is stored under the address control of the memory control circuit 7 and corresponds to, for example, half the storage area of the memory 41 corresponding to the address of the pixel data to be displayed as a still image. Only the pixel data A2 having the address corresponding to the area SA1 is written to the storage area SA1 of the memory 41 (see FIG. 6A). on the other hand,
The remaining storage area SA2 of the memory 41 is a storage area for displaying a moving image.

[0035] At time t ₃ when the writing of pixel data A2 to the memory 41 is completed, becomes movies and photos mixed mode, the switch SW1 is contact with the control circuit 2 "b"
Can be switched to The control circuit 2 alternately sets one of the memories 41 and 42 to the write mode and the other to the read mode according to the vertical / horizontal synchronization signal of the input video signal, as in the moving image display mode. Therefore, the input video signal is alternately written to the memories 41 and 42, and the written pixel data is alternately read from the memories 41 and 42.

At this time, as shown in FIGS. 5 (d), (e) and (f), the switch SW2 is connected to the contact "b" and the switch SW3 is connected to the contact "a" to connect the pixel to the memory 42. A "mixed display first period" (Ma) whose length corresponds to the generation cycle of the clock signal CK2, in which data is written and pixel data is read from the memory 41;
2 is connected to the contact "a" and the switch SW3 is connected to the contact "b" to write pixel data to the memory 41 and read pixel data from the memory 42. The length corresponds to the generation cycle of the clock signal CK2. And “Mixed display second period” (Mb) are alternately taken and repeated.

In each mixed display period, the input video signal is sent to the frame memories 41 and 42, and is controlled by the address of the memory control circuit 7, as shown in FIG.
The data is written only in the moving image storage areas SA2 and SA2 of the memories 41 and 42. In other words, enters the mixed display first period at time t _3, the field memory 42, the write enable signal WR2, the number of pixels the pixel data B2 of one field with respect to the horizontal direction of the video storage area SA2 by the memory control circuit The value is reduced in accordance with the address and written only in the moving image storage area SA2 (FIG. 6B)
reference). On the other hand, in the storage area SA1 of the memory 42, the pixel data is not rewritten. In this case, the pixel data in the storage area SA1 of the memory 42 that has not been rewritten matches the pixel data previously written in the storage area SA1 of the memory 41.

Next, at time t ₄ when the writing of pixel data in the field memory 42 is completed, mixed display second
Enter the period. In the mixed display second period, the read enable signal RD2 (see FIG.
(M) and the still image A2 not rewritten are read out and sent to the column electrode driver 5 (see FIG. 5 (n)). On the other hand, in the field memory 41, the write enable signal WR1
The pixel data C1 for one field is reduced in the number of pixels in the horizontal direction by (see FIG. 5 (g)) and written into the moving image storage area SA2 by the memory control circuit (see FIG. 6 (h)).

In this way, the pixel data to be displayed as a still image is written to both memories 41 and 42, and the writing of the pixel data thereafter is limited to a predetermined area of the memory, and the written still image pixel data is held. By doing so, as shown in FIG. 6D, the screen of the PDP corresponding to such a storage area of the memory becomes a still image, and the other part of the PDP becomes a moving image corresponding to the sequentially input pixel data. it can.

Next, another embodiment of the operation of the driving device shown in FIG. 4 will be described with reference to FIGS. The operation of the driving device in the moving image display mode is the same as the operation display mode of the operation shown in FIG. That is, in the “moving image display mode” in which the input video signal is displayed as a moving image in real time, the control circuit 2 sets one of the memories 41 and 42 to the writing mode in accordance with the vertical / horizontal synchronization signal of the input video signal. The other is set to the read mode alternately. The memory control circuit 7 generates write enable signals WR1 and WR2 required for writing and reading of the memories 41 and 42 according to the clock CK2 from the control circuit 2.
And the read enable signals RD1 and RD2 are generated and supplied to the respective memories. Therefore, pixel data for one field is alternately written to the memories 41 and 42, and the written pixel data is alternately read from the memories 41 and 42.

Next, at time t when the second moving image display period ends.
_{In 2} , when a moving image / still image mixed mode designation signal is input to the control circuit 2 from the operating means 8, the operation enters the “moving image / still image display mode”. In video / still image display mode,
As shown in FIGS. 7D, 7E and 7F, the switch SW
2 is connected to the contact "a" and the switch SW3 is connected to the contact "b" to write pixel data to the memory 41 and read pixel data from the memory 42. The length corresponds to the generation cycle of the clock signal CK2. And the switch SW2 is connected to the contact "b" and the switch SW3 is connected to the contact "a" to write pixel data to the memory 42 and read pixel data from the memory 41. The clock signal CK
"Mixed display second period" (Mb) corresponding to the occurrence cycle of No. 2 is alternately taken and repeated.

[0042] At time t ₂ the mixed display first period is started, the switch SW2 is connected to the contact "a", the switch SW3 is connected to the contact "b". At this time, the input video signal B1 for one field is transmitted to the memory control circuit 7
By the address control, as shown in FIG. 8A, for example, the number of pixel data in the horizontal direction is reduced and written only in the moving image storage area SA2 of the memory 41 corresponding to the address of the screen displaying the moving image. Accordingly, the storage area SA1 excluding the moving image storage area SA2 that has not been rewritten.
Is maintained without being rewritten as still image pixel data.

At time t ₃ when the writing of the pixel data B 1 to the memory 41 ends, the second mixed display period is entered.
As shown in FIG. 8B, the input video signal B2 for one field is subjected to the address control of the memory control circuit 7, and only the moving image storage area SA2 of the memory 42 corresponding to the address of the screen displaying the moving image as shown in FIG. Is written, for example, with the number of pixel data in the horizontal direction being reduced. Therefore, a part of the pixel data A2 written in the storage area SA1 excluding the moving image storage area SA2 that has not been rewritten,
The pixel data for the still image is maintained without being rewritten. On the other hand, the written pixel data is read from the memory 41 and displayed on the PDP 6.

As shown in FIG. 8C, the input video signal is sent to the frame memories 41 and 42 in each of the mixed display periods, and is controlled by the memory control circuit 7 in accordance with the address control. Only the moving image storage areas SA2 and SA2 of 41 and 42 are written in a limited manner and displayed as moving images. At the same time, the pixel data that has not been rewritten in each memory is displayed as a still image on the PDP 6 by multiple readings.

In each of the above embodiments, the moving image is displayed in a half area of the screen and the still image is displayed in the remaining area. Can take any size. Further, the driving method of the driving device can be applied to a channel guide function of displaying a plurality of images on one screen and displaying one of the images as a moving image for a certain period.

Further, the driving device may be a PDP driving device that divides one field into a plurality of subfields and displays one screen.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a PDP driving device according to the present invention.

FIG. 2 is a diagram for explaining the operation of the driving device of the PDP of FIG. 1;

FIG. 3 is a diagram illustrating a state of a memory of the driving device in FIG. 1;

FIG. 4 is a configuration diagram showing a second embodiment of a PDP driving device according to the present invention.

FIG. 5 is a diagram illustrating the operation of the driving device of the PDP of FIG. 4;

FIG. 6 is a diagram illustrating a state of a memory of the driving device in FIG. 4;

FIG. 7 is a diagram illustrating a further operation of the PDP driving device of FIG. 4;

FIG. 8 is a diagram illustrating a state of a memory when the driving device of FIG. 4 is operated as shown in FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 5, 9 Display drive means 6 Display panel 7 Memory control means 41, 42 1st and 2nd memory

Claims (5)

[Claims] An A / D converter for sampling a video signal to obtain pixel data corresponding to each pixel; a first and a second memory for storing the pixel data; and a first and a second memory. A memory control unit that controls writing and reading to write the pixel data to the first and second memories and alternately reads the written pixel data from the first and second memories; And a display driving means for driving the display panel based on pixel data read from the two memories, wherein each of the first and second memories includes a plurality of the plurality of memories displayed on one screen. A plurality of storage areas assigned to each of the pixels, wherein the memory control unit stores the pixels in a predetermined storage area of the plurality of storage areas of the first and second memories; The display panel drive, characterized in that rewriting the over data. 2. The method according to claim 1, wherein said memory control means rewrites pixel data only in one of a plurality of storage areas of each of said first and second memories. The driving device of the display panel according to the above. 3. The display according to claim 1, wherein said memory control means sequentially rewrites pixel data in each of a plurality of storage areas of each of said first and second memories. Panel drive. 4. The memory control means stores pixel data read from a second storage area other than a predetermined storage area of one of the first and second memories in a corresponding storage of the other memory. 2. The display panel driving apparatus according to claim 1, wherein the pixel data corresponding to the second memory area of the one memory and the corresponding memory area of the other memory is not rewritten after writing to the area. 5. The display panel driving device according to claim 1, wherein the display panel is a plasma display panel that divides one field into a plurality of subfields and performs a gray scale display.