JP2008306231A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a PLL circuit achieving high-speed responsivity and stable operation. <P>SOLUTION: A low-amplitude signal of a phase comparison circuit operated with a low supply voltage VddL is inputted to a first differential circuit having an N-channel MOSFET input configuration and a second one having a P-channel MOSFET input configuration that are operated with a high supply voltage each. As the loads of the first and second differential circuits, a MOSFET in diode connection is in parallel with the MOSFET in cross couple connection. A P-channel MOSFET, where a prescribed bias voltage is supplied to the gate, is connected to an N-channel MOSFET in series. The source of the P-channel MOSFET is controlled by the output signal of the first differential circuit. The source of the N-channel MOSFET is controlled by the output signal of the second differential circuit. An up current or a down current is formed from the drain of the P- and N-channel MOSFETs. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and relates to a technique that is effective when used for a semiconductor device having a PLL (phase locked loop) circuit.

FIG. 10 shows a block diagram of the PLL studied prior to the present invention. The PLL includes a phase comparison circuit PFD, a charge pump circuit CP, a low-pass filter LPF, a voltage control oscillation circuit VCO (voltage-current conversion circuit VIC + current control oscillation circuit CCO), and a frequency divider circuit DiV-1. In Non-Patent Document 1, the external supply is one power supply, but the internal regulator generates a low voltage VddL, and the internal operation has a configuration of a two power supply PLL composed of VddH and VddL. A level conversion circuit LS is inserted between the phase comparison circuit PFD operating at the low power supply voltage VddL and the charge pump circuit CP of the high power supply voltage VddH. The up signal UP and the down signal DN that have undergone level conversion drive the switch of the charge pump circuit CP. There are various configurations of the charge pump CP as shown in Non-Patent Document 2.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005 `` A 0.16-2.55-GHz CMOS ACTIVE CLOCK DESKEWING PLL USING ANALOG PHASE INTERPOLATION '' IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 11, NOVEMVER 1996 `` A 320MHz, 1.5mW @ 1.35V CMOS PLL for Microprocessor Clock Generation ''

  In the PLL circuit of FIG. 10, the phase comparison circuit PFD outputs an up signal UP and a down signal DN having a pulse width corresponding to the phase difference between the reference clock Fref and the feedback clock FB. The level conversion circuit LS that performs level conversion is required to operate at high speed for high response. However, in order to realize a narrow pulse operation corresponding to the phase difference with the amplitude of the high power supply voltage VddH, the power supply current spike in the level shift LS circuit becomes large and the charge pump circuit CP sharing the same power supply line VddH, current-voltage conversion It adversely affects analog circuits such as the circuit VIC, such as increased jitter and reference clock spurious deterioration. Further, since the switch MOSFET of the charge pump circuit CP is driven with the amplitude of the high power supply voltage VddH and a high slew rate waveform, an unnecessary charge injection amount including feedthrough in the switch MOSFET becomes large, and the charge pump circuit CP circuit. Increase the output noise.

  An object of the present invention is to provide a semiconductor device including a PLL circuit that realizes high-speed response and stable operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One example of the semiconductor device disclosed in the present application is as follows. The low-amplitude signal of the phase comparison circuit operating at the low power supply voltage VddL is input to the first differential circuit having the N-channel MOSFET input configuration and the second differential circuit having the P-channel MOSFET input configuration operating at the high power supply voltage. A diode-connected MOSFET and a cross-coupled MOSFET are configured in parallel as load circuits of the first and second differential circuits. A P-channel MOSFET and an N-channel MOSFET whose gates are supplied with a predetermined bias voltage are connected in series, the source of the P-channel MOSFET is controlled by the output signal of the first differential circuit, and the source of the N-channel MOSFET is the above-mentioned Controlled by the output signal of the second differential circuit, an up current or a down current is formed from the drains of the P-channel MOSFET and the N-channel MOSFET.

  The low-amplitude signal is input to the differential circuit of the N-channel MOSFET input and the P-channel MOSFET input respectively as the phase comparison output signal, and the MOSFET that forms the up current or the down current is directly controlled by the output signal. Stabilization of operation can be realized.

  FIG. 1 shows a circuit diagram of an embodiment of a charge pump circuit according to the present invention. The up signal UP and its inverted signal UPB formed by the phase comparison circuit are supplied to the gates of the N-channel type differential MOSFETs MN1 and MN2. A current source IB1 is provided between the sources of the differential MOSFETs MN1 and MN2 and the circuit ground potential (VSS: 0 V). The following load circuit is provided between the drains of the differential MOSFETs MN1 and MN2 and the high power supply voltage VddH. The load circuit includes diode-type P-channel MOSFETs MP1 and MP4 provided at the drains of the differential MOSFETs MN1 and MN2, respectively, and P-channel MOSFETs MP2 and MP3 parallel to the MOSFETs MP1 and MP4, respectively. The MOSFETs MP2 and MP3 are in a latch form with their gates and drains cross-connected.

  The P-channel MOSFET MP5 forms an up current Iup corresponding to the up signals UP and UPB of the phase comparison circuit. The source of the MOSFET MP5 is connected to the drain of the differential MOSFET MN2. A bias voltage VBP is supplied to the gate of the MOSFET MP5. A stabilization capacitor C1 of the bias voltage VBP is provided between the gate of the MOSFET MP5 and the high power supply voltage VddH.

  The Dan signal DN and its inverted signal DNB formed by the phase comparison circuit are supplied to the gates of P-channel type differential MOSFETs MP7 and MP6. A current source IB2 is provided between the sources of the differential MOSFETs MP6 and MP7 and the high power supply voltage VddH. The following load circuit is provided between the drains of the differential MOSFETs MP6 and MP7 and the circuit ground potential (VSS: 0 V). The load circuit includes diode-shaped N-channel MOSFETs MN3 and MN6 provided at the drains of the differential MOSFETs MP6 and MP7, respectively, and N-channel MOSFETs MN4 and MN5 arranged in parallel with the MOSFETs MN3 and MN6, respectively. The MOSFETs MN4 and MN5 are latched with their gates and drains cross-connected.

  The N-channel MOSFET MN7 forms a down current Idn corresponding to the down signals DN and DNB of the phase comparison circuit. The source of the MOSFET MN7 is connected to the drain of the differential MOSFET MP7. A bias voltage VBN is supplied to the gate of the MOSFET MN7. A stabilizing capacitor C2 of the bias voltage VBN is provided between the gate of the MOSFET MN7 and the ground potential VSS of the circuit.

  The circuit operation of the charge pump circuit of this embodiment is as follows. When the up signal UP is at the low level and the inverted signal UPB is at the high level (VddL), the N-channel MOSFET MN1 is in the off state, the N-channel MOSFET MN2 is in the on state, and the current of the current source IB1 flows toward the MOSFET MN2. The current flowing through the MOSFET MN2 also flows through the diode-type MOSFET MP4 constituting the load circuit to generate the voltage Vgsp4. For this reason, the node (a) becomes a potential which is lowered from the high power supply voltage VddH by the source-gate voltage Vgsp4 of the MOSFET MP4. The voltage Vgsp4 at the node (a) simultaneously turns on the cross-coupled P-channel MOSFET MP2. Since the differential MOSFET MN1 is off and no current flows, the drain node charges of the P-channel MOSFETs MP1 and MP2 are discharged to the high power supply voltage VddH. When the potential of the node (a), which is the source voltage of the MOSFET MP5, decreases from VddH by the voltage Vgsp4, the gate-source voltage of the P-channel MOSFET MP5 decreases (or reverse bias), and the P-channel MOSFET MP5 is turned off. Thus, the up current Iup is made zero.

  When the up signal UP is at a high level (VddL) and the inverted signal UPB is switched to a low level, the N-channel MOSFET MN1 is turned on and the N-channel MOSFET MN2 is turned off. The current of the current source IB1 flows to the MOSFETMN1 side. The current flowing through the MOSFET MN1 also flows through the diode-type MOSFET MP1 constituting the load circuit to generate the voltage Vgsp1. For this reason, the drain potential of the MOSFET MP1 decreases from the high power supply voltage VddH up to that time to VddH−Vgsp1. Due to this voltage drop, the P-channel MOSFET MP3 is turned on, and the node (a) is changed from the previous VddH-Vgsp4 to the high power supply voltage VddH. The P-channel MOSFET MP5 is turned on when the source potential rises to the high power supply voltage VddH, and an up current Iup determined by the bias voltage VBP supplied to the gate flows, so that the control formed by the charge pump circuit CP (not shown). Increase the voltage. In this way, during the period when the up signal UP formed by the phase comparison circuit PFD is at the high level (VddL), the charge pump operation is performed in which the up current Iup is supplied to the low pass filter LPF.

  When the down signal DN is at a low level and the inverted signal DNB is at a high level (VddL), the P-channel MOSFET MP6 is off, the P-channel MOSFET MP7 is on, and the current of the current source IB2 flows to the MOSFET MP7 side. The current flowing through the MOSFET MP7 also flows through the diode-type MOSFET MN6 constituting the load circuit to generate the voltage Vgsn3. For this reason, the node (b) becomes a potential that is increased by the voltage Vgsn6 between the source and gate of the MOSFET MN6 from the ground potential VSS of the circuit. The voltage Vgsn6 of the node (b) simultaneously turns on the cross-coupled N-channel MOSFET MN4. Since the differential MOSFET MP6 is off and no current flows, the drain node charges of the N-channel MOSFETs MN3 and MN4 are discharged to the ground potential VSS of the circuit. When the potential of the node (b), which is the source voltage of the MOSFET MN7, increases by the voltage Vgsn6, the gate-source voltage of the N-channel MOSFET MN7 decreases (or reverse bias), and the N-channel MOSFET MN7 is turned off. The down current Idn is set to zero.

  When the down signal DN is at a high level (VddL) and the inverted signal DNB is switched to a low level, the P-channel MOSFET NP6 is turned on and the P-channel MOSFET MP7 is turned off. The current of the current source IB2 flows to the MOSFET MP6 side. The current flowing through the MOSFET MP6 also flows through the diode-type MOSFET MN3 constituting the load circuit to generate the voltage Vgsn3. For this reason, the drain potential of the MOSFET MN3 rises from the ground potential VSS so far to Vgsn3. This voltage rise turns on the N-channel MOSFET MN5 and changes the node (b) from the previous Vgsn6 to the ground potential VSS (0 V). The N-channel MOSFET MN7 is turned on when the source potential is lowered to the ground potential VSS, and the down current Idn determined by the bias voltage VBN supplied to the gate flows, so that the control voltage formed by the charge pump circuit CP (not shown). Reduce. In this way, a charge pump operation is performed in which the down current Idn is supplied to the low-pass filter LPF while the down signal DP formed by the phase comparison circuit PFD is at a high level (VddL).

  The amplitudes of the output nodes (a) and (b) of the differential circuit are the difference voltages Vgsp4 and Vgsn6 generated by the tail currents formed by the current sources IB1 and IB2, respectively, and are much smaller than the high power supply voltage VddH. Since it is about the value obtained by adding the overdrive voltage to the threshold value Vth of the MOSFET, it can be easily designed to be lower than the low power supply voltage VddL. Since the output amplitude can be limited by the diode-connected MOS load circuit, a thin film MOSFET constituting the phase comparison circuit PFD can be used as the MOSFET used, and the differential circuit load circuits are all thin film MOSFETs MP1 to MP4 and MN3. By substituting for ~ MN6, the output nodes (a) and (b) can be transitioned at high speed with the high-speed performance of the fine process device. Conventionally, thick film MOSFETs are used for the differential input MOSFETs MN1, MN2 and MP6, MP7 to which a high voltage is applied to the drain and the charge pump output drive MOSFETs MP5, MN7. That is, although the charge pump circuit CP operates at the high power supply voltage VddH, the circuit configuration of FIG. 1 can use a low breakdown voltage thin film gate MOSFET, and the charge pump output MOSFETs MP5 and MN7. Can be driven directly.

  In FIG. 1, elements having a square gate electrode, such as MOSFETs MN1, MN2, MP6, MP7, etc., indicate that the gate insulating film is thick, and the gate electrodes, such as MOSFETs MP1, MP2, MN3, MN4, etc. The element indicated by the straight line indicates that the gate insulating film is thin. The P-channel MOSFET is indicated so that it can be distinguished from the N-channel MOSFET by adding a circle to the gate. Such an expression method is the same in the circuit diagrams shown below.

  FIG. 2 shows a circuit diagram of an embodiment of a bias circuit used in the charge pump circuit. The current formed by the current source IB1 is passed through the diode-shaped P-channel MOSFET MP1a. This MOSFET MP1a and a P-channel MOSFET MP3a in the form of a current mirror are provided. This MOSFET MP3a and a diode-type P-channel MOSFET MP5a are connected in series, and a current source Iup is provided between the drain thereof and the ground potential VSS of the circuit. The gate and drain voltages of the MOSFET MP5a are supplied as the bias voltage VBP to the gate of the P-channel MOSFET MP5.

  The current formed by the current source IB2 is passed through the diode-shaped N-channel MOSFET MN3a. This MOSFET MN3a and an N-channel MOSFET MN5a in the form of a current mirror are provided. This MOSFET MN5a and a diode-shaped N-channel MOSFET MN7a are connected in series, and a current source Idn is provided between the drain thereof and the high power supply voltage VddH. The gate and drain voltages of the MOSFET MN7a are supplied as the bias voltage VBN to the gate of the N-channel MOSFET MP7.

  In this embodiment, in order to accurately transfer the bias voltage sources Iup and Idn to the charge pump unit, a differential circuit replica configuration is adopted. That is, the current sources IB1 and IB2 are made the same as the bias current (tail current) of the differential circuit as described above, MP5 = MP5a and MN7 = MN7a, MP1 = MP1a, MP3 = MP3a, MN3 = MN3a, MP5 = MN5a Same size as

  FIG. 3 is a timing chart for explaining an example of the operation of the charge pump circuit. When the feedback clock FB is delayed with respect to the reference clock Fref, the up signal UP is set to the high level for a period corresponding to the phase difference. In the charge pump circuit, the node (a) is set to the high power supply voltage VddH while the up signal UP is at the high level, and the up current Iup flows as described above. On the contrary, when the feedback clock FB advances with respect to the reference clock Fref, the down signal DN is set to the high level for a period corresponding to the phase difference. In the charge pump circuit, the node (b) is set to the ground potential VSS (0 V) while the down signal DN is at the high level, and the down current Idn flows as described above.

  In the phase comparison circuit of this embodiment, the UP signal and DN signal having the minimum pulse width are output during the phase comparison operation. By always outputting such a signal having a narrow pulse width, a dead zone in the charge pump circuit, that is, instability of the output voltage when both the output MOSFETs MP5 and MN7 are turned off is prevented. For example, if the currents corresponding to the minimum pulse width are ΔIup and ΔIdn, the actual up current is Iup−ΔIdn and the actual down current Idn−ΔIup. Thereby, even when the clock Fref and the feedback clock FB completely coincide with each other, through currents such as ΔIup and ΔIdn flow in the charge pump circuit to stabilize the output. In this embodiment, the ΔIup and ΔIdn that accurately correspond to such a narrow pulse width can be supplied.

  In the charge pump circuit of this embodiment, the switching operation is fast. Since the amplitude of the output nodes (a) and (b) is the gate-source voltage Vgs of the diode-connected P-channel MOSFET and N-channel MOSFET and is small and close to the threshold voltage Vth of the MOSFET, the full amplitude of the high power supply voltage VddH can be obtained. Transitions can be made much faster than when doing so. In addition, since a short channel thin film MOSFET is used as the MOSFET of the load circuit of the differential circuit, the speed can be further increased.

  The charge pump circuit of this embodiment has low noise. Since the high-speed switching voltage amplitude is low as described above, the amount of noise charge injected by filled-through or the like is reduced as compared with the switching with the full amplitude signal. That is, the parasitic capacitance between the output currents of the MOSFETs MP5 and MN7 and the switching signal is configured to switch the sources of the current MOSFETs MP5 and MN7 of the charge pump circuit with a low amplitude and fix the gate voltage to the bias voltages VBP and VBN. There is little crosstalk.

  The charge pump circuit of this embodiment is a low noise source with no spike current in the high power supply voltage VddH. Therefore, power fluctuation noise due to power line impedance does not occur and other analog circuit blocks connected to the same power line do not have a bad influence as a noise source. The output signal (VddL amplitude) of the high-speed phase comparison circuit PFD having a thin film MOS structure is directly input to the differential input MOSFET, and the differential input MOSFET operates as a current path changeover switch. Only a constant current flows and no spike current is generated. Strictly speaking, during the period in which the charge pump currents Iup and Idn flow, the power supply line is increased or decreased by this amount. Can be ignored.

  FIG. 4 shows a circuit diagram of another embodiment of the charge pump circuit according to the present invention. This embodiment is a modification of FIG. 1, and P-channel MOSFETs MPA and MPB and N-channel MOSFETs MNA and MNB are added to the circuit of FIG. The P-channel MOSFET MPA is connected to the MOSFETs MP1 and MP2 in parallel, and the P-channel MOSFET MPB is connected to the MOSFETs MP3 and MP4 in parallel. A bias voltage Vgp is commonly supplied to the gates of these MOSFETs MPA and MPB. The N-channel MOSFET MNA is connected in parallel to the MOSFETs MN3 and MN4, and the N-channel MOSFET MNB is connected in parallel to the MOSFETs MN5 and MN6. A bias voltage Vgn is commonly supplied to the gates of these MOSFETs MNA and MNB. These MOSFETs MPA, MPB and MNA, MNB are operated as constant current sources.

  The operation will be described by taking N-channel input differential circuits (MN1, MN2) to which up signals UP, UPB are input as an example. When the input signal UP changes from the low level (0 V) to the high level (VddL) and the input signal UPB changes from the high level to the low level, the tail current IB1 flows from the differential MOSFET MN1 to the MN2. The output node (a) rises with its diode characteristics from the voltage Vgsp4 so far to the threshold value (Vth) of the MOSFET MP4. However, charging to the high power supply voltage VddH is accomplished by generating the voltage Vgsp1 at the drain of the MOSFET MP1 and turning on the MOSFET MP3 at this voltage. In this embodiment, the MOSFET MPB for the current source operation is added in parallel to charge the output node (a) toward the high power supply voltage VddH during the transmission time period of this path. After the differential MOSFET MN2 is turned off and the current is cut off, the voltage Vgsp4 is charged by the MOSFET MP4 and MPB up to the threshold (Vth), and the node (a) is charged by the current of the MOSFET MPB after the threshold (Vth). I do. During this time, if the MOSFET MP3 is activated along the path of the MOSFETs MP1-MP3, the MOSFET MP3 is also added for charging. Since the MOSFET MPB charges the output node (a) toward the high power supply voltage VddH immediately after switching the current of the differential circuit, the delay time is shortened. For such an operation, the currents of the MOSFETs MPA and MPB are set to the tail current IB1 or less.

  The MOSFET MPA is provided in order to perform switching opposite to the above at high speed. That is, when the input signal UP changes from the high level (VddL) to the high level (0V) and the input signal UPB changes from the low level (0V) to the high level (VddL), the node (a) is changed at a high speed to cause the MOSFET MP5. Is shut off at high speed. Similarly, the switch control of the N-channel MOSFET MN7 in which the node (b) changes at a high speed in response to the change of the down signals DN and DNB to form the down current Idn by the N-channel MOSFETs MNA and MNB operating as constant current sources. Done.

  FIG. 5 shows a circuit diagram of still another embodiment of the charge pump circuit according to the present invention. In this embodiment, resistors R1 and R2 are used as the load circuit of the differential circuit to reduce the number of elements. That is, the resistor R1 is connected between the drain of the N-channel differential MOSFET MN2 and the high power supply voltage VddH, and the high power supply voltage VddH is applied to the drain of the differential MOSFET MN1. Similarly, a resistor R2 is connected between the drain of the P-channel differential MOSFET MP7 and the ground potential VSS, and the ground potential VSS is supplied to the drain of the differential MOSFET MP6. In this embodiment circuit, the amplitudes of the output nodes (a) and (b) are IB1 × R1 and IB2 × R2, respectively. The transition time of the output node is determined by the capacity of the nodes (a) and (b) and the resistors R1 and R2, and the resistance values of the resistors R1 and R2 need to be reduced in order to increase the speed. In order to cut off the MOSFETs MP5 and MN7 for the charge pump current, the output amplitudes IB1 × R1 and IB2 × R2 are set to the voltages as described above.

  The bias voltage source circuit includes the following circuits. Although not particularly limited, the reference current Icp formed by the digital / analog conversion circuit DAC is supplied to the diode-shaped N-channel MOSFET MN7b. A resistor R2b is provided between the source of the MOSFET MN7b and the ground potential of the circuit. The gate voltage of the MOSFET MN7b is supplied as the bias voltage VBN to the gate of the N-channel MOSFET MN7 via the resistor R3. The MOSFET MB7b is provided with an N-channel MOSFET MN7a in the form of a current mirror and a resistor R2a at the source. The drain current of the MOSFET MN7a flows through the drain of the P-channel MOSFET MP5a. The source of the MOSFET MP5a is supplied with the high power supply voltage VddH via the resistor R1a. Then, the gate voltage of the MOSFET MP5a is supplied as the bias voltage VBP to the gate of the P-channel MOSFET MP5 via the resistor R4.

  The differential amplifier AMP forms the gate voltage of the MOSFET MP5a, that is, the bias voltage VBP so that the drain voltages of the MOSFETs MP5 and MN7 are equal to the drain voltages of the MOSFETs MP5a and MN7a. With this configuration, the resistors R1a and R2a are used so as to be replicas of the differential circuit as in FIG. That is, MP5 = MP5a, R1 = R1a, MN7 = MN7a = MN7b, R2 = R2a = R2b. This configuration controls the bias voltage VBP so that when the down current Idn varies by Δi due to the influence of the drain voltage (CPout) of the MOSFET MN7, the up current Iup also varies by Δi due to the operation of the differential amplifier AMP. Acts as follows.

  FIG. 6 shows a circuit diagram of still another embodiment of the charge pump circuit according to the present invention. In this embodiment, a bias circuit combining the above-described FIG. 5 and FIG. 2 is used for the charge pump circuit as shown in FIG. Also in this embodiment, the bias voltage VBP is controlled corresponding to CPout by the operation of the differential amplifier AMP as in the bias circuit of FIG. The bias circuit of this embodiment can be similarly used for the charge pump circuit shown in FIG.

  FIG. 7 is a block diagram showing an embodiment of a PLL circuit according to the present invention. The PLL circuit includes a phase comparison circuit PFD, a charge pump circuit CP, a low-pass filter LPF, a voltage-controlled oscillation circuit VCO (voltage-current conversion circuit VIC + current-controlled oscillation circuit CCO), and a frequency divider circuit DiV1. The switch SW1 and the current source Iup of the charge pump circuit CP are configured by the P-channel MOSFET MP5, and the switch SW2 and the current source Idn are configured by the N-channel MOSFET MN7. The phase comparison circuit PFD outputs an up signal UP and a down signal DN having a pulse width corresponding to the phase difference between the reference clock Fref and the feedback clock FB. In the PLL circuit of this embodiment, as described above, the charge pump circuit CP is operated directly by the output signals (up signal UP, down signal DN) of the phase comparison circuit PFD. The reference clock Fref has a high frequency such as about 200 to 300 MHz, and the frequency dividing circuit has a frequency dividing ratio of 1 to 1/2. Therefore, the frequency of the internal clock signal Fout is also set to a high frequency such as 200 to 300 MHz or twice the frequency.

  The PLL circuit of this embodiment is operated with two power supply voltages, ie, a high power supply voltage VddH and a low power supply voltage VddL. The high power supply voltage VddH is set to 3.3 V, for example, and the low power supply voltage VddL is set to 1.2 to 1.0 V, for example. The low power supply voltage VddL may be the high power supply voltage VddH formed by a step-down power supply circuit. The phase comparison circuit PFD, the current control oscillation circuit CCO, and the frequency divider circuit DiV1 are operated with the low power supply voltage VddL. The charge pump circuit CP and the voltage / current conversion circuit VIC are operated at the high power supply voltage VddH. The output signal Fout is formed by the frequency dividing circuit DiV2. The frequency divider DiV2 is also operated with the low power supply voltage VddL.

  FIG. 8 shows a circuit diagram of an embodiment of the voltage controlled oscillation circuit VOC of FIG. As described above, the voltage-controlled oscillation circuit of this embodiment is constituted by the voltage-current conversion circuit VIC and the current-controlled oscillation circuit CCO. The control voltage Vc formed by the low pass filter is supplied to the gate of the N-channel MOSFET MN10. A resistor R10 is provided between the source of the MOSFET MN10 and the ground potential of the circuit, and is converted into a current signal Ic (= (Vc−Vth) / R10). This current Ic is supplied to a current mirror circuit composed of P-channel MOSFETs MP10 and M11. The high power supply voltage VddH is supplied to the sources of the MOSFETs MP10 and MP11. The drain current of the MOSFET MP11 is supplied to a current mirror circuit composed of N-channel MOSFETs MM11 and MN12 provided on the ground potential side of the circuit. The drain current of the MOSFET MN12 is used as the operating current of the ring oscillator constituting the current controlled oscillation circuit CCO. The operating voltage of the CMOS inverter circuit constituting this ring oscillator is set to the low power supply voltage VddL. If the breakdown voltage of the N-channel MOSFET MN11 is necessary, a diode-type MOSFET or resistance means may be connected to the drain to reduce the voltage.

  FIG. 9 shows a schematic element structure sectional view of an embodiment of a semiconductor device according to the present invention. In the figure, three MOSFETs MP3, MP4 and MP1 and one N-channel MOSFET MN3 are exemplified by way of example of P-channel MOSFETs used in the semiconductor device according to the present invention. The semiconductor device of this embodiment is not particularly limited, but an N-type well 2 and a P-type well 3 are formed on a P-type semiconductor substrate 1. A field insulating film 4 is formed on the surface of the P-type semiconductor substrate 1 in the boundary region between the N-type well 2 and the P-type well 3. The N-type well 2 is provided with P-channel MOSFETs MP3, MP4 and MP1. The P-type well 3 is provided with an N-channel MOSFET MN3.

  The MOSFET MP1 is formed to have the thinnest film thickness of the gate oxide film (insulating film) 17 that is possible in the process of the semiconductor device. For example, it is molded as thin as about 10 to 30 mm. The channel length is reduced to about 40 to 100 nm. In the MOSFETs MP3 and MP4, the gate oxide film 16 is formed thicker than the MOSFET MP1. This film thickness is set to a thickness of about 50 to 100 mm considering the breakdown voltage of the high power supply voltage VddH. The channel length is also increased to about 400 nm. MOSFETs having a thick film thickness such as N-channel MOSFETs MN1 and MN2 (not shown) are formed in the same manner as the N-channel MOSFETs MP3 and MP4. A MOSFET having a thin film thickness such as a P channel MOSFET MP1 (not shown) is formed in the same manner as the P channel MOSFET MP1. Although not particularly limited, the MOSFETs MP3 and MP4 are formed of a semiconductor region 5 having a common source. The N-type well 2 is provided with the same N-type diffusion layer 8 as the source and drain diffusion layers of the N-channel MOSFET, and a bias voltage VddH is applied thereto.

  The portions overlapping the gate electrodes G of the source, drain 5, 6 and 7 which are the high concentration P type semiconductor regions of the P channel MOSFETs MP3 and MP4 formed in the N type well 2 have a lower concentration p. A type semiconductor region 9 is formed and has an LDD (Lighly Doped Drain Structure) structure. The same applies to the source and drain of the P-channel MOSFET MP1. Further, a portion of the N-channel MOSFET MN3 formed in the P-type well 3 that overlaps with the gate electrode G of the source / drain 13 which is a high-concentration N-type semiconductor region has a lower-concentration N-type semiconductor region. The LDD structure is formed. Below the gate electrodes G in the MOSFETs MP3, MP4, MP1 and MN3, gate oxide films 15 to 18 having different thicknesses determined from the above-mentioned viewpoints are formed, and are formed on the side walls of the gate electrodes G. A sidewall insulating film is formed.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, various embodiments can be employed for the film thickness and element size of the gate insulating film. The ring oscillator may be replaced with a differential amplifier circuit in addition to the one using the CMOS inverter circuit as described above. As described above, the PLL circuit can be widely used for a circuit that operates at a high frequency affected by an unnecessary charge injection amount including a power supply current spike and a feedthrough in a switch MOSFET.

1 is a circuit diagram of an embodiment of a charge pump circuit according to the present invention. FIG. FIG. 2 is a circuit diagram of an embodiment of a bias circuit used in the charge pump circuit of FIG. 1. FIG. 2 is a timing diagram for explaining an example of the operation of the charge pump circuit of FIG. 1. It is a circuit diagram of another embodiment of the charge pump circuit according to the present invention. FIG. 6 is a circuit diagram of still another embodiment of the charge pump circuit according to the present invention. FIG. 6 is a circuit diagram of still another embodiment of the charge pump circuit according to the present invention. 1 is a block diagram of an embodiment of a PLL circuit according to the present invention. FIG. 8 is a circuit diagram of an embodiment of the voltage controlled oscillation circuit VOC of FIG. 7. It is a schematic element structure sectional view of one example of a semiconductor device concerning this invention. It is a block diagram of a PLL examined prior to the present invention.

Explanation of symbols

MP1-MP12 ... P-channel MOSFET, NM1-MN12 ... N-channel MOSFET, C0-C2 ... Capacitor, R1-R4 ... Resistance,
PFD ... Phase comparison circuit, CP ... Charge pump circuit, LPF ... Low pass filter, VIC ... Voltage current conversion circuit, CCO ... Current control oscillation circuit, DiV1,2 ... Division circuit,
DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor substrate, 2 ... N-type well, 3 ... P-type well, 4 ... Field insulating film, 5-7 ... Semiconductor region, 8 ... Diffusion layer, 9, 14 ... P-type semiconductor region 10, 12, 13: Semiconductor region, 15-18: Gate insulating film.

Claims (10)

A phase comparator circuit operating at a first power supply voltage and forming a first output signal and a second output signal corresponding to a phase difference between the first input signal and the second input signal;
A charge pump circuit that operates at a second power supply voltage that is greater than the first power supply voltage and that forms an output current corresponding to the first output signal and the second output signal;
A low-pass filter that forms a control voltage by the output current of the charge pump circuit;
A PLL circuit having a voltage-controlled oscillation circuit whose oscillation frequency is controlled in response to the control voltage,
The charge pump circuit is
A first conductivity type MOSFET that is supplied with a first bias voltage to the gate and forms an up-current from the second power supply voltage side;
A second conductivity type MOSFET that is supplied with a second bias voltage to the gate and forms a down current toward the ground potential side of the circuit;
A first differential MOSFET of a second conductivity type that receives the first output signal and operates differentially;
A first load circuit which is provided on the second power supply voltage side and forms a first voltage signal supplied to the source of the first conductivity type MOSFET corresponding to the output current of the first differential MOSFET;
A first conductivity type second differential MOSFET that differentially operates in response to the second output signal;
A second load circuit provided on the ground potential side of the circuit and forming a second voltage signal supplied to the source of the second conductivity type MOSFET corresponding to the output current of the second differential MOSFET;
The first voltage signal turns off the first conductivity type MOSFET when the first output signal is at a first level, and turns on the first conductivity type MOSFET when the first output signal is at a second level. State to form the up current,
The second voltage signal turns off the second conductivity type MOSFET when the second output signal is at the first level, and turns on the second conductivity type MOSFET when the second output signal is at the second level. A semiconductor device which forms the down current in a state. In claim 1,
The voltage controlled oscillation circuit is
A voltage-current conversion circuit for converting the control voltage into a current signal;
It consists of a ring oscillator whose frequency is controlled by the converted current signal,
The voltage-current conversion circuit operates with the second power supply voltage,
The ring oscillator is a semiconductor device that operates with the first power supply voltage. In claim 2,
The first conductivity type is a P channel type,
The second conductivity type is an N channel type,
The semiconductor device in which the first power supply voltage and the second power supply voltage are positive voltages. In claim 3,
The first load circuit includes:
First and second P-channel MOSFETs in a die-auto form with sources connected to the first power supply voltage side;
The first power supply voltage side is composed of third and fourth P-channel MOSFETs whose source is connected and whose gate and drain are cross-connected,
The drains of the first P-channel MOSFET and the third P-channel MOSFET are connected to one drain of the first differential MOSFET,
The drains of the second P-channel MOSFET and the fourth P-channel MOSFET are connected to the other drain of the first differential MOSFET,
When the first output signal is at the first level, an output current flows through the one drain,
When the first output signal is at the second level, an output current flows to the other drain,
One drain of the first differential MOSFET is connected to the source of the first conductivity type MOSFET,
The second load circuit is
First and second N-channel MOSFETs in the form of a die auto having a source connected to the circuit ground potential side;
The third and fourth N-channel MOSFETs having a source connected to the circuit ground potential side and a gate and a drain cross-connected,
The drains of the first N-channel MOSFET and the third N-channel MOSFET are connected to one drain of the second differential MOSFET,
The drains of the second N-channel MOSFET and the fourth N-channel MOSFET are connected to the other drain of the second differential MOSFET,
When the second output signal is at the first level, an output current flows through the one drain,
When the second output signal is at the second level, an output current flows to the other drain,
A semiconductor device in which one drain of the second differential MOSFET is connected to a source of the second conductivity type MOSFET. In claim 4,
The MOSFETs constituting the phase comparison circuit, the first to fourth P-channel MOSFETs, the first to fourth P-channel MOSFETs, and the MOSFETs constituting the ring oscillator are constituted by MOSFETs of a first gate insulating film,
The first and second differential MOSFETs, the first conductive MOSFET and the second conductive MOSFET, and the MOSFET constituting the voltage-current conversion circuit are thicker than the first gate insulating film. A semiconductor device composed of a MOSFET. In claim 3,
The first load circuit includes:
First and second resistance elements;
A first current source is provided between the source of the first differential MOSFET and the ground potential of the circuit,
The first resistance element is connected to one drain of the first differential MOSFET;
The second resistance element is connected to the other drain of the first differential MOSFET;
When the first output signal is at the first level, the current of the first current source flows to the one drain,
When the first output signal is at the first level, the current of the first current source flows to the other drain,
One drain of the first differential MOSFET is connected to the source of the first conductivity type MOSFET,
The second load circuit is
Third and fourth resistance elements,
A second current source is provided between the source of the second differential MOSFET and the second power supply voltage,
The third resistance element is connected to one drain of the second differential MOSFET;
The fourth resistance element is connected to the other drain of the second differential MOSFET;
When the second output signal is at the first level, the current of the second current source flows to the one drain,
When the first output signal is at the first level, the current of the second current source flows to the other drain,
A semiconductor device in which one drain of the second differential MOSFET is connected to a source of the second conductivity type MOSFET. In claim 6,
The MOSFET that constitutes the phase comparison circuit and the MOSFET that constitutes the ring oscillator are constituted by MOSFETs of a first gate insulating film,
The first and second differential MOSFETs, the first conductive MOSFET and the second conductive MOSFET, and the MOSFET constituting the voltage-current conversion circuit are thicker than the first gate insulating film. A semiconductor device composed of a MOSFET. In claim 5,
The first and second P-channel MOSFETs are provided with a first current source in parallel,
The third and fourth P-channel MOSFETs are provided with a second current source in parallel,
The first and second N-channel MOSFETs are provided with a third current source in parallel,
A semiconductor device in which a fourth current source is provided in parallel to the third and fourth N-channel MOSFETs. In claim 5 or 7,
A first series circuit comprising a fifth P-channel MOSFET of the first gate insulating film, a sixth P-channel MOSFET of the second gate insulating film, and a fifth current source;
The first series circuit is provided between the second power supply voltage and the ground potential of the circuit, and generates the first bias voltage from the gate and drain of the sixth P-channel MOSFET,
A second series circuit comprising a fifth N-channel MOSFET of the first gate insulating film, a sixth N-channel MOSFET of the second gate insulating film, and a sixth current source;
The second series circuit is a semiconductor device that is provided between the second power supply voltage and the ground potential of the circuit, and generates the second bias voltage from the gate and drain of the sixth P-channel MOSFET. In claim 5 or 7,
A first MOSFET of a first conductivity type in which a constant current is allowed to flow and is in the form of a diode;
A first mirror type second MOSFET in the form of a current mirror with the first MOSFET;
A third MOSFET of the second conductivity type in series with the second MOSFET;
A voltage comparison circuit;
Generating the first or second bias voltage from the gate and drain of the first MOSFET, generating the second or first bias voltage from the gate of the third MOSFET;
The voltage comparison circuit includes a gate of the third MOSFET so that a potential of a commonly connected drain of the first conductivity type MOSFET and the second conductivity type MOSFET is equal to a common voltage of the drain of the second MOSFET and the third MOSFET. Forming voltage,
The first MOSFET to the third MOSFET are semiconductor devices composed of the second gate insulating film.

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