JP2008306189A - Method for single-sided polishing of bare semiconductor wafer - Google Patents

Method for single-sided polishing of bare semiconductor wafer Download PDF

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JP2008306189A
JP2008306189A JP2008148771A JP2008148771A JP2008306189A JP 2008306189 A JP2008306189 A JP 2008306189A JP 2008148771 A JP2008148771 A JP 2008148771A JP 2008148771 A JP2008148771 A JP 2008148771A JP 2008306189 A JP2008306189 A JP 2008306189A
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polishing
semiconductor wafer
cloth
polishing cloth
membrane
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Klaus Roettger
レットガー クラウス
Klaus-Peter Meier
マイアー クラウス−ペーター
Norbert Graeml
グレムル ノルベルト
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Siltronic AG
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Siltronic AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/30—Work carriers for single side lapping of plane surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

Abstract

<P>PROBLEM TO BE SOLVED: To provide a single-sided polishing method with which nanotopography of a polished semiconductor wafer satisfies the requirements. <P>SOLUTION: The method for single-sided polishing of a bare semiconductor wafer is accomplished, by using a polishing head provided with a membrane, made of a resilient material. By using the method, polishing pressure is transmitted onto the backside of the semiconductor wafer to be polished, wherein the semiconductor wafer is pressed against a polishing cloth with a smooth surface, while a polishing agent is supported, and is prevented from sliding off the membrane by a retainer ring. The retainer ring is provided with channels on a side surface that faces the polishing cloth. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、弾性的な材料から形成されたメンブレンを備えたポリシングヘッドを使用することによって裸の（テクスチャを有さない）半導体ウェハの片面ポリシング（ＣＭＰ、化学機械的ポリシングのための方法に関し、前記弾性的な材料によって、ポリシングされるべき半導体ウェハの裏側にポリシング圧力が伝達される。メンブレン（メンブレンキャリヤ）を備えたこのようなポリシングヘッド（又はキャリヤヘッド）は、特に電子コンポーネントの構造を平坦化するために使用される。場合によっては、しかしながら、裸半導体ウェハのポリシングのためのポリシングヘッドの使用の報告もある。このことの例は、米国特許出願第２００２／００７７０３９号明細書に示されている。ＣＭＰの中心的な目的は、ポリシングされた半導体ウェハの、最大限の高いグローバル及びローカルな平坦度を達成することである。   The present invention relates to a single-side polishing (CMP, method for chemical mechanical polishing) of a bare (texture-free) semiconductor wafer by using a polishing head with a membrane formed from an elastic material, The elastic material transmits the polishing pressure to the back side of the semiconductor wafer to be polished, such a polishing head (or carrier head) with a membrane (membrane carrier), especially for flattening the structure of electronic components. In some cases, however, there are reports of the use of a polishing head for polishing bare semiconductor wafers, an example of which is shown in US patent application 2002/0077039. The central purpose of CMP is the polished semiconductor Of E c, it is to achieve maximum high global and local flatness.

ポリシングクロスにはしばしば、溝によって形成された表面構造（テクスチャ）が設けられている。溝は、研磨布における研磨剤の均一な分配、ひいては半導体ウェハの均一なポリシングを促進する。米国特許出願第２００５／０２０２７６１号明細書は、溝が設けられた研磨布を使用するＣＭＰ法を記載しており、このＣＭＰ法は、ポリシング剤の分配及び消費に関して最適化されている。
米国特許出願第２００２／００７７０３９号明細書 米国特許出願第２００５／０２０２７６１号明細書 The polishing cloth is often provided with a surface structure (texture) formed by grooves. The grooves facilitate uniform distribution of the abrasive in the polishing cloth and thus uniform polishing of the semiconductor wafer. US Patent Application No. 2005/0202761 describes a CMP method using a grooved abrasive cloth, which is optimized with respect to polishing agent distribution and consumption.
US Patent Application No. 2002/0077039 US Patent Application No. 2005/0202761

ローカル平坦度に関する裸半導体ウェハの特性のための要求条件は、特にナノトポグラフィにおいて常に増大しており、これの要求条件を満たすために、特別な努力が必要である。本特許出願に名を連ねた発明者たちによる実験は、テクスチャを有する研磨布と組み合わせて、裸半導体ウェハをポリシングするためにメンブレンポリシングヘッドを使用することの効果は、ポリシングされた半導体ウェハのナノトポグラフィが要求条件を満たさないということを示した。したがって、彼らの目的は、この欠点を克服し、完全な範囲において現代の要求条件に従う、弾性的な材料から形成されたメンブレンを備えたポリシングヘッドを使用することによる裸半導体ウェハの片面ポリシングのための方法を提供することである。   The requirements for the properties of bare semiconductor wafers with respect to local flatness are constantly increasing, especially in nanotopography, and special efforts are required to meet these requirements. Experiments by the inventors named in this patent application show that the effect of using a membrane polishing head to polish a bare semiconductor wafer in combination with a textured polishing cloth is It showed that topography did not meet the requirements. Therefore, their purpose is for single-side polishing of bare semiconductor wafers by using a polishing head with a membrane formed of an elastic material that overcomes this drawback and complies with modern requirements to the full extent. Is to provide a method.

この目的は、弾性的な材料から形成されたメンブレンを備えたポリシングヘッドを使用することによる裸半導体ウェハの片面ポリシングのための方法によって達成され、ポリシングヘッドによって、ポリシング圧力は、ポリシングされるべき半導体ウェハの裏側に伝達され、半導体ウェハは、研磨剤を供給しながら滑らかな面において研磨布に対して押し付けられ、かつリテーナリングによってメンブレンから滑り落ちるのを防止されており、リテーナリングには、研磨布に面した側面にチャネルが設けられている。   This object is achieved by a method for single-side polishing of a bare semiconductor wafer by using a polishing head with a membrane formed from an elastic material, whereby the polishing pressure is applied to the semiconductor to be polished. Transferred to the back side of the wafer, the semiconductor wafer is pressed against the polishing cloth on a smooth surface while supplying the abrasive, and is prevented from sliding off the membrane by the retainer ring. A channel is provided on the side facing the.

発明者たちは、その研究の過程において、好ましくないナノトポグラフィが、使用されている研磨布の表面構造に実質的に帰することを認識した。研磨布には、研磨布への研磨剤の表面にわたる供給を達成しかつ研磨後に研磨布からの半導体ウェハの持上げを容易にするために、溝のパターンが設けられていた。   The inventors have recognized in the course of their research that undesirable nanotopography is substantially attributed to the surface structure of the polishing cloth being used. The polishing cloth was provided with a pattern of grooves to achieve a supply of abrasive to the polishing cloth across the surface and to facilitate lifting of the semiconductor wafer from the polishing cloth after polishing.

請求項に記載の方法は、所要のナノトポグラフィが達成されることができるように、このような研磨布を排除する。その代わりに、半導体ウェハは、テクスチャを備えない、すなわち滑らかな面を備えた研磨布においてポリシングされ、滑らかな面とは、人工的に付加された凹み、例えば溝又は凹所、及び人工的に付加された突出部、例えばリッジ又はバンプを有さない表面を意味する。研磨布の表面は、ポリシング中に半導体ウェハと接触する領域においてのみ滑らかである必要がある。   The claimed method eliminates such an abrasive cloth so that the required nanotopography can be achieved. Instead, the semiconductor wafer is polished in a polishing cloth without texture, i.e. with a smooth surface, which is an artificially added recess, such as a groove or recess, and artificially By means of a surface without added protrusions, such as ridges or bumps. The surface of the polishing cloth needs to be smooth only in the area that contacts the semiconductor wafer during polishing.

しかしながら、滑らかな面を備えた研磨布の使用は、テクスチャを有する研磨布を使用することによって回避されることができる問題をも伴う。研磨布に設けられた溝は、ポリシング後の研磨布からの半導体ウェハの持上げを容易にする。研磨布と半導体ウェハとの間に包含された研磨剤は、研磨布上の半導体ウェハの強力な接着を保証する。ポリシングヘッドのメンブレンは比較的柔軟であるので、半導体ウェハは、傾斜しやすく、ポリシングヘッドが滑らかな研磨布から持ち上げられる時にメンブレンから分離される。半導体ウェハをポリシングヘッドと共に研磨布から持ち上げようとする場合、したがって、半導体ウェハは研磨布に残ってしまうことがある。これを回避するために、本発明による方法において、好適には３０ｍｍ／ｍｉｎより速く、５０ｍｍ／ｍｉｎよりも遅い速度で、ポリシング後にポリシングヘッドは研磨布から持ち上げられる。より高い速度において、しばしば、半導体ウェハは研磨布上に残される。ポリシングの後、研磨布を持ち上げる前に、研磨布に設けられた溝によって、又はポリシングプレートのエッジによってポリシングヘッドを案内することがさらに好適である。これは、同様に、半導体ウェハの接着を減じるように働く。溝は、ポリシングの間、半導体ウェハによって覆われない研磨布の領域、好適にはエッジ領域に位置する。なぜならば、本発明によれば、滑らかな研磨布はポリシングのために必要とされるからである。   However, the use of a polishing cloth with a smooth surface also involves problems that can be avoided by using a polishing cloth having a texture. The groove provided in the polishing cloth facilitates lifting of the semiconductor wafer from the polishing cloth after polishing. The abrasive contained between the polishing cloth and the semiconductor wafer ensures strong adhesion of the semiconductor wafer on the polishing cloth. Since the membrane of the polishing head is relatively flexible, the semiconductor wafer tends to tilt and is separated from the membrane when the polishing head is lifted from a smooth polishing cloth. When trying to lift the semiconductor wafer together with the polishing head from the polishing cloth, the semiconductor wafer may therefore remain on the polishing cloth. In order to avoid this, in the method according to the invention, the polishing head is lifted from the polishing cloth after polishing, preferably at a speed higher than 30 mm / min and lower than 50 mm / min. At higher speeds, often semiconductor wafers are left on the polishing cloth. It is further preferred that after polishing, the polishing head is guided by a groove provided in the polishing cloth or by the edge of the polishing plate before lifting the polishing cloth. This also serves to reduce the adhesion of the semiconductor wafer. The grooves are located in an area of the polishing cloth, preferably the edge area, that is not covered by the semiconductor wafer during polishing. This is because, according to the present invention, a smooth abrasive cloth is required for polishing.

裸半導体ウェハのポリシングのための考慮されなければならない別の品質パラメータは、ヘイズ（マイクロラフネス）である。研磨布に面した側面においてチャネルが設けられたリテーナリングがポリシングのために使用された場合、特に低いヘイズ値が得られることが分かった。適切なリテーナリングは、例えば米国特許第６２２４４７２号明細書に記載されている。３００ｍｍの直径を備えた裸半導体ウェハをポリシングするために、チャネルの数は好適には少なくとも３０、特に好適には少なくとも４５である。なぜならば、ヘイズ（マイクロラフネス）は、チャネルの数が増大するにつれて減少する傾向がある。   Another quality parameter that must be considered for the polishing of bare semiconductor wafers is haze (microroughness). It has been found that particularly low haze values are obtained when a retainer ring provided with channels on the side facing the abrasive cloth is used for polishing. A suitable retainer ring is described, for example, in US Pat. No. 6,224,472. In order to polish a bare semiconductor wafer with a diameter of 300 mm, the number of channels is preferably at least 30, particularly preferably at least 45. This is because haze (microroughness) tends to decrease as the number of channels increases.

裸半導体ウェハは、金属の不純物又は粒子による汚染から保護されていなければならない。したがって、ポリシングの間、半導体ウェハと直接接触するポリシングヘッドのメンブレンは、適切な材料から形成されていなければならない。できるだけ少ない粒子が形成されるように、メンブレンは、できるだけ金属を解放せず、できるだけ低い摩擦係数を有するべきである。シリコーンから形成されたメンブレンが特に適していることが分かった。   Bare semiconductor wafers must be protected from contamination by metallic impurities or particles. Therefore, during polishing, the membrane of the polishing head that is in direct contact with the semiconductor wafer must be made of a suitable material. The membrane should have as low a coefficient of friction as possible, freeing as much metal as possible, so that as few particles as possible are formed. Membranes formed from silicone have been found to be particularly suitable.

本発明の成功は、例と比較例とを比較することによって以下に実演される。   The success of the present invention is demonstrated below by comparing an example with a comparative example.

例と比較例：
３００ｍｍの直径を備えた、シリコーンから形成された半導体ウェハに、片面ポリシングが行われ、ポリシング結果はナノトポグラフィに関して検査される。本発明に従ってポリシングされた半導体ウェハのグループは、比較例の半導体ウェハと同じ条件においてポリシングされたが、ポリシング後の優れたナノトポグラフィを示した。唯一の相違点は、比較例の半導体ウェハが、テクスチャを有する研磨布上でポリシングされたということである。図１及び図２は、例の半導体ウェハと、比較例の半導体ウェハとにおけるナノトポグラフィ測定の結果をそれぞれ示している。研磨布のテクスチャの痕跡が、比較例の半導体ウェハの場合には明らかに見られ（図２）、これは、ナノトポグラフィが損なわれていることを意味している。 Examples and comparative examples:
A semiconductor wafer made of silicone with a diameter of 300 mm is subjected to single-side polishing and the polishing result is inspected for nanotopography. A group of semiconductor wafers polished according to the present invention were polished under the same conditions as the comparative semiconductor wafer, but showed excellent nanotopography after polishing. The only difference is that the comparative semiconductor wafer was polished on a textured polishing cloth. 1 and 2 show the results of nanotopography measurement on the semiconductor wafer of the example and the semiconductor wafer of the comparative example, respectively. Traces of the texture of the polishing cloth are clearly seen in the case of the comparative semiconductor wafer (FIG. 2), which means that the nanotopography is impaired.

例の半導体ウェハにおけるナノトポグラフィ測定の結果を示している。3 shows the results of nanotopography measurements on an example semiconductor wafer. 比較例の半導体ウェハにおけるナノトポグラフィ測定の結果を示している。The result of the nanotopography measurement in the semiconductor wafer of a comparative example is shown.

Claims (5)

弾性的な材料から形成されたメンブレンを備えたポリシングヘッドによる裸半導体ウェハの片面ポリシングのための方法において、該方法によって、ポリシング圧力が、ポリシングされる半導体ウェハの裏側に伝達され、半導体ウェハが、研磨剤を供給しながら、滑らかな表面を備える研磨布に対して押し付けられかつ、リテーナリングによってメンブレンから滑り落ちることを防止され、リテーナリングの、研磨布に面した側面にチャネルが設けられていることを特徴とする、方法。   In a method for single-side polishing of a bare semiconductor wafer by a polishing head with a membrane formed of an elastic material, the method transmits a polishing pressure to the back side of the semiconductor wafer to be polished, It is pressed against the polishing cloth with a smooth surface while supplying the abrasive, and is prevented from slipping off the membrane by the retainer ring, and a channel is provided on the side of the retainer ring facing the polishing cloth. A method characterized by. 少なくとも３０に等しいチャネルの数を有するリテーナリングが使用される、請求項１記載の方法。   The method of claim 1, wherein a retainer ring having a number of channels equal to at least 30 is used. 半導体ウェハが、ポリシングの後、ポリシングヘッドが研磨布から持ち上げられる前に、研磨布に設けられた溝又は研磨布のエッジによって案内される、請求項１又は２記載の方法。   The method according to claim 1, wherein the semiconductor wafer is guided by a groove or an edge of the polishing cloth provided in the polishing cloth after the polishing and before the polishing head is lifted from the polishing cloth. ポリシングヘッドが、ポリシングの後に、５０ｍｍ／ｍｉｎ以下の速度で研磨布から持ち上げられる、請求項１から３までのいずれか１項記載の方法。   The method according to any one of claims 1 to 3, wherein the polishing head is lifted from the polishing cloth at a speed of 50 mm / min or less after polishing. 半導体ウェハが、シリコーンから形成されたメンブレンを用いてポリシングされる、請求項１から４までのいずれか１項記載の方法。   The method according to claim 1, wherein the semiconductor wafer is polished using a membrane formed from silicone.
JP2008148771A 2007-06-06 2008-06-06 Method for single-sided polishing of bare semiconductor wafer Withdrawn JP2008306189A (en)

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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009030295B4 (en) * 2009-06-24 2014-05-08 Siltronic Ag Method for producing a semiconductor wafer
DE102009030292B4 (en) * 2009-06-24 2011-12-01 Siltronic Ag Method for polishing both sides of a semiconductor wafer
DE102009038941B4 (en) 2009-08-26 2013-03-21 Siltronic Ag Method for producing a semiconductor wafer
DE102009051008B4 (en) 2009-10-28 2013-05-23 Siltronic Ag Method for producing a semiconductor wafer
DE102009052744B4 (en) * 2009-11-11 2013-08-29 Siltronic Ag Process for polishing a semiconductor wafer
DE102010005904B4 (en) 2010-01-27 2012-11-22 Siltronic Ag Method for producing a semiconductor wafer
DE102010010885B4 (en) 2010-03-10 2017-06-08 Siltronic Ag Method for polishing a semiconductor wafer
DE102010013520B4 (en) 2010-03-31 2013-02-07 Siltronic Ag Process for double-sided polishing of a semiconductor wafer
DE102010014874A1 (en) 2010-04-14 2011-10-20 Siltronic Ag Method for producing a semiconductor wafer
DE102010024040A1 (en) 2010-06-16 2011-12-22 Siltronic Ag Process for polishing a semiconductor wafer
CN102263024A (en) * 2011-07-18 2011-11-30 北京通美晶体技术有限公司 Back side anticorrosion method of single side polishing wafer
DE102011082777A1 (en) 2011-09-15 2012-02-09 Siltronic Ag Method for double-sided polishing of semiconductor wafer e.g. silicon wafer, involves forming channel-shaped recesses in surface of polishing cloth of semiconductor wafer
DE102011089362B4 (en) 2011-12-21 2014-01-16 Siltronic Ag A method of polishing a substrate of semiconductor material
DE102012201516A1 (en) 2012-02-02 2013-08-08 Siltronic Ag Semiconductor wafer polishing method for semiconductor industry, involves performing removal polishing on front and back sides of wafer, and single-sided polishing on front side of wafer in presence of polishing agent
DE102013204839A1 (en) 2013-03-19 2014-09-25 Siltronic Ag Method of polishing a wafer of semiconductor material
DE102013205448A1 (en) 2013-03-27 2014-10-16 Siltronic Ag A method of polishing a substrate of semiconductor material
DE102013213838A1 (en) 2013-07-15 2014-09-25 Siltronic Ag A method of polishing a substrate of semiconductor material
DE102015217109B4 (en) 2015-09-08 2022-08-18 Siltronic Ag Process for polishing a substrate made of semiconductor material

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5769696A (en) * 1995-02-10 1998-06-23 Advanced Micro Devices, Inc. Chemical-mechanical polishing of thin materials using non-baked carrier film
JP3106418B2 (en) * 1996-07-30 2000-11-06 株式会社東京精密 Polishing equipment
US5944583A (en) * 1997-03-17 1999-08-31 International Business Machines Corporation Composite polish pad for CMP
US6132294A (en) * 1998-09-28 2000-10-17 Siemens Aktiengesellschaft Method of enhancing semiconductor wafer release
US6287174B1 (en) * 1999-02-05 2001-09-11 Rodel Holdings Inc. Polishing pad and method of use thereof
US6527624B1 (en) * 1999-03-26 2003-03-04 Applied Materials, Inc. Carrier head for providing a polishing slurry
US6224472B1 (en) 1999-06-24 2001-05-01 Samsung Austin Semiconductor, L.P. Retaining ring for chemical mechanical polishing
US6267643B1 (en) * 1999-08-03 2001-07-31 Taiwan Semiconductor Manufacturing Company, Ltd Slotted retaining ring for polishing head and method of using
DE60138343D1 (en) * 2000-07-31 2009-05-28 Ebara Corp Substrate holder and polishing device
EP1193031A1 (en) * 2000-09-29 2002-04-03 Infineon Technologies SC300 GmbH & Co. KG Arrangement for polishing disk-like objects
DE10058305A1 (en) 2000-11-24 2002-06-06 Wacker Siltronic Halbleitermat Process for the surface polishing of silicon wafers
KR100867339B1 (en) * 2000-12-01 2008-11-06 도요 고무 고교 가부시키가이샤 Polishing pad, method of manufacturing the polishing pad
US20030124963A1 (en) * 2001-12-27 2003-07-03 Applied Materials, Inc. Carrier head with a non-stick membrane
TWI289494B (en) * 2002-01-22 2007-11-11 Multi Planar Technologies Inc Chemical mechanical polishing apparatus and method having a retaining ring with a contoured surface for slurry distribution
DE10217374A1 (en) * 2002-04-18 2003-06-18 Wacker Siltronic Halbleitermat Production of semiconductor wafers made from silicon comprises sawing a single crystal made from silicon into silicon wafers, forming a mechanical cut on both sides of the wafers, polishing using polishing plates, and surface polishing
US6869335B2 (en) * 2002-07-08 2005-03-22 Micron Technology, Inc. Retaining rings, planarizing apparatuses including retaining rings, and methods for planarizing micro-device workpieces
JP2005026538A (en) * 2003-07-04 2005-01-27 Renesas Technology Corp Method of manufacturing semiconductor integrated circuit device
KR100600231B1 (en) * 2003-07-12 2006-07-13 동부일렉트로닉스 주식회사 CMP polishing head and its driving method
US6821192B1 (en) * 2003-09-19 2004-11-23 Applied Materials, Inc. Retaining ring for use in chemical mechanical polishing
TWI280177B (en) * 2004-02-02 2007-05-01 Powerchip Semiconductor Corp Dummy process of chemical mechanical polishing process and polishing pad conditioning method
US6951510B1 (en) 2004-03-12 2005-10-04 Agere Systems, Inc. Chemical mechanical polishing pad with grooves alternating between a larger groove size and a smaller groove size
US7201642B2 (en) * 2004-06-17 2007-04-10 Systems On Silicon Manufacturing Co. Pte. Ltd. Process for producing improved membranes
US7029375B2 (en) * 2004-08-31 2006-04-18 Tech Semiconductor Pte. Ltd. Retaining ring structure for edge control during chemical-mechanical polishing
KR100632468B1 (en) * 2005-08-31 2006-10-09 삼성전자주식회사 Retainer ring, polishing head and chemical mechanical polisher
JP2008062355A (en) * 2006-09-08 2008-03-21 Fujitsu Ltd Grinding device and manufacturing method for electronic device

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