JP2008306132A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of further improving the current driving capacity of a field-effect transistor having an n-channel region such as an NMOS transistor. <P>SOLUTION: An NMOS transistor 3 of a semiconductor device includes a semiconductor substrate 1 having an n-channel region, an n-type source/drain region 4, a gate insulating film 7, and a gate electrode 8. The n-type source/drain region 4 is formed in such a manner as to pinch the n-channel region on the semiconductor substrate 1. The gate insulating film 7 is formed on the n-channel region. A method for manufacturing the semiconductor device has a step for forming the gate insulating film 7 and the gate electrode 8 on the semiconductor substrate 1, a step for forming a thin film 20 including a silicon nitride in such a manner as to cover the gate electrode 8 on the semiconductor substrate 1, and a step for irradiating this thin film 20 with ultraviolet rays. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a field effect transistor having an n-channel region.

Conventionally, various techniques have been proposed to improve the current drive capability of NMOS (N-channel Metal Oxide Semiconductor) transistors. For example, according to Non-Patent Document 1, a high tensile silicon nitride layer having a high tensile stress is formed on an NMOS transistor, so that the current driving capability (on-current) of the NMOS transistor is increased. (A value obtained by dividing by an off-current) is disclosed.
S. Pidin et al., "A Novel Strain Enhanced CMOS Architecture Using Selectively Deposited High Tensile And High Compressive Silicon Nitride Films", IEDM Technical Digest, 2004, pp.921-924

  In the above conventional example, a method for further increasing the tensile stress of the formed silicon nitride film is not disclosed. For this reason, there is a problem that the tensile stress of the silicon nitride film cannot be further increased than when the silicon nitride film is formed, and the current driving capability of the NMOS transistor cannot be further improved.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can further improve the current drive capability of a field effect transistor having an n-channel region such as an NMOS transistor. It is to be.

  The semiconductor device of the present invention includes a field effect transistor. The field effect transistor has a semiconductor substrate, n-type source / drain regions, a gate insulating film, and a gate electrode. The semiconductor substrate has an n-channel region. The n-type source / drain regions are formed on the semiconductor substrate so as to sandwich the n-channel region. The gate insulating film is formed on the n-channel region. The gate electrode is formed on the gate insulating film.

The method for manufacturing a semiconductor device of the present invention includes the following steps.
First, a gate insulating film and a gate electrode are formed on a semiconductor substrate. A thin film containing silicon nitride is formed on the semiconductor substrate so as to cover the gate electrode. The thin film is irradiated with ultraviolet rays.

  According to the method for manufacturing a semiconductor device of the present invention, after a thin film containing silicon nitride is formed, the thin film is irradiated with ultraviolet rays. This irradiation improves the tensile stress of the thin film. Therefore, the current driving capability of the NMOS transistor can be further improved as compared with the case where no ultraviolet ray is irradiated.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, the semiconductor device of the present embodiment has a semiconductor substrate 1 which is, for example, a p-type silicon substrate. The semiconductor substrate 1 has an active region partitioned by an element isolation insulating film 2. The element isolation insulating film 2 is made of, for example, a silicon oxide film. The semiconductor device has a plurality of NMOS transistors 3 having a part of the active region of the semiconductor substrate 1 as an n-channel region. Note that since the field effect transistor included in the semiconductor device of this embodiment is a MOS type, the n-channel region is a region formed of a p-type semiconductor.

  Each NMOS transistor 3 has a pair of source / drain regions 4, 4 and a gate structure 6. The pair of source / drain regions 4 and 4 are formed on the upper surface of the semiconductor substrate 1 so as to sandwich the n channel region at a predetermined distance from each other. Two adjacent NMOS transistors 3 and 3 share a source / drain region 4 sandwiched between them. A silicide portion 5 is formed on a part of the upper surface of each source / drain region 4.

  The gate structure 6 is formed on the n-channel region of the semiconductor substrate 1 sandwiched between the two source / drain regions 4 and 4 adjacent to each other and the respective end portions of the two source / drain regions 4 and 4. Yes. The gate structure 6 includes a gate insulating film 7, a gate electrode 8, and sidewalls 10.

  The gate insulating film 7 is formed on the upper surface of the n channel region of the semiconductor substrate 1 sandwiched between a pair of adjacent source / drain regions 4. The gate electrode 8 is formed on the gate insulating film 7. The sidewall 10 is formed on the side surfaces of the gate insulating film 7 and the gate electrode 8. The gate electrode 8 has a polysilicon portion 8a on the side in contact with the gate insulating film 7 (the lower side in the figure), and has a silicide portion 9 on the polysilicon portion 8a.

  The sidewall 10 has a first insulating film 11 and a second insulating film 12. The first insulating film 11 is provided on the side surfaces of the gate insulating film 7 and the gate electrode 8 and on the end portions of the source / drain regions 4. The second insulating film 12 is provided on the first insulating film 11.

  The semiconductor device also has a thin film 20, an interlayer insulating film 21, a contact hole 22, a contact plug 23, and a wiring 24.

  The thin film 20 is formed on the semiconductor substrate 1 so as to cover the gate structure 6. That is, the thin film 20 is formed so as to cover the gate electrode 8.

  The thin film 20 contains silicon nitride. The thin film 20 may contain carbon. The thin film 20 may contain hydrogen.

  The contact hole 22 is a through hole provided in the interlayer insulating film 21. The contact plug 23 is filled in the contact hole 22. The wiring 24 is formed on the contact plug 23.

  Each of the silicide portion 5 and the silicide portion 9 is formed of, for example, nickel silicide or cobalt silicide. Each of the gate insulating film 7, the first insulating film 11, and the interlayer insulating film 21 is formed of, for example, a silicon oxide film. The second insulating film 12 is formed of, for example, a silicon nitride film.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described. 2 to 5 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

  Referring to FIG. 2, element isolation insulating film 2 is formed on semiconductor substrate 1 so as to partition the active region. A plurality of NMOS transistors 3 are formed in this active region of the semiconductor substrate 1. A silicide portion 5 is formed in a portion of the source / drain region 4 that is not covered with the gate structure 6.

  Referring to FIG. 3, thin film 20 is formed on semiconductor substrate 1 so as to cover gate structure 6 of each NMOS transistor 3.

The thin film 20 is, for example, a silicon nitride film. The silicon oxide film can be formed using a plasma CVD method in which a silane compound and nitrogen (N ₂ ) or a nitride compound are used as raw materials and a processing temperature is 200 ° C. or higher and 300 ° C. or lower. For example, SiH ₄ is used as the silane compound, and N ₂ O or NH ₃ is used as the nitride compound.

The thin film 20 may be a silicon nitride film containing carbon. The silicon nitride film containing carbon can be formed using a plasma CVD method using a silane compound and nitrogen or a nitrogen compound as raw materials and a processing temperature of 200 ° C. or more and 400 ° C. or less. As the silane compound, for example, trimethylsilane (3MS) or tetramethylsilane (4MS) is used, and as the nitrogen compound, for example, N ₂ O or NH ₃ is used.

  In the process described later, the portion of the thin film 20 between the two adjacent gate structures 6 can be used as an etching stopper film when the interlayer insulating film 21 is etched to form the contact hole 22 (FIG. 1). Used. Therefore, the subsequent removal of the etching stopper film is facilitated if the portion of the thin film 20 is not excessively thick. Therefore, the thin film 20 is preferably formed so as not to completely fill the space between the two gate structures 6. For this purpose, for example, the film thickness a on the upper surface of the gate structure 6 may be set larger than the film thickness b on the side surface of the gate structure 6.

  Referring to FIGS. 4 and 6, as a post process after forming thin film 20, ultraviolet light is irradiated onto thin film 20 as indicated by solid line arrows in the drawing.

  In order to prepare for this irradiation, first, the semiconductor substrate 1 is taken out from the chamber for forming the thin film 20. Then, the semiconductor substrate 1 is moved into the chamber 100 for ultraviolet irradiation. The atmosphere in the chamber 100 is an atmosphere containing at least one of nitrogen and helium.

  The semiconductor substrate 1 is placed on a susceptor 101 that is a member provided in the chamber 100. The susceptor 101 is held at a high temperature, and the semiconductor substrate 1 is heated by the susceptor 101. The temperature of the susceptor 101 is set to 400 ° C. or higher and 550 ° C. or lower, preferably 400 ° C. or higher and 480 ° C. or lower. Further, when the thin film 20 is formed by the plasma CVD method, this temperature is higher than the processing temperature at the time of formation.

  Then, the rotation shaft 103 that is a shaft perpendicular to the upper surface of the susceptor 101 is used as a rotation shaft, and the susceptor 101 is rotated by 180 ° at a low speed, for example. During this rotation, the semiconductor substrate 1 is irradiated with ultraviolet rays generated from at least one light source 102 installed above the chamber 100.

  The light emission wavelength of the light source 102 is 210 nm to 260 nm, preferably 220 nm to 240 nm. As the light source 102 for generating the ultraviolet light having the above emission wavelength, at least one of an excimer lamp, an excimer laser, a mercury lamp, a xenon lamp, and a deuterium lamp can be used, and in particular, the light emission of KrCl excimer is used. A light source is preferred. In addition to the light source 102, a filter for adjusting the wavelength may be used.

The irradiation intensity of ultraviolet rays is preferably 15 mW / cm ² or more. The rotation direction about the rotation shaft 103 may be clockwise or counterclockwise. By performing the above post treatment, the tensile stress of the thin film 20 increases to, for example, 1.6 GPa.

  Note that the thin film 20 irradiated with ultraviolet rays has a stoichiometric composition ratio (stoichiometric composition ratio) locally in a portion having a cross-link structure. For example, when the thin film 20 is a silicon nitride film, the composition ratio of silicon and nitrogen is Si: N = 3: 4. In addition, the mechanical strength (elastic modulus) of the thin film 20 is improved and is 250 GPa or less.

  Moreover, even if the bond hydrogen concentration of the thin film 20 at the time when the thin film 20 is formed is relatively high, the bond hydrogen concentration is greatly reduced by performing the above post treatment. For this reason, reliability such as hot carrier resistance in the NMOS transistor 3 is hardly deteriorated due to hydrogen.

  Referring to FIG. 5, interlayer insulating film 21 is formed on thin film 20. Next, a contact hole 22 extending from the upper surface of the interlayer insulating film 21 to the silicide portion 5 on the source / drain region 4 between two adjacent gate structures 6 penetrates the interlayer insulating film 21 and the thin film 20. It is formed. When the contact hole 22 is formed, first, the interlayer insulating film 21 is etched using the thin film 20 as an etching stopper film. Thereby, a part of the thin film 20 is exposed. Thereafter, the exposed thin film 20 is removed, and a contact hole 22 is formed.

  Referring again to FIG. 1, contact plug 23 is filled in contact hole 22. Thereafter, a wiring 24 in contact with the contact plug 23 is formed on the interlayer insulating film 21. As described above, the semiconductor device of the present embodiment is obtained.

Next, examples of the method for manufacturing the semiconductor device of the present embodiment will be described. Table 1 is a table summarizing the ultraviolet wavelength, the film stress (tensile stress) after the ultraviolet irradiation of the thin film 20, the irradiation time, and the set temperature of the susceptor 101 (FIG. 6) for six sample semiconductor devices. In addition, the irradiation intensity | strength of the ultraviolet-ray in the sample B-sample G is 15 mW / cm < ² >. Sample A is a comparative example in which only the semiconductor substrate 1 is heated by the susceptor 101 without being irradiated with ultraviolet rays.

  Referring to Table 1, the film stress of the thin film 20 of Sample A (Comparative Example) that was not irradiated with ultraviolet rays was 0.6 GPa. On the other hand, Sample B to Sample G irradiated with ultraviolet rays had a greater film stress on the thin film 20 than Sample A, which is a comparative example. Among Sample B to Sample G, the film stress of the thin film 20 of Sample E was the largest and was 1.6 GPa. From this, it was confirmed by experiments that the ultraviolet irradiation treatment with a wavelength of 222 nm is most effective in improving the film stress (tensile stress) of the thin film 20.

  As described above, particularly when ultraviolet rays having a wavelength of 222 nm were used, the tensile stress was 1.6 GPa, and the tensile stress was particularly greatly improved. This principle can be considered as follows.

  The thin film 20 contains silicon nitride. When silicon nitride is irradiated with ultraviolet rays, the energy of the ultraviolet rays is absorbed by the silicon nitride. As a result, various bonds of silicon nitride (a bond between silicon and nitrogen, a bond between silicon and hydrogen, and a bond between nitrogen and hydrogen) are once broken, and new various bonds are generated. That is, rearrangement of the amorphous structure occurs.

  If the wavelength of the ultraviolet light is smaller than 210 nm, the photon energy is high, and thus even the bonds involved in the film skeleton contributing to the tensile stress of the thin film 20 are cut. This cutting becomes a factor that hinders the improvement of the tensile stress of the thin film 20.

  On the other hand, if the wavelength of ultraviolet rays is larger than 260 nm, the photon energy is low, so that the ultraviolet rays are not sufficiently absorbed by the silicon nitride film, and the crosslinking reaction (cross-linking) due to ultraviolet irradiation does not proceed sufficiently.

  In ultraviolet irradiation with a wavelength of 210 nm or more and 260 nm or less, since the bond between nitrogen and hydrogen is selectively excited, a cross-linking reaction necessary for improving tensile stress is selectively performed, and the composition ratio of silicon nitride is locally chemical. It approaches the stoichiometric composition ratio. As a result, it is considered that the tensile stress is improved to 1.6 GPa as described above. Even when the thin film 20 contains carbon in addition to silicon nitride, the wavelength that promotes the cross-linking reaction necessary for improving the tensile stress is attributed to the bond between nitrogen and hydrogen, and is considered to be the same as that of the silicon nitride film. It is done.

  As described above, when the tensile stress of the thin film 20 is improved, the current driving capability of the NMOS transistor 3 is improved. This principle can be considered as follows.

  Referring to FIG. 4, thin film 20 having a tensile stress gives a force toward gate substrate 6 toward semiconductor substrate 1 (downward in the drawing) as indicated by a broken line arrow in the drawing. As a result, the gate structure 6 is pressed against the n-channel region of the semiconductor substrate 1 along the thickness direction (vertical direction in the drawing) of the semiconductor substrate 1. As a result, tensile stress is generated in the n-channel region in the surface direction of the semiconductor substrate 1 (lateral direction in the figure). Therefore, when the tensile stress of the thin film 20 is improved by ultraviolet irradiation (solid arrow in the figure) to the thin film 20, the tensile stress of the n-channel region is improved.

When a large tensile stress is applied to the n-channel region, the crystal lattice of silicon is distorted in this region, the symmetry of the isotropic band structure of the silicon crystal is lost, and energy level splitting occurs. As a result, carrier scattering and effective mass are reduced due to lattice vibration, and electron mobility is improved. As a result, the effect of improving the current drive capability of the NMOS transistor 3 can be obtained.

In order to utilize the above effect industrially, the irradiation intensity of ultraviolet rays is preferably 15 mW / cm ² or more. Note that when the ultraviolet intensity is less than 15 mW / cm ² , it takes a long time to improve the tensile stress of the thin film 20 by a desired amount, so that the productivity is deteriorated and the unit cost of the process is increased.

  Next, the influence of the temperature (curing temperature) of the semiconductor substrate 1 when ultraviolet irradiation is performed on the characteristics of the NMOS transistor 3 will be described.

  In forming the thin film 20, for example, a plasma CVD method with a processing temperature of 200 ° C. or higher and 300 ° C. or lower is used. Thereafter, the semiconductor substrate 1 is placed on the susceptor 101 at 400 ° C. or higher and 550 ° C. or lower, and the thin film 20 is irradiated with ultraviolet rays. As a result, the tensile stress can be improved efficiently, and the thermal budget can be suppressed. Thereby, inactivation of the impurity diffusion layer of the NMOS transistor 3 can be suppressed, and it is considered that the performance of the NMOS transistor 3 can be improved.

  Note that when the temperature of the susceptor 101 is less than 400 ° C. and the ultraviolet ray treatment is performed, the crosslinking reaction between silicon and nitrogen necessary for improving the tensile stress does not proceed sufficiently. When the temperature of the susceptor 101 exceeds 550 ° C. and the ultraviolet treatment is performed, the thermal budget increases and the silicide portion 5 of the source / drain region 4 and the silicide portion 9 of the gate electrode 8 in the NMOS transistor 3 are adversely affected.

  Next, the effect of rotation of the semiconductor substrate 1 when ultraviolet irradiation is performed will be described. Referring to FIG. 6, the semiconductor substrate 1 is rotated with an axis perpendicular to the upper surface as a rotation axis 103. During this rotation, the thin film 20 is irradiated with ultraviolet rays. Therefore, the thin film 20 can be uniformly irradiated with ultraviolet rays. As a result, the irradiation efficiency of the ultraviolet rays with respect to the thin film 20 is improved, and the processing time of the post processing can be shortened.

  Furthermore, the thin film 20 is uniformly contracted by being uniformly irradiated with ultraviolet rays. Therefore, the film thickness of the thin film 20 can be made uniform.

  Note that, when the thin film 20 is irradiated with ultraviolet rays while the semiconductor substrate 1 is stationary, a portion of the thin film 20 that is easily irradiated with ultraviolet rays and a portion that is difficult to be irradiated are generated. That is, uneven irradiation occurs on the thin film 20. For example, depending on the apparatus used for ultraviolet irradiation, the portion on the side surface of the gate structure 6 and the portion on the upper surface of the semiconductor substrate 1 between the gate structures 6 may be difficult to be irradiated with ultraviolet rays.

  According to the present embodiment, the tensile stress of the thin film 20 is improved by irradiating with ultraviolet rays as indicated by solid arrows in FIG. Thereby, as indicated by a broken line in the figure, the force with which the thin film 20 presses the gate structure 6 against the semiconductor substrate 1 increases. As a result, the tensile stress of the n channel region in the semiconductor substrate 1 is improved, and the current driving capability of the NMOS transistor 3 can be improved.

  Further, when the wavelength of the irradiated ultraviolet ray is 210 nm or more and 260 nm or less, the bond between nitrogen and hydrogen is selectively excited, and the crosslinking reaction necessary for improving the tensile stress is selectively performed. As a result, the tensile stress of the thin film 20 is greatly improved.

Moreover, when the irradiation intensity | strength of the irradiated ultraviolet rays is 15 mW / cm < ² > or more, the time for improving the tensile stress of the thin film 20 only by a desired quantity is suppressed, and productivity can be improved.

  The ultraviolet light source 102 (FIG. 6) is at least one of an excimer lamp, an excimer laser, a mercury lamp, a xenon lamp, and a deuterium lamp. Thereby, ultraviolet rays having a wavelength of 210 nm to 260 nm can be generated.

  Further, the temperature of the susceptor 101 (FIG. 6) is set to 400 ° C. or more and 550 ° C. or less. By setting the temperature to 400 ° C. or higher, the cross-linking reaction between silicon and nitrogen necessary for improving the tensile stress can be sufficiently advanced. Further, by setting the temperature to 550 ° C. or lower, the thermal budget is suppressed, and the adverse effect on the silicide portion 5 of the source / drain region 4 and the silicide portion 9 of the gate electrode 8 in the NMOS transistor 3 can be suppressed.

  Further, the atmosphere in the chamber 100 is an atmosphere containing at least one of nitrogen and helium, and ultraviolet irradiation is performed. Thereby, the oxidation of the thin film 20 can be suppressed.

(Embodiment 2)
7 to 10 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

  Referring mainly to FIG. 7, first, element isolation insulating film 2 and NMOS transistor 3 are formed on semiconductor substrate 1 in the same manner as in the first embodiment (FIG. 2) described above. Next, a partial thin film 20 a that becomes a part of the thin film 20 (FIG. 10) is formed on the semiconductor substrate 1 so as to cover the gate structure 6 of the NMOS transistor 3. Partial thin film 20a can be formed by the same method as thin film 20 in the first embodiment.

  Referring to FIG. 8, a step of causing film contraction in partial thin film 20a is performed. Specifically, the process of irradiating the partial thin film (first thin film) 20a with ultraviolet rays as shown by the solid line arrow is performed in the same manner as the ultraviolet irradiation in the first embodiment.

  In addition, at least one of the step of irradiating the partial thin film 20a with infrared rays, the step of irradiating the partial thin film 20a with an electron beam, and the step of performing plasma treatment on the partial thin film 20a is replaced with the step of irradiating the ultraviolet rays. Alternatively, it may be performed in combination with the ultraviolet irradiation step.

  Referring mainly to FIG. 9, partial thin film 20b, which is a part of thin film 20, is laminated on partial thin film 20a. And the process of generating film contraction in the partial thin film 20b is performed by the same process as the process of generating film contraction in the partial thin film 20a (FIG. 8).

  Referring to FIG. 10, partial thin film 20 c that is a part of thin film 20 is laminated on partial thin film 20 b. Thereby, the thin film 20 which consists of several partial thin films 20a-20c is formed. Then, in the same manner as in the ultraviolet irradiation in the first embodiment, a process of irradiating the thin film 20 (partial thin films 20a to 20c) with ultraviolet rays is performed as indicated by solid line arrows in the figure.

  Thereafter, in the same manner as in the first embodiment, the interlayer insulating film 21, the contact hole 22, the contact plug 23, and the wiring 24 are sequentially formed, and the semiconductor device in the present embodiment is completed.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted.

  According to the present embodiment, film contraction of the partial thin film (first partial thin film) 20a occurs as shown in FIG. Next, as shown in FIG. 9, film contraction of the partial thin film 20b occurs. Next, as shown in FIG. 10, ultraviolet rays are irradiated to cause film shrinkage of the partial thin film (second partial thin film) 20c. That is, the thin film 20 is not contracted at a stretch as in the first embodiment, and the contraction is generated for each of the partial thin films 20a to 20c. Thereby, it is possible to suppress occurrence of cracks in the thin film 20 and peeling of the thin film 20 from the base.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a method for manufacturing a semiconductor device including a field effect transistor having an n-channel region.

1 is a cross sectional view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic explanatory drawing of the chamber for ultraviolet irradiation in the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and its internal structure. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 3 NMOS transistor, 4 Source / drain region, 5,9 Silicide part, 6 Gate structure, 7 Gate insulating film, 8 Gate electrode, 20 Thin film, 20a-20c Partial thin film, 101 Susceptor, 102 Light source, 103 rotation axis.

Claims (6)

a semiconductor substrate having an n-channel region; an n-type source / drain region formed on the semiconductor substrate so as to sandwich the n-channel region; a gate insulating film formed on the n-channel region; and the gate insulation A method of manufacturing a semiconductor device including a field effect transistor having a gate electrode formed on a film,
Forming the gate insulating film and the gate electrode on the semiconductor substrate;
Forming a thin film containing silicon nitride on the semiconductor substrate so as to cover the gate electrode;
And a step of irradiating the thin film with ultraviolet light. ^{2. The} method of manufacturing a semiconductor device according to claim 1, wherein the wavelength of the ultraviolet light is 210 nm or more and 260 nm or less, and the irradiation intensity of the ultraviolet light is 15 mW / cm ² or more.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the ultraviolet light source is at least one of an excimer lamp, an excimer laser, a mercury lamp, a xenon lamp, and a deuterium lamp. The semiconductor device further includes a silicide film formed on the n-type source / drain regions;
The method of manufacturing a semiconductor device according to claim 1, wherein the irradiating step includes a step of heating the semiconductor substrate to 400 ° C. or higher and 550 ° C. or lower.   The method of manufacturing a semiconductor device according to claim 1, wherein the irradiating step is performed in an atmosphere containing at least one of nitrogen and helium. The step of forming the thin film includes a step of forming a first thin film that becomes a part of the thin film, a step of shrinking the first thin film, a part of the thin film on the first thin film, Forming a second thin film comprising:
Shrinking the first thin film comprises irradiating the first thin film with ultraviolet light, irradiating the first thin film with infrared light, irradiating the first thin film with an electron beam, and The method of manufacturing a semiconductor device according to claim 1, wherein the method is at least one of steps of performing plasma treatment on the first thin film.

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