JP2008304976A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent rendering speed from being reduced due to calculation of unnecessary digits after decimal point for high gradation accuracy in gradation rendering in an image display apparatus, which requires not so high accuracy for, for example, color separation in a dual screen for displaying images different depending on visual directions, wherein sub pixels to be combined are gradation-corrected with pixels not to be combined and having the same color. <P>SOLUTION: The device comprises a display part for gradation-displaying luminance of pixels arrayed in a matrix, and a rendering part 10 for calculating gradations with binary numbers. The rendering part 10 operating one operator to which a coefficient α of less than 1 and the other operator to which a coefficient (1-α) is given performs approximate calculation using β which is obtained by reversing each digit of α as an approximate value of (1-α). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image display apparatus that performs gradation rendering of pixels.

A liquid crystal display device or an EL display device performs gradation display of luminance for each pixel or each of RGB sub-pixels constituting the pixel. The gradation is subjected to rendering processing (numerical calculation processing for display) for various purposes (for example, multi-screen color separation countermeasure, liquid crystal panel local color unevenness countermeasure, crosstalk correction).
JP 2006-30362 A

However, the frame period of a liquid crystal display device or an EL display device is usually 60 Hz, and it is required that the gradation rendering process be performed quickly in time. In particular, a multi-screen having a plurality of input images requires a high-speed rendering process because there is a lot of data to be rendered. In the case of rendering processing such as pixel synthesis, gradation interpolation, and correction, there are two calculation terms. When one coefficient is given a coefficient α less than 1, the other calculation term is given a coefficient 1-α. May be. Here, 1−α indicates the remaining coefficient.

For example, as gradation rendering, Japanese Patent Application No. 2007-03891 filed by the present applicant.
In 1, the next sub-pixel gradation is calculated as a measure for color separation of two screens.

(Gradation of subpixel after correction) = (gradation of subpixel before correction) × (1−α) + (average gradation of subpixels of adjacent pixels) × α
In the above formula, α is a 6-bit coefficient of 0 ≦ α <1, and the gradation is 6 bits from 0 to 63. Therefore, this multiplication performs arithmetic processing up to 5 digits after the decimal point in binary. However, since the gradation for color separation measures is to correct the synthesized sub-pixels with the surrounding non-synthesized sub-pixels of the same color, a large error up to 5 gradations can be allowed. Therefore, when a conventional arithmetic unit that accurately calculates all digits is used, calculation processing is performed up to unnecessary lower digits, and there is a problem that it takes time and a device becomes large.

For example, when (1-α) in the above equation is calculated by a normal subtracter as shown in FIG. 23, the 6 bits of the subtracted α are inverted in the first step. In the second step, the least significant digit 1 (2
Add 0.000001 in decimal. In the third step, the subtracted number 1 is added. 4th
In step, subtract 1 which is a carry of α (ie, ignore the most significant digit). However, since the error of omitting the second step is within the allowable range as a measure for color separation on two screens,
The second step is an unnecessary process.

This problem is not just a two-screen problem. Since the screen display driver uses integer gradation control, even the pseudo halftone display FRC (frame rate control) described in Patent Document 1 only needs to have a gradation accuracy of 0.25 unit. Therefore, in rendering in which the gradation of the pixel is calculated by several digits after the decimal, there is a problem that the calculation time is spent by performing an unnecessary calculation as described above.

The invention of the present application has found that there is a case where approximation calculation may be used for rendering of gradation, and has found a method capable of rendering processing in a short time and reducing the circuit size.

In order to solve the above problems, an image display device of the present invention has a display unit that displays gradations of the luminance of pixels arranged in a matrix, and a rendering unit that calculates the gradations in binary numbers,
The rendering unit performs an operation of one operation term given a coefficient α less than 1 and the other operation term given a coefficient 1-α, and β obtained by inverting each digit of α is 1-α. Approximation calculation is performed as an approximate value.

Here, a conventional subtractor calculation method will be described. To make it easier to understand the principle of calculation, a decimal system is used. In the case of 789-123, a method of using the complement of 123 (the number of each digit is added to be 9) 876 is considered, and 789-123 = 789- (999-876)
= 789 + 876 + 1−1000. Thus, the complement of the number to be subtracted is added, 1 is added, and 1000 is subtracted.

In the case of a binary number, the complement can be easily obtained by inverting it with a NOT circuit. Therefore, in the conventional subtracting circuit, as shown in FIG. 23, in the first step, the subtracting 6 bits of α are inverted. In the second step, the lowest digit 1 (binary 0.000001)
Is added. In the third step, the subtracted number 1 is further added. In the fourth step, 1 which is a carry of α is subtracted (that is, the most significant digit is ignored). On the other hand, the present application performs an approximate calculation of only the first step. The calculation error in the second step is within an allowable range, the number to be subtracted in the third step is 1, so that it is ignored as 1-1 = 0, and the fourth step is ignored as in the normal calculation. .

The present invention focuses on the fact that the second step can be ignored in the rendering of the gradation, and the third step can be ignored when calculating 1−α. Thereby, the rendering process can be performed quickly, and the rendering circuit can be downsized.

In addition, a rendering unit that renders two individual images, and data for one display screen is extracted from the two rendered individual images output from the rendering unit, and the pixels of the two individual images are displayed in the horizontal direction of display. A two-screen composition unit that alternately arranges and mixes one mixed image, and a display unit that displays the mixed image output from the two-screen composition unit so that each individual image can be distinguished according to the viewing direction. ,
The coefficient α less than 1 and the correction formula (the gradation of the combined sub-pixel after correction) = (the gradation of the combined sub-pixel before correction) × (1−α) + (the adjacent non-combined pixel) When the average gradation of subpixels) x α is given,
The rendering unit is provided with a coefficient α of less than 1, and performs an approximate calculation using β obtained by inverting each digit of α as an approximate value of 1-α.

In the two-screen display color separation measure that can discriminate different images depending on the viewing direction, the subpixels to be combined are corrected with the surrounding subpixels of the same color that are not combined, so the rendering tolerance is wide. This can be done quickly, and the rendering circuit can be further miniaturized.

In addition, the display unit displays gradations of the luminance of pixels arranged in a matrix, and a rendering unit that performs the gradation calculation in binary, and the rendering unit is provided with a coefficient α less than 1. An arithmetic term and the other arithmetic term to which a coefficient 1-α is given are calculated, α ′ with the least significant digit of α set to 1 is an approximate value of α, and the least significant of α is excluded Approximation calculation is performed using 1-α ′, which is obtained by inverting the digit and setting the least significant digit to 1, as an approximate value of 1-α.

The aforementioned β is a value less than 1−α by the least significant digit 1 (binary 0.000001). Thus, by approximating the coefficient α to α ′, 1 can be obtained with a simple circuit. -Α 'can be obtained. Also, the AND circuit of the least significant digit is deleted from the β circuit described above, and the rendering process can be performed quickly with a small circuit. When the least significant digit of the coefficient α is 1, α ′ = α, and no calculation error of 1−α occurs.

In addition, a rendering unit that renders two individual images, and data for one display screen is extracted from the two rendered individual images output from the rendering unit, and the pixels of the two individual images are displayed in the horizontal direction of display. A two-screen composition unit that alternately arranges and mixes one mixed image, and a display unit that displays the mixed image output from the two-screen composition unit so that each individual image can be distinguished according to the viewing direction. ,
The coefficient α less than 1 and the correction formula (the gradation of the combined sub-pixel after correction) = (the gradation of the combined sub-pixel before correction) × (1−α) + (the adjacent non-combined pixel) When the average gradation of subpixels) x α is given,
α ′ with the lowest digit of α set to 1 is an approximate value of α, and each digit except the lowest digit of α is inverted so that the lowest digit is set to 1, 1-α ′ is an approximation of 1-α Approximate calculation is performed as a value.

In the two-screen display color separation measure that can discriminate different images depending on the viewing direction, the subpixels to be combined are corrected with the surrounding subpixels of the same color that are not combined, so the rendering tolerance is wide. This can be done quickly, and the rendering circuit can be further miniaturized.

Hereinafter, the best embodiment of the present invention will be described with reference to the drawings. However, the embodiment described below exemplifies an image display device for embodying the technical idea of the present invention, and is not intended to identify the present invention as this image display device. Other embodiments within the scope of the claims are equally applicable.

[Image display device]
The image display device according to Example 1 of the present embodiment is an image display device incorporated in an in-vehicle navigation device, and can perform two-screen display that displays different images in the direction of the driver and the direction of the passenger seat. FIG. 1 is a block diagram showing a main part of the image display device 1. FIG. 2 is a cross-sectional view of the display unit 4 showing the principle of two-screen display by the parallax barrier method.

As shown in FIG. 1, the image display device 1 includes a signal processing circuit 2, an EEPROM 3, and a display unit 4. The signal processing circuit is an ASIC, and the navigation unit 10 of the navigation device 100.
1 (RGB, sync signal) and the image signal from the DVD playback unit 102 (RGB,
(Synchronization signal) are rendered respectively, and the two signals subjected to the rendering process are synthesized. The rendering process will be described later in detail. The EEPROM 3 stores a coefficient α used for rendering processing. The display unit 4 displays the image synthesized by the signal processing circuit 2.

FIG. 2 is a diagram showing the configuration of the main part of the display unit 4 that displays different images depending on the viewing direction (driver's seat direction, passenger seat direction). The display unit 4 includes a liquid crystal panel 41, a parallax barrier 42 disposed on the front surface of the liquid crystal panel 41, an upper polarizing plate 43, and a lower polarizing plate 44 disposed on the back surface of the liquid crystal panel 41.
The illumination device 45 is configured.

The liquid crystal panel 41 is a color WVGA and has 800 pixels in the horizontal direction as shown in FIG.
There are 480 pixels in the vertical direction. One pixel is composed of three sub-pixels of RGB. As shown in FIG.
The liquid crystal panel 41 has a structure in which glass substrates 411 and 412 are bonded together with a sealant 413, and a liquid crystal 414 is sealed between the glass substrates 411 and 412. On the inner surface of the rear glass substrate 411, the pixel electrode 41 is provided for each sub-pixel GoL, GoR of 1 dot.
5 is formed, and on the inner surface of the front glass substrate 412, RGB as color filters are formed.
A colored layer 416 and a counter electrode 417 of each color are formed. RGB colored layers 41
6 is formed at a position corresponding to the pixel electrode 415, and the counter electrode 417 is formed on the entire surface of the front glass substrate 412. The lighting device 45 installed on the back side of the liquid crystal panel 41 is:
The liquid crystal panel 41 is irradiated with light through the lower polarizing plate 44.

A parallax barrier 42 as an image separating unit is disposed on the front surface (light emitting surface) side of the liquid crystal panel 41. The parallax barrier 42 is a panel provided with slits 42S at a predetermined interval. In the parallax barrier 42, only a portion where the slit 42S is provided functions as a transmission region that transmits light, and the other portion functions as a light shielding region that does not transmit light. The parallax barrier 42 has, for example, a configuration in which a liquid crystal is sandwiched between two substrates. By controlling the alignment of the liquid crystal, a transmissive region that functions as the slit 42S and a light-shielding region that does not transmit light. And form. The slits 42 </ b> S are located correspondingly between the adjacent colored layers 416 or pixel electrodes 415 in the liquid crystal panel 41. An upper polarizing plate 43 is disposed on the light front side of the parallax barrier 42.

Light emitted from the illumination device 45 enters the liquid crystal panel 41 via the lower polarizing plate 44, passes through the colored layer 416, and then exits from the liquid crystal panel 41. The light emitted from the liquid crystal panel 41 enters a plurality of observers 50R and 50L located at different observation positions through the slit 42S.

In the image display device 1 shown in FIG. 2, the RGB colored layer 416 through which light incident on the viewer 50L is transmitted is shown as colored layers RoL, GoL, and BoL, and the RGB colored layer through which light incident on the viewer 50R is transmitted. 6 is shown as a colored layer RoR, GoR, BoR. Therefore, the sub-pixels SGL having the colored layers RoL, GoL, BoL of the respective colors respectively indicate the RGB sub-pixels of the liquid crystal panel 41 through which the light incident on the observer 11L is transmitted, and the colored layers RoR, Go of the respective colors.
The sub-pixels SGR having R and BoR respectively indicate the sub-pixels of each color of RGB of the liquid crystal panel 41 through which the light incident on the viewer 50R is transmitted.

For example, as indicated by a broken line, the light transmitted through the colored layer GoL enters the observer 50L by passing through the slit 42S positioned correspondingly between the colored layers GoL and BoR.
On the other hand, the light transmitted through the colored layer BcR enters the observer 11R after passing through the slit 42S.

Next, the configuration of the drive circuit of the liquid crystal panel 41 will be described. FIG. 4 is a plan view of the liquid crystal panel 41 in the image display apparatus 1 according to the present embodiment. The liquid crystal panel 41 in the image display device 1 illustrated in FIG. 2 is a cross-sectional view taken along a cutting line AA ′ in the plan view of the liquid crystal panel 41 illustrated in FIG. . In FIG. 4, the vertical direction (column direction) on the paper surface is defined as the Y direction, and the horizontal direction (row direction) on the paper surface is defined as the X direction.

A plurality of scanning lines 4124 and a plurality of data lines 412 are provided on the inner surface of the rear glass substrate 411.
5 are arranged in a matrix, and a switching element 4126 such as a TFT element (Thin Film Transistor) is provided at the intersection of each scanning line 4124 and each data line 4125. The pixel electrode 415 is electrically connected to the switching element 4126.

Precisely, the glass substrate 411 on the back surface is the glass substrate 4 on the front surface with respect to the X direction and the Y direction.
It has the area | region which protrudes outside from 12. FIG. A scanning line drive circuit 4121 is disposed on the inner surface of the rear substrate 1 extending in the X direction, and the data line driver circuit 4122 is disposed on the inner surface of the rear substrate 1 protruding in the Y direction. Is arranged.

Each of the data lines 4125 indicated by S1, S2, S3,..., Sn (n: natural number) extends in the Y direction and is arranged at a constant interval in the X direction. One end of each data line 4125 is electrically connected to the data line driver circuit 4122. The data line driver circuit 4122 is electrically connected to the FPC 4123 through a wiring 4132. FPC4
123 is connected to the two-screen composition unit 6 of the image display apparatus 1 shown in FIG. 1, and the data line driving circuit 4122 receives the image signal (RGB, synchronization signal) from the two-screen composition unit 6 via the FPC 4123. Receive. The data line driving circuit 4122 is based on the image signal, S1, S2,
Data signals are supplied to the data lines 4125 indicated by S3.

Each scanning line 4124 indicated by G1, G2, G3,..., Gm (m: natural number) extends in the X direction and is arranged at a constant interval in the Y direction. One end of each scanning line 4124 is electrically connected to the scanning line driver circuit 4121. In addition, the scan line driver circuit 4121
Are electrically connected to the wiring 4133, and the wiring 4133 is electrically connected to the two-screen composition unit 6. The scanning line driving circuit 4121 receives an image signal from the two-screen composition unit 6 via the wiring 4133. The scanning line driving circuit 4121 is based on the image signal, G1, G2, G
3,..., Scanning signals are sequentially supplied to the scanning lines 4124 indicated by Gm.

The counter electrode 417 is electrically connected to the data line driver circuit 4122 through a wiring 4134 indicated by COM. The data line driving circuit 4122 drives the counter electrode 417 by supplying a driving signal via the wiring 4134 based on the control signal from the two-screen synthesis unit 6.

The scanning line driving circuit 4121 is based on the control signal from the two-screen composition unit 6 and G1, G2, G3
..., the scanning lines 4124 are sequentially and exclusively selected in the order of Gm, and the selected scanning line 41 is selected.
A scanning signal is supplied to 24. The data line driving circuit 4122 includes a two-screen composition unit 6.
Pixel electrode 4 present at a position corresponding to the selected scanning line 4124 based on the image signal from
15, a data signal corresponding to the display content is supplied via each data line 4125. Accordingly, a voltage is applied to the pixel electrode 415, and the pixel electrode 415 and the counter electrode 417 are applied.
The alignment state of the liquid crystal molecules of the liquid crystal 414 is switched between the non-display state and the intermediate display state, and a desired image can be displayed on the liquid crystal panel 41. That is, the two-screen composition unit 6 controls the scanning signals and data signals supplied to the plurality of scanning lines 4124 and the plurality of data lines 4125 by supplying the image signals to the scanning line driving circuit 4121 and the data line driving circuit 4122. The desired image can be displayed on the liquid crystal panel 41.

As shown in FIG. 5, the sub-pixel SGL on which the left input image is displayed and the sub-pixel SGR on which the right input image is displayed are alternately set in the X direction and the Y direction like a checkered pattern. Therefore, the image displayed for the viewer 50L is displayed by switching the alignment state of the liquid crystal molecules of the liquid crystal 4 between the pixel electrode 415 and the counter electrode 417 in the sub-pixel SGL, and is displayed for the viewer 50R. The displayed image is displayed by switching the alignment state of the liquid crystal molecules of the liquid crystal 414 between the pixel electrode 415 and the counter electrode 417 in the sub-pixel SGR.

[2 image display method]
Next, a display image displayed by the image display device 1 according to the present embodiment will be described.

The liquid crystal panel 41 has 800 pixels (horizontal) × 480 pixels (vertical). Accordingly, the two individual images (navigation image and DVD playback image) output from the navigation device 100 of FIG. 1 are images of 800 pixels (horizontal) × 480 pixels (vertical), respectively. Each pixel is RGB
The sub-pixel data is 6 bits indicating gradation, and the luminance of RGB is 2
The sixth power is 64 gradations. The luminance drive control of the scanning line driver circuit 4121 and the data line driver circuit 4122 is in units of one gradation. That is, a gradation that is not an integer cannot be specified. The period of one screen (800 pixels × 480 pixels), that is, the frame period is 60 Hz.

In FIG. 1, the navigation image and the DVD playback image input to the rendering unit 5 of the signal processing circuit 2 are each rendered with α as a coefficient. The rendered navigation image and DVD playback image are combined into a display image of 800 pixels (horizontal) × 480 pixels (vertical) by the two-screen combining unit 6. Note that half of the sub-pixels are not combined in the navigation image and the DVD playback image. In the rendering process, the gradation correction is performed on the subpixels to be combined with the subpixels of the same color that are not combined before the combining process.

FIG. 5 is a diagram conceptually illustrating a method of creating a display image by combining the left input image and the right input image. Here, the left input image is an image displayed to the observer 50L, and the right input image is an image displayed to the observer 50R. The display image is an image obtained by synthesizing the left input image and the right input image, and is an image displayed on the display screen of the liquid crystal panel 41 in the image display device 1.

In FIG. 5, the right input image includes input sub-pixel data Ri1R to Bi4R. Here, the input sub-pixel data is 6-bit data indicating the gradation of the sub-pixel. The alphabetic parts Ri, Gi, Bi in the input sub-pixel data indicate input sub-pixel data of each color of RGB. In FIG. 5, the right input image includes first to fourth four color pixels. The first color pixel is composed of Ri1R, Gi1R, Bi1R, and the second color pixel is composed of Ri2R, Gi2R, Bi2R. The same applies to the third and fourth color pixels. Similarly, the left input image includes first to fourth four color pixels.
The first color pixel is composed of Ri1L, Gi1LL, and Bi1L, and the second color pixel is composed of Ri2L, Gi2L, and Bi2L. The same applies to the third and fourth color pixels.

When the two-screen composition unit 6 creates a display image from the left input image and the right input image, the input subpixel data of the left input image and the input subpixel data of the right input image are converted into the subpixel SGL and the subpixel SGR. It is synthesized to correspond to each of. That is, as described above, the sub-pixel SG
Since L and the sub-pixel SGR are alternately set on the liquid crystal panel 41 in the X direction and the Y direction, the two-screen composition unit 6 performs the input sub-pixel data of the left input image and the right input as shown in FIG. The input sub-pixel data of the image is alternately synthesized corresponding to the sub-pixel SGL and the sub-pixel SGR.

Specifically, when creating the display image from the left input image and the right input image, the two-screen composition unit 6 alternately inputs the input subpixel data of the left input image and the right input image in the row direction and the column direction. This is taken out and used as display sub-pixel data constituting the display image. The display sub-pixel data is 6-bit data indicating the gradation of the sub-pixel. In the example shown in FIG. 5, the input sub-pixel data Ri1R, Bi1R, Gi2R, Gi3R, Ri4R, Bi4 in the input image for right are used.
R is used for the display image. Similarly, the input sub-pixel data Gi1L, R in the left input image
i2L, Bi2L, Ri3L, Bi3L, and Gi4L are used for the display image. A display image is created by alternately arranging these input sub-pixel data in the column and row directions as shown in FIG.

The two-screen composition unit 6 determines the pulse width of the current applied to the pixel electrodes 5 of the sub-pixels SGL and SGR based on the gradation value of the input sub-pixel data in the display image thus created, and the data as the image signal This is supplied to the line drive circuit 22.

In this way, the display image shown in FIG. 5 is displayed on the liquid crystal panel 41 of the image display device 1. On the display image shown in FIG. 5, the position of the slit 42S of the parallax barrier 42 is also indicated by a broken line. Since the viewer 50L views the display image through the slit 42S, the viewer 50L can see only the display sub-pixel data Gi1L, Ri2L, Bi2L, Ri3L, Bi3L, Gi4L,
The left input image can be recognized. On the other hand, the observer 50R displays the display image in the slit 42.
Display sub-pixel data Ri1R, Bi1R, Gi2R, Gi3R, R
Only i4R and Bi4R can be seen, and the right input image can be recognized.

[Problems with color separation]
Next, color separation will be described. In the basic display method described above, if a white line or a white point is included in the input image, color separation occurs in that portion, and a problem that the display image appears partially colored may occur. This will be specifically described.

As shown in FIG. 6, a case is considered where an image in which black and white pixels are arranged vertically and horizontally is input as the right input image and the left input image. In this case, according to the basic display method, as shown in the upper right of FIG. 6, the input sub-pixel data constituting the right input image and the left input image are alternately arranged vertically and horizontally. When this display image is viewed from the front, black and white pixels appear to be correctly arranged for the observer as in the front display image in FIG.

However, the observer 11R on the right side sees only the R and B display pixels as shown in the upper right of FIG. 6 for the white pixels in the display image. Become. Similarly, the viewer 11L on the left side sees only G display pixels, and thus actually sees green pixels instead of white. As described above, when a white line, a white point, or the like is displayed, a phenomenon in which a portion that should originally be white appears to be colored, that is, color separation occurs. This color separation is due to the fact that only half of the right and left input images are used in the basic display method. Therefore, color separation can be suppressed by correcting input sub-pixel data to be combined with adjacent input sub-pixel data that has not been combined.

[Rendering expression to solve the color separation problem]
Therefore, in the present embodiment, before combining, the pixels to be combined of the navigation image and the DVD playback image are rendered (adjustment calculation processing for display) using the adjacent pixels that are not combined and a predetermined coefficient. There are various selection methods for the positions of adjacent pixels used for rendering. As the selection method, when the slit 42S is a checkered parallax barrier 42, the left and right, left only, right only, top and bottom, top only, bottom only, top and bottom, left and right, and two rows of adjacent pixels are paired. There is a method of pairing two rows. The left and right examples will be described as a first rendering method, the upper and lower examples will be described as a second rendering method, and an example in which two columns are paired will be described as a third rendering method. As other methods, the first to third rendering methods can be applied. In addition, when the slit 42S is not a checkered pattern, for example, in the case of a stripe pattern, there is a method of selecting diagonally adjacent pixels.

<< First rendering method: left and right >>
FIG. 7 shows a first rendering method. The input image for the right is a navigation image,
The left image is a DVD playback image. In the example of FIG. 7, for convenience of explanation, it is assumed that both input images are composed of 3 pixels (horizontal) × 2 pixels (vertical) instead of 800 pixels (horizontal) × 480 pixels (vertical). Each pixel has three input sub-pixel data of RGB.

In the rendering of the present invention, display subpixel data is synthesized by combining an average of input subpixel data of the same color of a certain input subpixel data and one or more pixels adjacent to the input subpixel data with a predetermined coefficient α. Create Specifically, the calculation is performed using the following formula.

Input subpixel data = (1−α) × input subpixel data + α × (average of the same color input subpixel data of pixels adjacent to the input subpixel data) (basic formula)
As shown in FIG. 7, in the first rendering method, the left and right sides are adjacent pixels, so the basic formula is as follows.
<In the case of the intermediate pixel Ro2L with adjacent pixels on the left and right>
Ro2L = (1-α) Ri2L + α (Ri1L + Ri3L) / 2
<In the case of the leftmost pixel Ro1R with no adjacent pixel on the left>
Ro1R = (1-α) Ri1R + α (Ri2R)
<In the case of the right end pixel Ro3R with no adjacent pixel on the right>
Ro3R = (1-α) Ri3R + α (Ri2R)
In FIG. 7, an expression of each display sub-pixel data when the target pixel is located in the middle of the input pixel data (that is, not located at the end) is represented by Expression (1-1). The expression of each display subpixel data when it is located at the left end is shown by Expression (1-2), and the expression of each display subpixel data when it is located at the right end is shown by Expression (1-3). ing.

Here, the coefficient α will be described. As understood from the above formula, when the coefficient α = 0, the display sub-pixel data is equal to the input sub-pixel data at the corresponding position. Therefore, when the coefficient α = 0, color separation occurs as described above. On the other hand, when the coefficient is 0.5, the display sub-pixel data is obtained by combining 1/2 of the input sub-pixel data positioned on the left and right with the input sub-pixel data at the corresponding position. Since this is equivalent to performing smoothing filtering, the color separation is reduced, but the resolution of the display image is lowered. For example, when black and white stripes are displayed for each line, a solid gray image is obtained due to the smoothing effect. As described above, the coefficient α is preferably set in a range of 0 <α <0.5.

Furthermore, as a result of confirmation by the inventors' experiment, it was found that α = 0.4 is optimal. As described above, α = 0.5 is optimal from the viewpoint of preventing color separation. However, since the visual sensitivity for human color images is lower than that for black and white (gray) images, α = 0.4 is set. However, the effect of reducing color separation is sufficient. Further, if α = 0.4, it is possible to suppress a decrease in resolution. Therefore, the coefficient is preferably in the range of 0.3 ≦ α <0.5, particularly α
= 0.4 is optimal. Note that the value of the coefficient α may be different for each of the RGB colors, or may be the same value.

<< Second rendering method: top and bottom >>
FIG. 8 shows a second rendering method. In the example of FIG. 8, for convenience of explanation, both input images are not 800 pixels (horizontal) × 480 pixels (vertical), but 2 pixels (horizontal) × 3 pixels (vertical).
It shall be comprised by. As shown in FIG. 8, in the second rendering method,
Since the upper and lower sides are adjacent pixels, the basic formula is as follows.
<In the case of the intermediate pixel Ro3L in which adjacent pixels are above and below>
Ro3L = (1-α) Ri3L + α (Ri1L + Ri5L) / 2
<In the case of the upper end pixel Ro1R with no adjacent pixel>
Ro1R = (1-α) Ri1R + α (Ri3R)
<In the case of the lower end pixel Ro5R where the adjacent pixel is not below>
Ro5R = (1-α) Ri5R + α (Ri3R)
<< Third rendering method: 2-column pair >>
FIG. 9 shows a third rendering method. In the example of FIG. 9, for convenience of explanation, both input images are 2 pixels (horizontal) × 2 pixels (vertical) instead of 800 pixels (horizontal) × 480 pixels (vertical).
It shall be comprised by. As shown in FIG. 9, in the third rendering method,
Since the two columns form a pair and the pixels in one column have the pixels in the other column as adjacent pixels, the basic formula is as follows.
<For paired left pixel Ro1R>
Ro1R = (1-α) Ri1R + α (Ri2R)
<For paired right pixel Ro2L>
Ro2L = (1-α) Ri2L + α (Ri1L)
In the second and third rendering methods, the preferable value of the coefficient α is the same as that in the first rendering method.

[Approximation calculation of rendering]
As described above, in the two-screen display, color separation can be suppressed without reducing the resolution of the display image by rendering the above basic expression using an appropriate coefficient α. In this rendering process, gradation correction is performed on sub-pixels to be combined with sub-pixels of the same color that are not combined, and the allowable error is as large as five gradations. The invention of the present application performs rendering processing quickly by paying attention to the fact that rendering may be approximate calculation.

The approximate calculation of rendering will be described taking the above-described first rendering method in which left and right pixels are adjacent pixels as an example. FIG. 10 is a comparison table of normal calculation and approximate calculation. The approximation calculation of this comparison table is performed by the circuits shown in the block diagrams of FIGS. Since the comparison table of FIG. 10 includes other approximation operations (ignoring the fractional part of multiplication) in addition to the approximation operations of the present invention, the gradation error after correction is 48.75−. 46 = 2.75. As described above, this error is not a problem in practical use, but the error of the approximate calculation according to the present invention is as small as 1.25 when errors of other approximate calculations are excluded, as will be described later.

FIG. 11 is a block diagram of the rendering circuit (right screen R) 10 of FIG. The rendering circuit 10 performs the same operation for the left and right screens, and for a total of six (right screen R, right screen G, right screen B, left screen R, left screen G, left screen B) for each RGB. There is.

FIG. 12 shows the first multiplication circuit 15 of the rendering circuit (right screen R) 10 of FIG. 11, which approximates the basic expression (1-α) × input subpixel data. FIG. 13 shows second multiplication circuits 14A to 14C, which are three identical circuits of the rendering circuit (right screen R) 10 of FIG. 11, and α × (the same color input of pixels adjacent to the input sub-pixel data). Approximate calculation of (average of subpixel data).

In this example, the coefficient α is a value of 5 bits after the decimal point. FIG. 14 shows the value of α in binary notation and 10
It is a contrast table with alpha of a decimal system. As described above, α is optimally about 0.4, so it is 0 in binary.
. 01110 (0.43750 in decimal). The coefficient α is stored in the EEPROM 3 in FIG. 1 and is output via the EEPROM controller 7. The coefficient α can also be output from the navigation device 100 to the rendering unit 5 via the i2c bus register 8. Which coefficient α is output to the rendering unit 5 is selected by the navigation device 100.

FIG. 15 is a diagram showing the operation of the block diagram of FIG. 12, and shows an approximate calculation of (1-α) × input subpixel data. In FIG. 15, it is assumed that the reference input sub-pixel data N1 to be calculated is 101000 (40 in decimal notation). Then, an integer obtained by shifting N1 to the right is obtained. Further, an integer shifted to the right is obtained, and this is repeated 5 times, which is the number of 1-α bits. 1st time is 0
10100, the second time is 000010, the third time is 00101, the fourth time is 000010, 5
The second time becomes 000001. The five bits 01110 of the coefficient α are assigned to the NOT circuit (1 in FIG.
10001 inverted by 51A-E) is defined as β. This β is an approximate 1-α,
β is 0.00001 (0.03125 decimal) less than 1-α. AND the five right shifts (n1) of N1 and the five bits of β. The sum of these five logical products is 010101 (1
21) is calculated in the decimal system. FIG. 15 shows a comparison between the approximate multiplication by the right shift integer and the normal multiplication not approximated. As shown in FIG. 15, the approximate multiplication of this embodiment ignores the decimal part of normal multiplication. As described above, since the approximation calculation is performed while ignoring the decimal part, the calculation process can be speeded up and the calculation circuit can be made small.

The first multiplier circuit 15 of FIG. 12 will be described in comparison with FIG. Six bits of Ri [5: 0] in FIG. 12 are the reference sub-pixel data in FIG. Ri [5: 1] in FIG. 12 is Ri [5: 0].
] Is added to the upper 5 bits, and one 0 bit (1′h0) is added to the higher 5 bits to form 6 bits. This corresponds to the one-time right shift integer 010100 in FIG. Ri [5
: 2] 2'h0, Ri [5: 3] 3'h0, Ri [5: 4] 4'h0, Ri [5]
5'h0 is added to the right shift integer.

Alpha [4: 0] in FIG. 12 is the coefficient α in FIG. An AND circuit 152A is obtained by adding 1'h0 to Ri [5: 0] and inverting alpha [4] by NOT circuit 151A.
Is logically ANDed. alpha [4] is the upper 4 bits of alpha [4: 0], and the inversion by NOT circuit 151A corresponds to 1 of the upper 1 bit of β in FIG. A
The logical product of the ND circuit 152A corresponds to n10 × β, one time 010100 in FIG. A
The logical products obtained by the ND circuits 152A to 152E are summed up by the Adder 153 to be 010101.

As described above, the present application performs an approximate calculation using 1−α as β. Conventionally, 1 is subtracted by a subtractor.
-Α is calculated and input to the AND circuits 152A to 152E. Here, a conventional subtractor calculation method will be described. To make it easier to understand the principle of calculation, a decimal system is used. 789
In the case of −123, consider the method of using the complement of 123 (the number of each digit is 9) 876, 789-123 = 789− (999−876) = 789 + 876 + 1−100
0. Thus, the complement of the number to be subtracted is added, 1 is added, and 1000 is subtracted. In the case of a binary number, the complement can be easily obtained by inverting it with a NOT circuit. Therefore, in the case of a normal subtracting circuit, as shown in FIG. 23, the subtracting 6 bits of α are inverted in the first step. In the second step, the least significant digit 1 (0.00000 in binary)
Add 1). In the third step, the subtracted number 1 is added. In the fourth step, 1 which is a carry of α is subtracted (that is, the most significant digit is ignored).

On the other hand, the present application performs an approximate calculation of only the first step. The calculation error of the second step is within the allowable range, and the number of subtracted third step is 1, so 1-1 = 0 and ignored.
The fourth step ignores the most significant digit. The present invention focuses on the fact that the second step can be ignored in gradation rendering, and the third step can be ignored when calculating the 1-coefficient.

FIG. 16 is a comparison table showing the error when the multiplication of FIG. 10 is not approximated, that is, only the approximate calculation with 1−α as β. In the example of FIG. 16, the error of the approximate calculation in which 1-α is β in the first embodiment of the present invention is 1.25 in decimal. As described above, the gradation for color separation countermeasures is to correct the synthesized sub-pixels with the neighboring sub-pixels of the same color that are not synthesized, so that a large error up to 5 gradations can be allowed. Therefore, an error that ignores the decimal part of multiplication is not a problem in practice. Thereby, the rendering process can be performed quickly, and the rendering circuit can be downsized.

FIG. 17 is a diagram illustrating the operation of the block diagram of FIG. 13, and approximates α × (average of the same color input subpixel data of pixels adjacent to the input subpixel data). In FIG. 17, adjacent subpixel data (average) N2 to be calculated is the average value when there are two adjacent subpixels on the left and right. Here, N2 is set to 111100 (60 in decimal notation). And FIG.
Similarly, an integer obtained by shifting N2 to the right is obtained. Find an integer that is further shifted to the right,
The number of bits is repeated 5 times. The first time is 011110, the second time is 00111, the third time is 000111, the fourth time is 000011, and the fifth time is 000001. AND the 5 right shifts (n1) of N1 and 5 bits of α. The total of these five logical products 011001 (1
25) is calculated in the decimal system. FIG. 17 shows a comparison between the approximate multiplication by the right shift integer and the normal multiplication not approximated. As shown in FIG. 17, the approximate multiplication of this embodiment ignores the decimal part of normal multiplication. As described above, since the approximation calculation is performed while ignoring the decimal part, the calculation process can be speeded up and the calculation circuit can be made small.

The second multiplication circuits 14A to 14C in FIG. 11 are obtained by deleting NOT circuits 151A to 151E from the first multiplication circuit 15 in FIG. Therefore, the multiplication coefficient in FIG. 13 is α.

The rendering circuit (right screen R) 10 in FIG. 11 performs processing including the first rendering method (left and right). The input sub image data Rin _{+ 1} [5: 0] input to the rendering circuit (right screen R) 10 is input until the next input sub pixel data is input by the first register 11A formed of a flip-flop. Stores and holds pixel data. Furthermore,
A similar second register 11B is provided in the subsequent stage of the first register 11A. As a result, n
Where R _{n + 1} [5: 0] is input, the output of the first register 11A is Ri _n [5: 0], and the output of the second register 11B is Ri _{n−. 1} [5
: 0]. Ri _n [5: 0] is the reference input sub-pixel data to be rendered, Ri _n−1 [5: 0] is the input sub-pixel data of the same color of the adjacent pixel on the left side, and Ri
_{n + 1} [5: 0] is the input sub-pixel data of the same color of the pixel adjacent on the right side.

Ri _n [5: 0] and alhpa [4: 0] are input to the first multiplication circuit 15, and the first multiplication circuit 15 approximates β (β≈1-α) to the reference input sub-pixel data. Multiply by. Ri _n-1 [5: 0] and alhpa [4: 0] are input to the second multiplication circuit 14A, and the second multiplication circuit 14A approximates α to the input sub-pixel data of the same color of the adjacent pixel on the left side. Multiply.
Ri _{n + 1} [5: 0] and alhpa [4: 0] are input to the second multiplication circuit 14B, and the second
The multiplication circuit 14B substantially multiplies the input sub-pixel data of the same color of the adjacent pixel on the right side by α. Average data of Ri _n−1 [5: 0] and Ri _{n + 1} [5: 0] and alhpa [4: 0] are input to the second multiplier circuit 14C, and the second multiplier circuit 14C is adjacent to the left and right. The average of the input sub-pixel data of the same color of the pixel is approximately multiplied by α.

The output of the first multiplier circuit 15 and the output of the second multiplier circuit 14A are input to the adder 12B,
The adder 12B adds these. The output of the adder 12B is a calculated value when the reference input sub-pixel data is the rightmost pixel in FIG. The output of the first multiplier circuit 15 and the output of the second multiplier circuit 14B are input to the adder 12C, and the adder 12C adds them. Adder 12C
Is an operation value obtained when the reference input sub-pixel data is the leftmost pixel in FIG. The output of the first multiplier circuit 15 and the output of the second multiplier circuit 14C are input to the adder 12D, and the adder 1
2D adds these. The output of the adder 12D is a calculated value when the reference input sub-pixel data is an intermediate pixel (other than both ends) in FIG. Note that mode [1: 0] and the first selection circuit 16 can select the output of the adder 12B other than the output of the adder 12D or the output of the adder 12C as the output at the intermediate pixel. .

When the reference input sub-pixel data is at the right end, the output of the adder 12B is selected by the EN1, EN2_799, EN800 and the second selection circuit 17, and when the reference input subpixel data is at the left end, the output of the adder 12C is selected. Selects the first selection circuit 16. Then, the second selection circuit 17
1 is delayed by the delay circuit 18 in order to synchronize with other signals to become an output signal Ro _n [5: 0] of the rendering unit, which is input to the two-screen composition unit 6 of FIG.

The rendering circuit (right screen R) 10 of FIG. 11 in FIG. 11 is the R rendering process of the navigation image for the right screen, but the same processing is performed for the navigation images G and B and the DVD playback image for the left screen. For RGB, other rendering circuits (right screen G, right screen B,
Left screen R, left screen G, left screen B). Then, they are input to the two-screen composition unit 6 in FIG.

The navigation image and the DVD playback image input to the two-screen composition unit 6 are synthesized by the above-described method and displayed on the display unit 4 so as to be discriminated by the viewing direction.

Next, Example 2 will be described. FIG. 18 is a block diagram illustrating a first multiplication circuit according to the second embodiment. FIG. 19 is a block diagram illustrating a second multiplication circuit according to the second embodiment. As shown in FIGS. 18 and 19, in the second embodiment, the NOT circuit 151E and the AND circuit 152E, which are multiplications of the least significant digit of β, are deleted from the first multiplication circuit (FIG. 12) of the first embodiment. The second multiplication circuit of Example 1 (FIG. 13
) And the AND circuit 141E which is the multiplication of the least significant digit of α is deleted.

FIG. 20 shows the operation of the block diagram of FIG. 20 is the same as FIG. 15 in the first embodiment.
The fifth bit of β is set to 1 (through) to keep the number to be multiplied. As a result, the data name is set to 1-α 'instead of β.

FIG. 21 shows the operation of the block diagram of FIG. FIG. 21 is the same as FIG.
In this case, the fifth bit of α is set to 1 (through) to keep the number to be multiplied. As a result, the data name is changed to α ′ instead of α. When the least significant digit of α is 0, α ′ is 0.
00001 (0.03125 in decimal) and when the least significant digit of α is 1, α ′ =
α.

In this way, the AND circuit is reduced by directly outputting the multiplied number without passing through the AND circuit. In the first embodiment, the sum of the coefficient of the first multiplier circuit and the coefficient of the second multiplier circuit is not 1. However, the sum is 1 in the second embodiment.
When the least significant digit of the coefficient α is 1, α ′ = α, and no calculation error of 1−α occurs.

FIG. 22 is a comparison table showing errors in the approximation calculation of the second embodiment. The error is 0.8 decimal.
75. As described above, the gradation for color separation countermeasures is to correct the synthesized sub-pixels with the neighboring sub-pixels of the same color that are not synthesized, so that a large error up to 5 gradations can be allowed. Therefore, an error that ignores the decimal part of multiplication is not a problem in practice. Thereby, the rendering process can be performed quickly, and the rendering circuit can be downsized.

The approximate calculation described above relates to the first rendering method, but it can also be applied to the second and third rendering methods. Furthermore, although the above-mentioned embodiment is a checkered slit, it can also be applied to slits of other patterns such as stripes.

Further, although the above-described embodiment has been described with respect to two screens with low permissible accuracy of rendering, it can also be applied to rendering of other gradations. For example, as in Patent Document 1, in the case of FRC (frame rate control) that displays different gradations between frames at a cycle of 4 frames, an illusion of eye is used to simulate 0.25 units of halftone. Since gradation display is performed, rendering of this gradation may be performed in units of 0.25 (2 decimal places in binary).

  Moreover, although the display part of the above-mentioned Example was a liquid crystal, it is applicable also to EL.

It is a block diagram which shows the principal part of the image display apparatus which concerns on this embodiment. Sectional drawing of the display part 4 which shows the principle of 2 screen display by a parallax barrier system. It is a figure which shows the pixel count of a liquid crystal panel. It is a top view of the liquid crystal panel in the image display apparatus concerning this embodiment. A method for creating a display image in the two-screen display mode will be described. It is explanatory drawing of color separation. It is a figure explaining the 1st rendering method. It is a figure explaining the 2nd rendering method. It is a figure explaining the 3rd rendering method. 3 is a comparison table showing errors in approximation calculation in Example 1. FIG. 2 is a block diagram illustrating a rendering circuit of FIG. 1. FIG. 12 is a block diagram illustrating a first multiplication circuit in FIG. 11. FIG. 12 is a block diagram illustrating a second multiplication circuit in FIG. 11. It is a figure which shows the setting register | resistor of the coefficient (alpha). It is a figure which shows the calculation method of FIG. 6 is a comparison table showing only an error in approximation calculation in which 1-α in Example 1 is approximately β. It is a figure which shows the calculation method of FIG. FIG. 6 is a block diagram illustrating a first multiplication circuit according to a second embodiment. FIG. 6 is a block diagram illustrating a second multiplication circuit according to the second embodiment. It is a figure which shows the calculation method of FIG. It is a figure which shows the calculation method of FIG. 10 is a comparison table showing errors in approximation calculation of Example 2. It is a figure which shows the conventional multiplier.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image display apparatus 2 Signal processing circuit 3 EEPROM
DESCRIPTION OF SYMBOLS 4 Display part 41 Liquid crystal panel 4121 Scan line drive circuit 4122 Data line drive circuit 4124 Scan line 4125 Data line 42 Parallax barrier 42S Slit 43 Upper polarizing plate 44 Lower polarizing plate 45 Illuminating device 5 Rendering part 6 2 screen composition part 10 Rendering circuit 11A First register 11B Second register 12A, 12B, 12C, 12D Adder 14A, 14B, 14C Second multiplier circuit 15 First multiplier circuit 16 First selector circuit 17 Second selector circuit 18 Delay circuit 50L , 50R observer 100 navigation device 101 navigation unit 102 DVD playback unit

Claims (4)

A display unit that displays the luminance of pixels arranged in a matrix in gradation, and a rendering unit that performs the calculation of the gradation in binary, and the rendering unit is one of the calculation terms that is given a coefficient α of less than 1 An image display apparatus that performs an operation of the other operation term to which a coefficient 1-α is given and performs an approximate operation using β obtained by inverting each digit of α as an approximate value of 1-α. A rendering unit that renders two individual images, and data for one display screen is extracted from the two rendered individual images output from the rendering unit, and pixels of the two individual images are alternately displayed in the horizontal direction of the display. A two-screen composition unit that arranges and synthesizes one mixed image, and a display unit that displays the mixed image output by the two-screen composition unit so that each individual image can be distinguished according to the viewing direction;
The coefficient α less than 1 and the correction formula (the gradation of the combined sub-pixel after correction) = (the gradation of the combined sub-pixel before correction) × (1−α) + (the adjacent non-combined pixel) When the average gradation of subpixels) x α is given,
The rendering unit is provided with a coefficient α of less than 1, and performs an approximate calculation using β obtained by inverting each digit of α as an approximate value of 1-α. A display unit that displays the luminance of pixels arranged in a matrix in gradation, and a rendering unit that performs the calculation of the gradation in binary, and the rendering unit is one of the calculation terms that is given a coefficient α of less than 1 And the coefficient of 1−α, the other operation term is calculated, α ′ with the least significant digit of α set to 1, α ′ being an approximate value of α, and each digit excluding the least significant digit of α An image display device characterized by approximating 1-α ', which is inverted and having the least significant digit set to 1, as an approximate value of 1-α. A rendering unit that renders two individual images, and data for one display screen is extracted from the two rendered individual images output from the rendering unit, and pixels of the two individual images are alternately displayed in the horizontal direction of the display. A two-screen composition unit that arranges and synthesizes one mixed image, and a display unit that displays the mixed image output by the two-screen composition unit so that each individual image can be distinguished according to the viewing direction;
The coefficient α less than 1 and the correction formula (the gradation of the combined sub-pixel after correction) = (the gradation of the combined sub-pixel before correction) × (1−α) + (the adjacent non-combined pixel) When the average gradation of subpixels) x α is given,
α ′ with the lowest digit of α set to 1 is an approximate value of α, and 1−α ′ is the approximate value of 1−α with the lowest digit turned to 1 by inverting each digit except the lowermost digit of α An image display device characterized by performing approximate calculation as a value.

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