JP2008301146A - Frame synchronization method and device in imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control distortion of an image as much as possible by suppressing generation of disordered synchronization in synchronizing a frame outputted from an imaging apparatus with an external frame synchronization signal inputted from an external circuit. <P>SOLUTION: In the method for synchronizing a frame outputted from the imaging apparatus 2b with an external frame synchronization signal S2 inputted from an external circuit, a phase difference between an internal frame synchronization signal S18 generated by the imaging apparatus 2b and the external frame synchronization signal S2 is detected, the time corresponding the phase difference detected is shared to ensure uniform distribution to a scanning period of each line forming a frame, and the scanning time of each line is adjusted by changing a frequency dividing ratio of a variable frequency divider 22. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a frame synchronization method and apparatus in an imaging apparatus used as a surveillance camera for a building or factory.

  Conventionally, in buildings, factories, department stores, supermarkets, underground malls, etc., surveillance cameras (imaging devices) are installed at multiple locations for monitoring or crime prevention, and the captured images (images) are managed in a management room or central monitoring center. A monitoring system for observing or recording in a recording device is used.

  In such a monitoring system, when the recorded video is played back, it is necessary to be able to play back the video from the plurality of monitoring cameras in synchronization with each other. It is necessary to record the video from the surveillance camera in synchronization.

  In such a monitoring system, in order to synchronize images from a plurality of monitoring cameras, a synchronization signal generator (SYNC GENERATOR) serving as a reference for the image signal is often provided. In that case, each surveillance camera genlocks the frequency and phase in synchronization with the synchronization signal output from the synchronization signal generator. When no synchronization signal generator is provided, a synchronization signal is extracted from a video signal output from another surveillance camera, and a frame is output in synchronization with this.

  Conventionally, various methods have been proposed in order to synchronize the frame of the surveillance camera with a synchronization signal input from the outside of the surveillance camera.

  For example, in Patent Document 1, the frequency of the internal clock is changed based on the phase difference between the external clock input from the outside and the internally generated internal clock, and the frame signal obtained by dividing the external clock and the internal clock are divided. Synchronize with the frame signal.

In Patent Document 2, a coincidence detection is performed between an external synchronization signal that is a synchronization signal of a video signal supplied from the outside and an internal synchronization signal that is a synchronization signal generated internally, and based on the coincidence detection signal, When the synchronization signal is counted to reach a predetermined value, the selection of the external synchronization signal is instructed.
JP 2003-347933 A JP-A-8-32832

  However, conventionally, the phase difference between the external frame synchronization signal of the video signal input from the outside and the internal frame synchronization signal generated inside the surveillance camera is collectively corrected to one line (1-TV line). Therefore, when the frame frequency of the video signal input from the outside fluctuates, or when the deviation from the frequency of the internal frame synchronization signal generated inside the surveillance camera is large even for the same video standard signal There is a problem that synchronization disturbance occurs and the video is distorted.

  Also, the video signal input from the outside has a frame frequency such as RS170 (frame frequency: 30 Hz) which is a video signal standard for monochrome television and RS170A (frame frequency: 29.97 Hz) which is a video signal standard for color television. In a system in which video signals that are slightly different from each other are input, two crystal oscillators corresponding to the respective frame frequencies are provided, and the crystal oscillators are switched according to the input video signal. In this case, there is a problem that the circuit scale becomes large.

  The present invention has been made in view of the above-described problems. In synchronizing a frame output from an imaging apparatus with an external frame synchronization signal input from the outside, occurrence of synchronization disturbance is suppressed and image distortion is suppressed as much as possible. With the goal.

  A method according to the present invention is a method of synchronizing a frame output from an imaging device with an external frame synchronization signal input from the outside, and includes an internal frame synchronization signal generated by the imaging device and the external frame synchronization signal. The time difference corresponding to the detected phase difference is distributed so that the time corresponding to the detected phase difference is uniformly distributed with respect to the scanning time of each line constituting one frame, and the scanning time of each line is adjusted. To do.

  By distributing the time corresponding to the phase difference so as to be uniformly distributed to each line, synchronization disturbance is suppressed and image distortion is also suppressed.

  Further, the internal frame synchronization signal is generated by dividing the clock signal generated inside the imaging apparatus, and the scanning time of each line is adjusted by changing the division ratio of the clock signal. .

  Thus, synchronization can be realized using a single frequency clock signal in response to video signals having different frequencies of the frame synchronization signal.

  According to the present invention, when synchronizing the frame output from the imaging apparatus with the external frame synchronization signal input from the outside, it is possible to suppress the occurrence of synchronization disturbance and to suppress the distortion of the video as much as possible.

  FIG. 1 is a block diagram showing an example of the overall configuration of a monitoring system 1 according to an embodiment of the present invention.

  In FIG. 1, the monitoring system 1 includes a plurality of cameras 2a, 2b, 2c, a controller 3, a management device 4, and the like. The cameras 2a, 2b, and 2c output moving image (image data) DT of about 30 frames per second, and are installed as surveillance cameras in buildings and factories. In the present embodiment, three cameras 2a, 2b, and 2c are shown, but two cameras or four or more cameras may be used.

  Note that all or part of the cameras 2a, 2b, and 2c may be referred to as “camera 2”. The same applies to other elements.

  The controller 3 controls the operation and direction of the cameras 2a, 2b, 2c. In addition, the image DT output from the cameras 2 a, 2 b, 2 c is sent to the management device 4.

  The management device 4 includes a device body 4a and a display device 4b. The apparatus main body 4a is provided with a processing device 4c, a storage device 4d, an input device and an instruction device (not shown), a communication interface, and the like. The images DT output from the cameras 2a, 2b, and 2c are displayed on the screen of the display device 4b and recorded (recorded) in the storage device 4d. The management device 4 can be configured by a computer or the like.

  Of the cameras 2a, 2b, and 2c, one camera 2a is set as a parent camera. The parent camera 2a outputs an image DTa to the cameras 2b and 2c so that the other cameras (child cameras) 2b and 2c are synchronized with the parent camera 2a. Each camera 2b, 2c extracts a frame synchronization signal from the image DTa sent from the parent camera 2a, and uses this to obtain frame synchronization.

  Next, the camera 2b will be described focusing on the circuit for frame synchronization and its operation.

  The camera 2b extracts a frame synchronization signal (external frame synchronization signal) from the image DTa output from the parent camera 2a, and the external frame synchronization signal and the internal frame synchronization signal generated inside the camera 2b are synchronized. To process. That is, the phase difference between the internal frame synchronization signal and the external frame synchronization signal is detected, and the time corresponding to the detected phase difference is uniform with respect to the scanning time of each line (scanning line) constituting one frame. The scanning time for each line is adjusted so as to be distributed.

  At this time, the internal frame synchronization signal is generated by dividing the clock signal generated inside the camera 2b, and the scanning time of each line is adjusted by changing the division ratio of the clock signal.

  More specifically, when the number of clocks of the clock signal generated in the time corresponding to the phase difference is divided by the number of lines constituting one frame and the quotient and the remainder are calculated, the lines constituting one frame For the number of lines corresponding to the remainder value, the scanning time is shortened or extended for each pixel corresponding to the value obtained by adding 1 to the quotient value for each line, and the remaining lines For each line, the scanning time for each pixel corresponding to the quotient value is shortened or extended for each line.

  Also, in this embodiment, based on the phase difference between the external frame synchronization signal and the internal frame synchronization signal, the frequency is controlled by varying the frequency division ratio when generating the recovered clock signal by dividing the clock signal. By doing so, the image synchronization disturbance was eliminated.

  The external frame synchronization signal may be obtained from a synchronization signal generator provided in the controller 3 instead of extracting from the image DTa output from the parent camera 2a. Hereinafter, description will be given with reference to the drawings.

  2 is a diagram showing a circuit of the frame synchronizer FS in the camera 2b, FIG. 3 is a diagram showing an example of the circuit of the clock generator, FIG. 4 is a diagram showing an example of the video signal S1, and FIG. 5 is a diagram of the frame synchronizer FS. FIGS. 6A and 6B are diagrams illustrating the state of signals at each unit, and FIGS.

  In FIG. 2, the camera 2b includes, as a frame synchronization device FS, a synchronization separation unit 11, an edge detection unit 12, an edge detection unit 13, an interval period generation unit 14, a correction pixel number counter 15, a correction line number counter 16, and a pixel number. A register 17, a subtractor 18, a line number register 19, a subtractor 20, a phase determination unit 21, a variable frequency divider 22, a pixel counter 23, a line counter 24, a frame counter 25, a clock generator 26, and the like are provided. .

  The synchronization separation unit 11 separates and extracts a frame synchronization signal (external frame synchronization signal) S2 included in the video signal (image signal) S1 output from the camera 2a.

  As shown in FIG. 4, in the video signal S1, for example, one frame is composed of two fields, and each field includes a vertical synchronizing signal, a horizontal synchronizing signal for 262.5 lines, and a video signal. . The number of lines composing one frame is 525. Since the scanning time of one frame is 1/30 second, the frequency of the frame synchronization signal S2 is 30 Hz, and rises every 1/30 second and falls after 1/60 second of each.

  The edge detection unit 12 detects the rising edge (the leading edge shown in FIG. 4) of the frame synchronization signal S2 extracted by the synchronization separation unit 11, and outputs an edge signal (edge pulse) S3 synchronized with the rising edge.

  The edge detection unit 13 detects the rising edge (the leading edge shown in FIG. 4) of the frame synchronization signal (internal frame synchronization signal) S18 generated inside the camera 2b, and outputs an edge signal (edge pulse) S4 synchronized with the rising edge. To do.

  The interval period generator 14 detects the phase difference based on these two edge signals S3 and S4. That is, the time width T1 indicating the time from the input time point of the signal input earlier to the input time point of the signal input later is detected from among the edge signals S3 and S4, and is turned on during the time width T1 (“H The phase difference interval period signal S5 that is “level” is output.

  The correction pixel number counter 15 counts the clock signal CLK output from the clock generator 26 while the phase difference interval period signal S5 is ON, and counts the number of lines per frame (here, “525”). A carry signal S6 is output every time. That is, the correction pixel number counter 15 clears the count value to 0 when the count value reaches the number of lines per frame, and outputs the carry signal S6 each time. The count value when the phase difference interval period signal S5 is turned off is output as it is as the count value S7.

  Therefore, the correction pixel number counter 15 divides the clock number of the clock signal CLK generated in the time corresponding to the phase difference by the number of lines constituting one frame, and the number of carry signals S6 corresponding to the quotient. And the count value S7 corresponding to the remainder is output.

  The correction line number counter 16 counts the carry signal S6 output from the correction pixel number counter 15, and outputs the count value S8.

  For example, if the number of clock signals CLK while the phase difference interval signal S5 is ON is “1200”, 1200 ÷ 525 = 2 remainder 150, so the count value S8 is “2” and the count value S7 is “150”.

  “2” of the count value S8 is the number of pixels on which frequency control for correcting the phase difference is to be performed on all lines, and “150” of the count value S7 is a line on which frequency control of one pixel is additionally performed. Indicates a number.

  The count values S7 and S8 of the correction pixel number counter 15 and the correction line number counter 16 are cleared for each frame.

  The pixel number register 17 stores the number of pixels per line, and the line number register 19 stores the number of lines per frame. In this example, “780” is stored as the number of pixels per line, and “525” is stored as the number of lines per frame.

  The subtracter 18 subtracts the count value S8 of the correction line number counter 16 from the number of pixels stored in the pixel number register 17, and outputs a subtraction value S9 as a result. The subtraction value S9 is a pixel number of each line where frequency control is started (hereinafter sometimes referred to as “control start pixel number”).

  In this example, since 780-2 = 778, frequency control is performed on the 778th and 779th pixels for all lines. Here, it is assumed that numbers 0 to 779 are assigned to 780 pixels.

  The subtracter 20 subtracts the count value S7 of the correction pixel number counter 15 from the number of lines stored in the line number register 19, and outputs a subtraction value S10 as a result. The subtraction value S10 is a line number for additionally performing frequency control of one pixel in addition to frequency control of two pixels of all lines (hereinafter, may be referred to as “additional control start line number”).

  In this example, since 525-150 = 375, the frequency control is further performed for one pixel for the 375th and subsequent lines. That is, for the 375th and subsequent lines, frequency control is performed for a total of three pixels.

  The phase determination unit 21 compares the edge signal S3 and the edge signal S4 to determine whether the phase is a leading phase or a lagging phase. That is, if the frame synchronization signal S18 is advanced with respect to the frame synchronization signal S2, the PLUS signal S11 indicating the advance phase is output, and if it is delayed, the MINUS signal S12 indicating the delay phase is output. When the phase difference is zero, that is, when the phases match, no output is made. In that case, the variable frequency divider 22 maintains the original counter decode value and does not change the frequency division ratio.

  The variable frequency divider 22 divides the clock signal CLK by a variable frequency dividing ratio and outputs a reproduction clock signal S13. When the PLUS signal S11 is output from the phase determination unit 21, the variable frequency divider 22 increases the division ratio by increasing the counter decode value in order to extend the scanning time, and the recovered clock signal S13. Reduce the frequency. For example, when the counter decode value in a steady state is “10”, that is, the frequency division ratio is 1/10, the counter decode value is incremented by 1 and the frequency division ratio is 1/11. On the contrary, when the MINUS signal S12 is output, in order to shorten the scanning time, the frequency division ratio is decreased by decreasing the counter decode value, and the frequency of the reproduction clock signal S13 is increased. For example, the counter decode value is minus 1 and the division ratio is 1/9.

  However, the variable control of the frequency division ratio in the variable frequency divider 22 is performed only for the reproduction clock signal S13 corresponding to the line number and pixel number specified by the subtraction value S9 and the subtraction value S10. Note that the pixel position in one frame coincides with the clock position of the reproduction clock signal S13.

  For example, in this example, the division ratio is set to 1/9 only for the 778th and 779th pixels of all lines and the 1st pixel of the 375th and subsequent lines, As a result, the frequency of the corresponding pixel in each line is increased, and the scanning time for the entire line is shortened. In FIG. 5, frequency control is performed at clock positions (pixel positions) indicated by diagonal lines in each line of the variable frequency divider described in the bottom column.

  That is, as shown in FIG. 6, when there is no phase difference, the frequency division ratios are all 1/10 as shown by CL1, but when the phase difference occurs as shown above, a diagonal line is put. For the reproduction clock signal S13 corresponding to the indicated clock position (pixel position), the frequency division ratio is changed to 1/9 as indicated by CL2.

  As a result, the period of the frame synchronization signal S18 is shortened, and the end of the frame synchronization signal S18 almost coincides with the end of the frame synchronization signal S2 although the rising edge at the leading edge is delayed with respect to the frame synchronization signal S2. As a result, the phase difference with respect to the frame synchronization signal S2 is eliminated, and frame synchronization is achieved. In addition, since the scanning time of each line constituting one frame is adjusted uniformly or evenly, the distortion of the image can be suppressed without causing the synchronization disturbance.

  The pixel counter 23 counts the reproduction clock signal S13 and outputs a count value S14 indicating the pixel number in each line. That is, the pixel counter 23 counts the reproduction clock signal S13, and clears the counter when the number of pixels per line is reached. A carry signal S15 is output every time the counter is cleared once.

  The line counter 24 counts the carry signal S15 output from the pixel counter 23, and outputs a count value S16 indicating the line number. The line counter 24 clears the counter when the count value S16 reaches the number of lines per frame.

  The frame counter 25 counts the reproduction clock signal S13 and outputs a frame synchronization signal S18. The frame synchronization signal S18 is generated, for example, by inverting “H” and “L” every time the number of pixels per half frame is reached. Further, the frame synchronization signal S18 may be generated using the carry signal S17 output from the line counter 24.

  In order to obtain the count values S14 and S16 and the frame synchronization signal S18, the pixel counter 23, the line counter 24, the frame counter 25, and the like can be configured in various combinations other than those described above.

  The clock generator 26 generates a clock signal CLK having a higher frequency than the reproduction clock signal S13. The clock signal CLK is frequency-divided by the variable frequency divider 22 to become a reproduction clock signal S13 corresponding to the pixel of the video signal.

  As shown in FIG. 3, the clock generator 26 includes a crystal oscillator 31 and a multiplier 32. In this example, a clock signal having a frequency of 12.2727 MHz is generated by the crystal oscillator 31, multiplied by 10 by the multiplier 32, and a clock signal CLK having a frequency of 122.727 MHz is output.

  Thus, in this example, the counter decode value of the variable frequency divider 22 is set to “10”, and the clock signal CLK having a frequency 10 times that of the reproduction clock signal S13 is generated. Then, the correction pixel number counter 15 counts the clock signal CLK that is ten times the reproduction clock signal S13, so that the number of clocks counted by the correction pixel number counter 15 is ten times that of the reproduction clock signal S13. Accordingly, the frequency division ratio of the reproduction clock signal S13 of the corresponding pixel is set to 1/11 or 1/9, and thereby the frequency of the reproduction clock signal S13 is changed by about 10%, so that the entire period of the frame synchronization signal S18 is changed. Is adjusted to eliminate the phase difference from the frame synchronization signal S2.

  Since the frequency division ratio in the variable frequency divider 22 is discrete, it is not always possible to achieve complete synchronization by frequency control of one frame synchronization signal S18. However, such frequency control is continuously applied to each frame. As a result, the phase difference between the frame synchronization signal S18 and the frame synchronization signal S2 is not accumulated, and the frame synchronization between the image DTa of the parent camera 2a and the image DTb of the child camera 2b can be achieved. .

  The camera 2b may be configured to output a video signal using the reproduction clock signal S13 or signals output from the pixel counter 23, line counter 24, and frame counter 25.

  In the embodiment described above, the frequency dividing ratio is varied using the variable frequency divider 22 with respect to the clock signal CLK output from the clock generator 26, thereby generating the frame synchronization signal S18. The frequency frame synchronization signal S18 can be easily generated. Therefore, even in a system in which video signals having different frame synchronization signal frequencies are input, synchronization can be realized by the clock generator 26 using a single crystal oscillator (crystal). Therefore, the circuit scale does not increase as in the case where a plurality of crystal oscillators are provided.

  In the embodiment described above, when the phase difference between the frame synchronization signal S2 and the frame synchronization signal S18 exceeds the standard value of the scanning time of one line, it is distributed to each line within the range not exceeding the standard value. You can do it.

  In the embodiment described above, the pixel number for the line on which additional frequency control is performed is the first number. However, other pixel numbers, for example, the number 777 in the above example may be used. Also, with respect to pixel numbers for which frequency control is performed on all lines, frequency control may be performed on pixels with other numbers.

  In the above embodiment, the counter decode value of the frequency division ratio of the variable frequency divider 22 is “10”, but other values such as “8”, “12”, “16”, “32”, etc. An appropriate value may be set, and the frequency of the clock signal CLK of the clock generator 26 may be set accordingly. Further, when the frequency division ratio is varied, the counter decode value is set to plus 1 or minus 1, but may be plus 2, 3, 4, or minus 2, 3, 4, or the like. Further, the frequency division ratio may be varied according to the magnitude of the phase difference. Further, the frequency division ratio may be varied according to the clock position (pixel position).

  In the above embodiment, the edge detection unit 12, the edge detection unit 13, the interval period generation unit 14, and the phase determination unit 21 correspond to “phase difference detection unit” or “phase difference detection unit” in the present invention. . Further, the correction pixel number counter 15, the correction line number counter 16, the pixel number register 17, the subtracter 18, the line number register 19, the subtractor 20, the phase determination unit 21, and the variable frequency divider 22 are included in It corresponds to “a means for adjusting the scanning time of each line by distributing the time corresponding to the phase difference so as to be uniformly distributed with respect to the scanning time of each line constituting one frame” or “control unit”. The phase determination unit 21 corresponds to the “phase advance / delay determination unit” in the present invention. The subtraction value S9 and the subtraction value S10 correspond to the “clock position designation signal” in the present invention.

  In the above embodiment, the frame synchronizer FS is realized by hardware using circuit elements, by software executed by a CPU or DSP executing a program stored in a memory, or by a combination thereof. It is possible.

  In the above embodiment, the frame period, the number of lines in one frame, the number of pixels in one line, and other constants and values are not limited to those described above. In addition, the structure, configuration, shape, number, processing contents, etc. of the whole or each part of the frame synchronization device FS, the camera 2b, or the monitoring system 1 can be appropriately changed in accordance with the spirit of the present invention.

The embodiment described below is also included in this embodiment.
(Appendix 1)
A method of synchronizing a frame output from an imaging device with an external frame synchronization signal input from the outside,
Detecting a phase difference between the internal frame synchronization signal generated by the imaging device and the external frame synchronization signal;
The time corresponding to the detected phase difference is distributed so as to be uniformly distributed with respect to the scanning time of each line constituting one frame, and the scanning time of each line is adjusted.
A frame synchronization method in an imaging apparatus.
(Appendix 2)
The internal frame synchronization signal is generated by dividing the clock signal generated inside the imaging device,
Adjusting the scanning time of each line by varying the frequency division ratio of the clock signal;
A frame synchronization method in the imaging apparatus according to attachment 1.
(Appendix 3)
When the quotient and the remainder are calculated by dividing the number of clocks of the clock signal generated in the time corresponding to the phase difference by the number of lines constituting one frame, the line of the lines constituting one frame For the number of lines corresponding to the remainder value, the scanning time is shortened or extended for each number of pixels corresponding to the value obtained by adding 1 to the quotient value for each line, and the rest For each of the lines, for each line, the time for performing scanning for each number of pixels corresponding to the value of the quotient is shortened or extended.
A frame synchronization method in the imaging apparatus according to attachment 2.
(Appendix 4)
A frame synchronization device in an imaging device for synchronizing a frame output from the imaging device with an external frame synchronization signal input from the outside,
Means for detecting a phase difference between the internal frame synchronization signal generated by the imaging apparatus and the external frame synchronization signal;
Means for distributing the time corresponding to the detected phase difference so as to be uniformly distributed with respect to the scanning time of each line constituting one frame, and adjusting the scanning time of each line;
A frame synchronization apparatus in an imaging apparatus, comprising:
(Appendix 5)
A frame synchronization device in an imaging device for synchronizing a frame output from the imaging device with an external frame synchronization signal input from the outside,
A clock signal generator;
A variable divider for dividing the clock signal by a variable dividing ratio;
A frame counter that divides the recovered clock signal output from the variable frequency divider to generate an internal frame synchronization signal;
A phase difference detector that detects a phase difference between the internal frame synchronization signal and the external frame synchronization signal;
Based on the number of clocks of the clock signal generated in the time corresponding to the phase difference, the frequency dividing ratio of the variable frequency dividing unit is varied, and one line included in each line constituting one frame. A control unit that adjusts the scanning time of each line by varying the period of the reproduction clock signal;
A frame synchronization apparatus in an imaging apparatus, comprising:
(Appendix 6)
The control unit outputs a clock position designation signal that designates a clock position to be adjusted in each line constituting one frame based on the number of clocks of the clock signal generated in a time corresponding to the phase difference. ,
The variable frequency dividing unit may change the frequency dividing ratio to be small or large when the clock position in each line in one frame based on the reproduced clock signal coincides with the clock position of the clock position designation signal. Controlled to adjust the scanning time of each line,
The frame synchronization apparatus in the imaging apparatus according to appendix 5.
(Appendix 7)
The controller is
Counting the clock signal generated at a time corresponding to the phase difference, obtaining a quotient and a remainder divided by the number of lines constituting one frame, and based on the obtained quotient and remainder, the variable frequency dividing unit Output the clock position in each line in one frame in which the frequency division ratio is variable to the variable frequency divider.
The frame synchronization apparatus in the imaging apparatus according to appendix 6.
(Appendix 8)
A phase advance / delay determination unit for determining a phase advance or delay in the internal frame synchronization signal and the external frame synchronization signal is provided;
The variable frequency dividing unit varies the frequency dividing ratio to be small or large based on the output from the phase advance / delay determining unit when the control unit varies the frequency dividing ratio.
The frame synchronization apparatus in the imaging apparatus according to appendix 7.

It is a block diagram which shows the example of the whole structure of the monitoring system which concerns on this invention. It is a figure which shows the circuit of the frame synchronizer in a camera. It is a figure which shows the example of the circuit of a clock generator. It is a figure which shows the example of a video signal. It is a figure which shows the state of the signal of each part in a frame synchronizer. It is a figure explaining the mode of frequency control in each clock position.

Explanation of symbols

1 Monitoring system 2b, 2c Camera (imaging device)
12 Edge detection unit 13 Edge detection unit 14 Interval period generation unit 15 Correction pixel number counter 16 Correction line number counter 21 Phase determination unit 22 Variable frequency divider 23 Pixel counter 24 Line counter 25 Frame counter 26 Clock generator FS Frame synchronization device S2 Frame sync signal (external frame sync signal)
S9 Subtraction value (clock position designation signal)
S10 Subtraction value (clock position designation signal)
S18 Frame synchronization signal S (internal frame synchronization signal)

Claims (5)

A method of synchronizing a frame output from an imaging device with an external frame synchronization signal input from the outside,
Detecting a phase difference between the internal frame synchronization signal generated by the imaging device and the external frame synchronization signal;
The time corresponding to the detected phase difference is distributed so as to be uniformly distributed with respect to the scanning time of each line constituting one frame, and the scanning time of each line is adjusted.
A frame synchronization method in an imaging apparatus. A frame synchronization device in an imaging device for synchronizing a frame output from the imaging device with an external frame synchronization signal input from the outside,
Means for detecting a phase difference between the internal frame synchronization signal generated by the imaging apparatus and the external frame synchronization signal;
Means for distributing the time corresponding to the detected phase difference so as to be uniformly distributed with respect to the scanning time of each line constituting one frame, and adjusting the scanning time of each line;
A frame synchronization apparatus in an imaging apparatus, comprising: A frame synchronization device in an imaging device for synchronizing a frame output from the imaging device with an external frame synchronization signal input from the outside,
A clock signal generator;
A variable divider for dividing the clock signal by a variable dividing ratio;
A frame counter that divides the recovered clock signal output from the variable frequency divider to generate an internal frame synchronization signal;
A phase difference detector that detects a phase difference between the internal frame synchronization signal and the external frame synchronization signal;
Based on the number of clocks of the clock signal generated in the time corresponding to the phase difference, the frequency dividing ratio of the variable frequency dividing unit is varied, and one line included in each line constituting one frame. A control unit that adjusts the scanning time of each line by varying the period of the reproduction clock signal;
A frame synchronization apparatus in an imaging apparatus, comprising: The control unit outputs a clock position designation signal that designates a clock position to be adjusted in each line constituting one frame based on the number of clocks of the clock signal generated in a time corresponding to the phase difference. ,
The variable frequency dividing unit may change the frequency dividing ratio to be small or large when the clock position in each line in one frame based on the reproduced clock signal coincides with the clock position of the clock position designation signal. Controlled to adjust the scanning time of each line,
The frame synchronization apparatus in the imaging device according to claim 3. The controller is
Counting the clock signal generated at a time corresponding to the phase difference, obtaining a quotient and a remainder divided by the number of lines constituting one frame, and based on the obtained quotient and remainder, the variable frequency dividing unit Output the clock position in each line in one frame in which the frequency division ratio is variable to the variable frequency divider.
The frame synchronization apparatus in the imaging device according to claim 4.

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