JP2008300956A - Receiver input circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver input circuit capable of obtaining an excellent SN ratio without executing impedance matching adjustment by arranging a semiconductor buffer circuit 3 between an antenna radiation circuit and a frequency selecting circuit 4. <P>SOLUTION: The receiver circuit is provided with an antenna input terminal 1 allowing an antenna power feeding line 7 to be connected thereto, an emitter follower transistor circuit 3 having an input end connected to the antenna input terminal 1 via a coupling capacitor 2, a frequency selecting circuit 4 connected to an output end of the emitter follower transistor circuit 3, and a high-frequency amplifier stage 5 receiving a frequency selecting output signal of the frequency selecting circuit 4. In the receiver input circuit, the antenna power feeding line 7 having a wavelength extremely shorter than the wavelength of a reception signal induced in the antenna 6 is connected to the antenna input terminal 1, and the semiconductor buffer circuit 3 separates electrical connection between the antenna radiation circuit and the frequency selecting circuit 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a receiver input circuit, and in particular, between an antenna radiation circuit and a frequency selection circuit when the length of an antenna feed line connected to an antenna input terminal of the receiver is remarkably shorter than a reception signal wavelength. The present invention relates to a receiver input circuit in which a semiconductor buffer circuit is connected to the antenna and the electrical coupling between the antenna radiation circuit and the frequency selection circuit is isolated to improve the SN ratio of the receiver.

  Generally, a receiver input circuit is composed of a circuit comprising an impedance matching circuit and a frequency selection circuit arranged and connected between an antenna input terminal and a high-frequency input stage. Impedance matching with the selection circuit is performed, and a desired reception frequency signal in the reception signal is selected by the frequency selection circuit. In this case, the impedance matching circuit is usually composed of a circuit including a variable capacitance element, and the frequency selection circuit is often composed of a parallel tuning circuit in which an inductor element with an intermediate tap and a variable capacitance element are connected in parallel. .

  FIG. 4 is a circuit diagram showing a typical configuration example of such a known receiver input circuit.

As shown in FIG. 4, the receiver input circuit, connected in parallel to the antenna input terminal 11, an impedance matching circuit 12 consisting of a variable capacitance element 12 _{1, 1} and with intermediate tap inductor element 13 and the variable capacitance element 13 ₂ A high-frequency amplifier stage 14 including an input coupling capacitor 14 ₁ , a base bias resistor 14 _2, and an amplifying transistor 14 ₃ is connected to the receiver input circuit. A reception antenna 15 is connected to the antenna input terminal 11 through an antenna feed line 16. In this case, the variable capacitance element 12 ₁ constituting the impedance matching circuit 12 is connected between the antenna terminal 11 and the intermediate tap of the inductor element 13 ₁ . The parallel tuning circuit 13 has a hot-side (non-grounded) circuit end connected to the input end of the high-frequency amplification stage 14 and a cold-side (grounded) circuit end connected to the ground point.

  The receiver input circuit configured as described above operates as follows.

When the reception signal received by the reception antenna 15 is supplied to the impedance matching circuit 12 through the antenna input terminal 11, the reception signal is supplied to the parallel tuning circuit 13 through the intermediate taps of the variable capacitance element 12 ₁ and the inductor element 13 _1. Then, the parallel tuning circuit 13 selects a reception signal having a required frequency from among the reception signals, and the selected reception signal is supplied to the high frequency amplification stage 14. At this time, to achieve the impedance matching with the antenna radiation circuit connected to the antenna terminal 11 and the parallel tuning circuit 13 by appropriately adjusting the capacitance of the variable capacitor 12 _1, also the variable capacitance element of the parallel tuning circuit 13 By appropriately adjusting the capacitance value of 13 _2, the parallel tuning circuit 13 selects a received signal having a required frequency, and the selected received signal having the required frequency is supplied to the high frequency amplification stage 14.

By the way, a receiver having this type of receiver input circuit has a noise figure F of the receiver as described in “Electronic Information Communication Handbook”, edited by the Institute of Electronics, Information and Communication Engineers, published by Ohmsha, 1998, page 2398, etc. If

It is represented by

  In this equation (1), Ro represents the termination impedance of the receiver input circuit. When the receiver input circuit is terminated by the parallel tuning circuit 13, the termination impedance is the resonance impedance of the parallel tuning circuit 13 and the high frequency amplification. It is represented by the parallel connection impedance with the input impedance of stage 14. Rs represents the impedance excluding the termination impedance Ro when viewing the direction of the antenna input terminal 11 from the input end of the high frequency amplification stage 14, that is, the radiation impedance of the antenna circuit. Further, Rn represents an equivalent noise resistance expressed by converting the noise of all stages connected to the high frequency amplification stage 14 including the high frequency amplification stage 14 into the input terminal of the high frequency amplification stage 14.

In order to make the noise figure F of the receiver input circuit represented by the equation (1) as small as possible, a transistor having a low equivalent noise resistance is used as the amplifying transistor 14 ₃ constituting the high-frequency amplifier stage 14, and the like. The equivalent noise resistance Rn is lowered by increasing the amplification factor of the high-frequency amplifier including the amplifying transistor 14 _{3 and the} like, and at the same time, the termination impedance Ro representing the resonance impedance of the parallel tuning circuit 14 may be increased. The reason for this is clear from the following description. That is, in this receiver input circuit, if the radiation impedance Rs of the antenna radiation circuit or the like and the resonance impedance Ro of the parallel tuning circuit 14 are in an impedance matching state, the condition of Rs = Ro is satisfied, and the expression (1) is

It is represented by

  In this equation (2), if the equivalent noise resistance Rn is made small and the input impedance Rs is made large, the noise figure F can be made small, and the input impedance Rs and If the condition of Rs >> Rn is satisfied with the equivalent noise resistance Rn, the noise figure F becomes a value asymptotic to 2.

  By the way, in an actual receiver input circuit, it is not always easy to obtain a configuration that satisfies such a condition that Rs >> Rn. The reason is that when the receiver receives the specific frequency signal in the received signal, the receiver's noise figure F can be set to a value approximate to 2, even if the receiver's received signal is specified. When the frequency signal is selected and changed to another frequency signal, the impedance matching adjustment between the antenna radiation circuit and the parallel tuning circuit 14 and the tuning frequency adjustment of the parallel tuning circuit are independent each time the selection is changed. This is because, as a result, adjustment work for sequentially bringing the noise figure F closer to 2 is necessary by alternately adjusting the impedance matching and the tuning frequency.

In this way, the known receiver input circuit can adjust the impedance matching and the tuning frequency each time the tuning frequency of the parallel tuning circuit is changed to reduce the noise figure F of the receiver. Must be performed alternately, and these realistic adjustments cannot be performed by simple adjustment work.
No patent literature to use

  The present invention has been made in view of such a technical background. The object of the present invention is to provide a semiconductor buffer circuit between the antenna radiation circuit and the frequency selection circuit, so that the impedance matching adjustment is not performed. It is an object of the present invention to provide a receiver input circuit capable of obtaining a high S / N ratio.

  To achieve the above object, a receiver input circuit according to the present invention includes an antenna input terminal to which an antenna feed line is connected, a semiconductor buffer circuit having an input terminal connected to the antenna input terminal through a coupling capacitor, and a semiconductor buffer circuit A frequency selection circuit coupled to the output terminal of the antenna and a high-frequency amplifier stage to which a frequency selection output signal of the frequency selection circuit is supplied, and the antenna input terminal has an extremely short antenna supply compared to the reception signal wavelength induced in the antenna. An electric wire is connected, and a configuration means is provided in which the electrical coupling between the antenna radiation circuit section and the frequency selection circuit section is isolated by a semiconductor buffer circuit.

  In this case, one specific circuit of the semiconductor buffer circuit in the configuration means is an emitter-follower transistor circuit, whose input terminal is the base of the transistor and whose output terminal is the emitter of the transistor.

  Another specific circuit of the semiconductor buffer circuit in the configuration means is a source follower transistor circuit, the input terminal of which is the gate of the transistor and the output terminal of which is the source of the transistor.

  As described above in detail, the present invention is used when directly receiving a received signal using an antenna such as a whip antenna or when the length of the antenna feed line is very short compared to the received signal wavelength. In order to adjust the receiver input circuit, it is only necessary to change the tuning frequency of the parallel tuning circuit, and there is no need to perform impedance matching adjustment each time the setting is changed. Therefore, the adjustment of the receiver input circuit can be simplified, and the use of the semiconductor buffer circuit eliminates the need for the termination impedance of the antenna radiation circuit, greatly reducing the attenuation of the received signal voltage in the receiver input circuit. The signal / noise ratio (S / N) at the receiver can be improved by at least about 5 dB.

  Furthermore, by using the receiver input circuit according to the present invention, as an incidental effect, when the antenna circuit direction is viewed from the frequency converter, a semiconductor buffer circuit is connected in the middle, and the output impedance of the semiconductor buffer circuit Shows a low output impedance characteristic of about several ohms, so that the local output signal leaking from the frequency converter in the direction of the antenna circuit is sufficiently suppressed by this low output impedance, and the leakage component in the direction of the antenna circuit is sufficiently attenuated. As a result, radiation propagation from the antenna to the outside can be sufficiently suppressed.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing one embodiment of a receiver input circuit according to the present invention.

As shown in FIG. 1, 1 is an antenna input terminal, 2 is a capacitive element for coupling, 3 is a semiconductor buffer circuit, and in this example, an emitter follower transistor circuit, 4 is a tuning circuit, and these components constitute a receiver. An input circuit is configured. In addition, 5 is a high-frequency amplification stage following the receiver input circuit, and 6 and 7 are a reception antenna and an antenna feed line externally connected to the antenna input terminal 1. In this case, the emitter follower transistor circuit 3 includes a base bias resistor 3 ₁ , an emitter follower connection transistor 3 _2, and an emitter load resistor 3 ₃ , and the tuning circuit 4 includes a tuning inductor element 4 ₁ and a tuning variable capacitance element 4. _{It consists of two} . High-frequency amplifier stage 5 includes a coupling capacitance element 5 ₁ and the base bias resistor 5 ₂ and the amplifying transistor 5 _3. The antenna 6 is a whip antenna, and its signal output end is connected to the antenna input terminal 1 through the antenna feed line 7. In this case, the antenna feed line 7 has a length that is extremely shorter than the reception signal wavelength induced in the antenna 6.

The coupling capacitive element 2 has an input terminal connected to the antenna input terminal 1 and an output terminal connected to the base of the emitter follower connection transistor 3 ₂ . Emitter-follower connected transistors 3 _2, the base is connected to the power supply terminal Vcc through the base bias resistor 5 _2, a collector connected directly to the power supply terminal Vcc, an emitter is connected to ground through an emitter load resistor 3 _3. The tuning inductor element 4 ₁ has one end connected to the emitter of emitter-follower connected transistors 3 _2, and the other end is connected to the input terminals of the high frequency amplifier stage 5. Tuning variable capacitive element 4 ₂ has one end connected to the input terminals of the high frequency amplifier stage 5 and the other end connected to ground. Coupling capacitance element 5 ₁ has one end connected to the input terminals of the high frequency amplifier stage 5 and the other end connected to the base of the amplifying transistor 5 _3. Amplifying transistor 5 _3, and a base connected to the base bias resistor 5 _2.

  The receiver input circuit according to this embodiment configured as described above operates as follows.

When a reception signal received by the reception antenna 6 is applied to the antenna input terminal 1, the reception signal is supplied to the emitter follower transistor circuit 3 through the coupling capacitive element 2. The emitter follower transistor circuit 3 is supplied with the received signal at a high input impedance, output from the emitter of the emitter-follower connected transistors 3 ₃ to the tuning circuit 4 in the low output impedance state. Tuning circuit 4, those selected received signal of the required frequency by adjustment of the tuning variable capacitive element 4 _2, the received signal selected by the tuned circuit 4 is supplied to a succeeding radio frequency amplifier stage 5.

In this case, the emitter follower connection transistor 3 ₂ in the emitter follower transistor circuit 3 operates as a semiconductor buffer circuit, and its input impedance has an extremely high impedance compared to the impedance of the antenna radiation circuit. It becomes possible to operate the antenna input side in the circuit in an endless (open) state. At this time, the reception signal voltage induced in the reception antenna 6 is directly supplied to the base of the emitter follower connection transistor 3 ₂ that is not terminated by the impedance matching load through the antenna input terminal 1 and the coupling capacitive element 2. not the signal voltage is reduced by connecting the impedance matching load to the size of 1/2, it is derived from the emitter-follower connected transistors 3 _second emitter while maintaining intact the voltage is applied to the tuning circuit 4.

  With such a configuration, the received signal voltage induced in the receiving antenna 6 can be taken out of the tuning circuit 4 with the voltage value as it is, whereas the antenna radiation circuit of the conventional receiver input circuit is used. When terminated with an impedance equal to the impedance, the received signal voltage at the terminal end is ½ of the induced received signal voltage compared to the case of no termination. In this case, since the combined impedance value (resistance value) is ½, the noise voltage at the end portion is ½ in power and 1 / √2 in voltage. Therefore, the signal-to-noise voltage ratio of the non-terminated receiver input circuit of the present invention is 3 dB better than the terminated type of the conventional receiver input circuit. In addition, as will be described later, the signal-to-noise voltage ratio of the entire receiver gradually approaches 6 dB as Rn increases.

  As is clear from the above description, the receiver input circuit of the present invention cannot use the noise power, and therefore can use a noise figure that is a conventional parameter when comparing the signal-to-noise ratio. Instead, the signal-to-noise voltage ratio is used.

  Next, FIGS. 2A and 2B are circuit diagrams showing an equivalent circuit of the receiver input circuit shown in FIG.

In FIG. 2A, e ₀ is the antenna induced voltage, Rs is the radiation impedance of the antenna circuit, the circuit portion indicated by the dotted frame EF is the emitter follower circuit, n · ea is the output drive voltage of the emitter follower circuit EF, Ro Is the resonance impedance of the parallel tuning circuit 4, and Rn is an equivalent noise resistance when all the noise generated from all subsequent stages including the high frequency amplification stage 4 is generated from this resistor Rn of the high frequency amplification stage 4. In this case, the parallel tuning circuit 4 boosts and outputs the input drive voltage n · ea by Q times, and the boost ratio at this time is generally represented by n. When this voltage gain is expressed in the form of being transferred to the emitter follower circuit EF, the output drive voltage of the emitter follower circuit EF is n · ea.

  Further, when the equivalent circuit of FIG. 2A is expressed in a simplified form, it becomes as shown in FIG. 2B, and the emitter follower circuit EF and its pre-stage circuit are collectively expressed as an output drive voltage n · ea. It is a representation.

  Here, FIGS. 5A and 5B are circuit diagrams for comparison with FIGS. 2A and 2B and showing an equivalent circuit of a conventional receiver input circuit.

As shown in FIG. 5A, the resonance impedance of the tuning circuit alone is Ro, and the impedance Ro and the radiation impedance Rs of the antenna circuit are impedance matched by an ideal transformer having a winding ratio of 1: n. if that have a relation of n ² Rs = Ro.

  Further, as shown in FIG. 5B, the antenna induced voltage ea is expressed by n · ea when converted to the secondary side of the tuning circuit, and the radiation impedance Rs is also applied to the secondary side of the tuning circuit. When converted, it is expressed as n · Rs.

  By performing the above operation, the signal-to-noise voltage ratio (SN voltage ratio) between the receiver input circuit of the present invention and the conventional receiver input circuit is compared between FIG. 2 (b) and FIG. 4 (b). The signal-to-noise voltage ratio (SN voltage ratio) of each receiver input circuit is as follows.

The SN voltage ratio of the receiver input circuit of the present invention shown in FIG.

The SN voltage ratio of the conventional receiver input circuit shown in FIG.

Therefore, if the ratio of the result of Formula (3) and the result of Formula (4) is obtained and the ratio is the SN improvement degree in the present invention, the SN improvement degree is

It becomes.

Here, the SN improvement is obtained when the radiation impedance Rs of the antenna circuit is (75/2) ohms, the value of the step-up ratio n is changed in three ways, and the equivalent noise resistance Rn is changed in five ways. The values shown in Table 1 could be obtained.

  In this case, the equivalent noise resistance Rn is usually a value in the range of several hundred ohms to several tens of kilohms. In particular, the SN improvement can be achieved. In particular, even when the boost ratio n is 1, that is, when the tuning circuit is not used (including the case of the lumped band-pass filter), the SN improvement of 5 dB or more is observed. In general, the SN improvement degree of about 5 dB can be expected even when viewed comprehensively.

  The above-described embodiment shows an example in which the emitter follower transistor circuit 3 is used as a semiconductor buffer circuit. However, even when the source follower transistor circuit 8 is used as a semiconductor buffer circuit, the emitter follower transistor circuit 3 is used. A function similar to that when the transistor circuit 3 is used can be exhibited.

  FIG. 3 is a circuit diagram showing another embodiment of a receiver input circuit according to the present invention, and shows an example in which a source follower transistor circuit 8 is used as a semiconductor buffer circuit.

As shown in FIG. 3, 8 is an example using a semiconductor buffer circuit, in this example, a source follower transistor circuit. This source follower transistor circuit 8 includes gate bias resistors 8 ₁ and 8 ₂ and a source follower connection transistor. 8 ₃ and the source load resistor 8 _4, and their interconnection state is in accordance with the interconnection state in the emitter follower transistor circuit 3.

  The configuration of each circuit other than the configuration of the semiconductor buffer circuit 8 is the same as the configuration of the corresponding circuit of the receiver input circuit illustrated in FIG. 1, and in FIG. 3, the receiver illustrated in FIG. The same components as those of the input circuit are denoted by the same reference numerals, and description of those components is omitted.

  The operation of the receiver input circuit according to the other embodiment and the effect obtained thereby are the same as the operation of the receiver input circuit according to the embodiment illustrated in FIG. 1 and the effect obtained thereby. Therefore, the description of the operation and the effects obtained thereby will be omitted here.

1 is a circuit diagram showing a circuit configuration of an embodiment of a receiver input circuit according to the present invention. FIG. 2 is a circuit diagram illustrating an equivalent circuit of the receiver input circuit illustrated in FIG. 1. The other embodiment of the receiver input circuit by this invention is shown, and it is a circuit diagram which shows the circuit structure. It is a circuit diagram which shows the typical structural example of a known receiver input circuit. It is a circuit diagram which shows the equivalent circuit of a known receiver input circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Antenna input terminal 2 Capacitance element 3 Coupling element 3 The example which used the emitter follower transistor circuit in the semiconductor buffer circuit 3 ₁ Base bias resistance 3 ₂ Emitter follower connection transistor 3 ₃ Emitter load resistance 4 Tuning circuit 5 High frequency amplification stage 6 Reception antenna 7 Antenna feed line 8 Example using source follower transistor circuit in semiconductor buffer circuit 8 ₁ , 8 ₂ Gate bias resistance 8 ₃ Source follower connection transistor 8 ₄ Source load resistance

Claims (4)

An antenna input terminal to which an antenna feed line is connected, a semiconductor buffer circuit having an input terminal connected to the antenna input terminal through a coupling capacitor, a frequency selection circuit coupled to an output terminal of the semiconductor buffer circuit, and the frequency selection A high-frequency amplification stage to which a frequency selection output signal of the circuit is supplied, an antenna feed line that is extremely shorter than a reception signal wavelength induced in the antenna is connected to the antenna input terminal, and an antenna radiation circuit is provided by the semiconductor buffer circuit A receiver input circuit characterized in that the electrical coupling between the circuit unit and the frequency selection circuit unit is isolated. 2. The receiver input circuit according to claim 1, wherein the semiconductor buffer circuit is an emitter follower transistor circuit, and an input terminal thereof is a base of a transistor and an output terminal thereof is an emitter of the transistor. 2. The receiver input circuit according to claim 1, wherein the semiconductor buffer circuit is a source follower transistor circuit, and an input terminal thereof is a gate of the transistor and an output terminal thereof is a source of the transistor. The antenna connected to the antenna input terminal is a whip antenna, and is disposed in the vicinity of the antenna input terminal and connected to the antenna input terminal through an extremely short antenna feed line. The receiver input circuit as described in any one of thru | or 3.

Images