JP2008299355A - Driving device of liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data driver for a liquid crystal display device which solves problem points arising by performance of high-frequency operations and lowers a main driving frequency. <P>SOLUTION: The data driver for a liquid crystal display device is composed of a single integrated circuit comprising: an m-bit (m: an integer) register circuit 21 that outputs a latch clock signal to receive a start signal corresponding to a first clock signal; data latch circuits 22, 23 that receive all video signals each having n-bit (n: an integer) data at the same time, and latch and output three kinds of video signals of at least two sets corresponding to a source video signal; a line latch circuit 25 that stores and outputs a video signal based on a load signal of a third signal generating circuit and latches the video signals of the data latch circuit corresponding to the latch clock signal of the register; a D/A converting circuit 27 that converts the video signal of the line latch into an analog signal; and a data output circuit 29 that makes the D/A converting circuit output the analog signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a drive device for a liquid crystal display device, and more particularly to a data driver for a liquid crystal display device.

  As shown in FIG. 1, a general active matrix liquid crystal display device includes a gate line (G1 to Gn) and a data line (D1 to Dn), a thin film transistor for switching each pixel, a pixel electrode, , A liquid crystal panel 1 composed of liquid crystal buried between the two upper and lower plates, A gate driver 2 for sequentially applying drive signals to the gate lines (G1 to Gn) of the liquid crystal panel 1 and a data driver 3 for applying video data to the data lines (D1 to Dn) of the liquid crystal panel 1 are provided. .

  In the general liquid crystal display device configured as described above, recently, the liquid crystal panel 1 is directed to increase in size and resolution. Thus, as the size and resolution are increased, the drive frequency of each driver 2 and 3 increases to drive the liquid crystal display device. However, the development of a driver IC that can be directly driven at such a high frequency has been developed. difficult. Even if a direct driver IC is developed, direct drive is impossible due to the problem of high frequency EMI.

  Therefore, as shown in FIG. 2, data drivers 3a and 3b are formed on both sides of the liquid crystal panel 1 separately into odd lines and even lines, and the drive frequency is halved. However, in the liquid crystal display device as shown in FIG. 2, since the drivers are formed on both sides, the area occupied by the liquid crystal panel that actually displays the image in the entire liquid crystal display device becomes relatively small. There was a limit to getting.

  The data driver 3 of FIG. 1 of the conventional liquid crystal display device described above will be described with reference to the accompanying drawings.

  FIG. 3 is a configuration block diagram of a data driver of a conventional liquid crystal display device.

  A conventional data driver of a liquid crystal display device includes an m-bit shift register 11 that outputs a latch clock by shifting a source start pulse (SSP) by a source pulse clock (SCL), and three types of display data by a source clock (SCL). Data latch unit 12 that latches (DA (n), DB (n), DC (n)) and outputs it, and polarity is switched for each horizontal section by an external POL signal for inversion. A line conversion logic 14 and all display data of one horizontal line output from the data latch unit 12 according to the latch clock output from the shift register 11 are loaded with an external load signal and the line. A 3 mxn-bit 2-line latch unit 13 that latches and stores line by line according to the output of the conversion logic 14; A D / A converter that selects and outputs one of 2n levels formed by an external reference voltage in order to convert the data output from the line latch unit 12 into an analog signal applied to the liquid crystal. 15 and a data output circuit 16 that amplifies the signal output from the D / A converter 15 to a stable voltage with a sufficient driving capability and a small output voltage deviation and applies the amplified voltage to the liquid crystal.

  The operation of the conventional data driver configured as described above will be described.

  FIG. 4 is an operation timing chart of the conventional data driver.

  First, the shift register 11 inputs a source clock (SCL) and a source start pulse (SSP) and sequentially inputs m latch clocks (SR01, SR02, SR03,..., SR0m) (m = 64). Output to the latch unit 13. The source clock (SCL) is a clock signal having a frequency of about 65 MHz in XGA.

  Then, the data latch unit 12 latches the three types of n-bit display data (DA (n), DB (n), DC (n)) at the falling edge of the source clock (SCL) to the line latch unit 13. Output. Therefore, the line latch unit 13 uses the latch clock (SR01, SR02, SR03,..., SR0m) output from the shift register 11 to receive the n-bit display data latched at the falling edge of the source clock. The first line latch unit 13a latches. One line data is stored in the second line latch unit 13b at a time by an external load signal after storing display data of one horizontal line. At the same time, the next line data is latched in the first line latch unit by the latch clock (SR01, SR02, SR03,..., SR0m) output from the shift register 11. Such an operation is repeated.

  Thus, the line data stored by the line latch unit 13 is output to the D / A converter 15.

  The D / A converter 15 selects one voltage corresponding to the line data input from the line latch unit 13 among the 2n levels formed by the external reference voltage (VREF) using internal data. Output. At this time, the line conversion logic 14 changes the polarity for each line by an external POL signal to facilitate inversion.

  The analog signal selected and output from the D / A converter 15 is applied to the liquid crystal by the data output circuit 16 as a stable voltage with a sufficient driving capability and a small output voltage deviation, and is displayed.

  However, such a conventional data driver has the following problems.

  According to the trend of large screen and high resolution of recent liquid crystal display devices, the biggest challenge in applications such as liquid crystal notebook personal computers and monitors is the problem of high operating frequency depending on resolution (XGA is 65 MHz, EWS is 107 MHz) Since the operating frequency of the existing data driver IC is 55 MHz when driven at 5 V (40 MHz when driven at 3.3 V), direct driving is impossible. Even if a driver IC that can be directly driven is developed, it cannot be directly driven due to the problem of high frequency EMI.

  On the other hand, a line memory can be provided outside the conventional data driver as described above, and the frequency can be lowered to ½ through data two-division driving or IC-specific division driving. In this case, however, the use of line memory increases the cost and weight of the product. Therefore, power consumption and volume also increase.

  The present invention is to solve the above-described problems, and an object of the present invention is to provide a data driver for a liquid crystal display device that solves problems caused by operating at a high frequency and reduces the main drive frequency. There is to do.

  In order to achieve such an object, the driving device of the liquid crystal display device of the present invention includes a first signal generating circuit for outputting a start signal to the outside; a second signal generating circuit for outputting a first clock signal to the outside; A third signal generating circuit for outputting a load signal to the outside; generating means for outputting a source video signal having a frequency to the outside; and a latch clock signal for outputting a start signal corresponding to the first clock signal. M (integer) -bit register circuit for receiving and all the video signals respectively having n (integer) -bit data are received simultaneously, and at least two sets of three kinds of video signals corresponding to the source video signal are latched A data latch circuit for outputting and storing and outputting a video signal based on a load signal of the third signal generating circuit, and a latch clock signal for the register A corresponding line latch circuit for latching the video signal of the data latch circuit, a D / A conversion circuit for converting the video signal of the line latch into an analog signal, and a data output circuit for outputting an analog signal from the D / A conversion circuit; And the frequency of the first clock signal is reduced by the number of sets of three types of video signals compared to the frequency of the source video signal. .

  The liquid crystal display device driving device of the present invention includes a first signal generating circuit for outputting a source start signal to the outside; a second signal generating circuit for outputting a first clock signal to the outside; and a load signal for outputting to the outside. A third signal generating circuit for outputting; a fourth signal generating circuit for outputting a polarity signal to the outside; and a latch clock signal for outputting the source start signal corresponding to the first clock signal. -Bit register circuit, each video signal has n (integer)-bit data, and each set of video signals simultaneously receives all video signals to display one pixel of LCD, at least two sets A data latch circuit that latches and outputs the three types of video signals, and stores and outputs the video signal based on the load signal of the third signal generation circuit, and latches the register A 3m × n line latch circuit that latches the video signal of the data latch circuit corresponding to the lock signal, a polarity inversion circuit that inverts the polarity of the video signal from the data latch, and a D that converts the video signal of the line latch into an analog signal A single integrated circuit comprising: a / A conversion circuit; and a data output circuit for outputting an analog signal from the D / A conversion circuit; and the drive frequency of the drive device according to the number of sets of the three types of video signals Is reduced.

  The liquid crystal display device driving device of the present invention includes a first signal generating circuit for outputting a source start signal to the outside; a second signal generating circuit for outputting a first clock signal to the outside; and a load signal for outputting to the outside. A third signal generating circuit for outputting; a fourth signal generating circuit for outputting a polarity signal to the outside; a register circuit for shifting a source start signal corresponding to the first clock signal and outputting a sampling clock signal; and an LCD pixel A data sampling circuit that simultaneously receives and outputs at least two sets of three types of video signals, and stores and outputs the video signals based on the load signal of the third signal generation circuit. The video signal of the data latch corresponding to the latch clock signal of the shift register is latched, and the third signal generation is performed. 3m × n line latch circuit for storing and outputting the video signal corresponding to the load signal of the circuit, a polarity inversion circuit for inverting the polarity of the video signal from the data latch, and converting the video signal of the latch circuit into an analog signal And a single integrated circuit including a data output circuit for outputting an analog signal from the D / A conversion circuit, and driving the driving device according to the number of the three kinds of video signals. The frequency is reduced.

  The liquid crystal display driving apparatus of the present invention as described above has the following effects.

  That is, the drive device of the present invention can be made with a module that is advantageous for high frequency EMI, etc. by eliminating the external memory and circuit by lowering the main drive frequency to 1/2 or 1/3 by the driver itself, In both cases, effects such as cost reduction, reduction in product size and volume, and reduction in power consumption can be obtained.

  In addition, XGA and EWS resolutions can be realized in a single or double structure for a notebook personal computer and monitor.

Embodiment 1 of the Invention
Embodiment 1 of the present invention will be described below with reference to the drawings.

  FIG. 5 shows the IC structure according to the first embodiment in which the data frequency applied to the odd and even portions of the data line is separated and processed in parallel to reduce the operating frequency of the data driver by half. It is the waveform of the operation. In FIG. 5, a first signal generating circuit for outputting a start signal (SSP) to the outside, a second signal generating circuit for outputting a first clock signal to the outside, and a first signal for outputting a load signal (LOAD) to the outside. 3 signal generating circuit, generating means for outputting a source video signal having a frequency to the outside, a fourth signal generating circuit for outputting a signal having a polarity to the outside, and inverting the polarity of the video signal from the data latch The polarity inversion circuit to be made is not shown. The three types of video signals AC are, for example, R, G, and B values of each pixel, respectively.

  The m-bit shift register 21 is supplied with a source clock (SCL) of ½ frequency, and latch pulses (SR01, SR02,... in FIG. 7) are generated by the source clock and the source start pulse (SSP). appear. Further, the data separated into odd and even numbers outside the driver IC is latched by the first data latch unit 22 and the second data latch unit 23, respectively. The three types of n-bit odd data and the even data latched by the first and second latch units 22 and 23 are the first latch 25a of the odd line of 3m × n bits by the latch pulse of the shift register 27. The latches are latched in the first latches 26a of the even lines.

  The display data of one horizontal line stored in the first latch lines 25a and 26a is stored once in the odd and even second line latches 25b and 26b at one load signal, and the data in the next line is the shift register. Are sequentially latched in the first line latches 25a and 26a. The line data stored in the odd-numbered and even-numbered second line latches 25b and 26b select the voltage among the two reference voltages by the respective D / A converters 27 and 28.

  At this time, the line conversion logic 24 makes the inversion easy by switching the polarity of the voltage. The selected reference voltage is applied to the liquid crystal through the data output circuits 29 and 30 as a stable voltage with a sufficient drive capability and a small output voltage deviation.

  On the other hand, in the above embodiment, the data is stored in the first and second latch units 22 and 23 in the order in which the data arrives, and the output terminals of the two data output circuits 29 and 30 are alternately arranged three by three. There is also a method of connecting to the data line of the liquid crystal panel.

  Embodiment 2 of the Invention FIG. 6 is a second embodiment of the present invention.

  In the first embodiment, the data is separated into the odd number and the even number, but in this embodiment, three data latch units 32, 33, and 34 are provided, and the data of the first data line is stored in the first latch unit 32. The data of the second data line is applied to the second latch unit 33, the data of the third data line is applied to the third latch unit 34, and the data of the fourth data line, the fifth data line, and the sixth data line are again applied to the first, The data is separated by applying each to the second and third latch sections.

  Further, by applying a frequency of 1/3 when the parallel driving is not performed to the shift register 31, the operating frequency of the data driver IC can be reduced to 1/3.

  Other operations are the same as those in the first embodiment.

  In the first and second embodiments of the present invention, the data driver is attached only to one side of the liquid crystal panel. However, if such a driver is formed in a double structure as shown in FIG. It can be reduced by a factor of two.

1 is a block diagram illustrating a general liquid crystal display device. The block diagram of a liquid crystal display device having a general double driver. FIG. 6 is a configuration block diagram of a data driver of a conventional liquid crystal display device. FIG. 4 is an operation timing chart of the driver of FIG. 3. 1 is a configuration block diagram of a data driver of a liquid crystal display device according to a first embodiment of the present invention. The block diagram of the configuration of the data driver of the liquid crystal display device according to the second embodiment of the present invention. FIG. 3 is an operation timing chart of the driver according to the first embodiment of the present invention.

Explanation of symbols

21, 31 Shift register 22, 23, 32, 33, 34 Data latch 24, 35 Line conversion logic 25, 26, 36, 37, 38 Line latch 25a, 25b, 26a, 26b, 36a, 36b, 37a, 37b , 38a, 38b Line memories 27, 28, 39, 40, 41 D / A converters 29, 30, 42, 43, 44 Data output circuit

Claims (2)

In a liquid crystal display device comprising an active matrix type liquid crystal panel including 2m lines and a liquid crystal panel driving device arranged on one side of the liquid crystal panel, the driving device comprises:

In response to a clock signal (SCL) having a half frequency of the source clock pulse and a start pulse (SSP), m latch clock pulses (SR01, SR02,...) Shifted by the clock signal (SCL) interval. ) For generating a shift register (21),

A latch unit (22, 23) for temporarily holding each of two pieces of pixel data of odd-numbered line pixel data and even-numbered line pixel data that are continuous in a series of digital pixel data;

The odd line pixel data latched by the latch unit (22, 23) is read in synchronization with each of the m latch clock pulses (SR01, SR02,...) Output from the shift register (21). 1 odd line latch, and a first even line latch that reads even line pixel data at the same time, and holds m odd line pixel data and m even line pixel data for one horizontal line. Odd line latch and even line latch part (25a, 26a),

A second latch that latches 2m pixel data for one horizontal line held in the first odd-numbered line latch and even-numbered line latch units (25a, 26a) at a time in response to a load signal every horizontal scanning period. Odd line latch and even line latch (25b, 26b) and

Digital pixel data held in the second odd line latch and even line latch units (25b, 26b) are simultaneously converted into analog signals, and m odd lines (Y ₁ , Y ₃ ) of the liquid crystal panel are converted. to Y ₃₈₃₎ and those of m even line _{(Y 2,} Y _{4 ~Y 384} and has a D / a converter provided in) (27), a liquid crystal display device.
In a liquid crystal display device comprising an active matrix type liquid crystal panel including 3m lines and a liquid crystal panel driving device disposed on one side of the liquid crystal panel, the driving device comprises:

A shift register (31) for generating m latch clock pulses shifted by the clock signal interval in response to a clock signal having a 1/3 frequency of the source clock pulse and a start pulse;

Latch section (32, 33, 34) for temporarily holding each of three line pixel data of i-th, i + 1-th and i + 2-th (i = 1 to m) consecutive in a series of digital pixel data

A first i-th line latch that reads the i-th line pixel data latched by the latch unit in synchronization with each of the m latch clock pulses output from the shift register, and simultaneously reads the i + 1-th line pixel data. 1 i + 1-th line latch, and i-second line latch for reading i + 2-th line pixel data at the same time. The m-th i-th line pixel data, m i + 1-th line pixel data and m A first i-th line latch, i + 1-th line latch and i + 2-th line latch (36a, 37a, 38a) for holding i + 2nd line pixel data,

A second i-th line latch that latches 3m pixel data for one horizontal line held in the i-th, i + 1-th and i + 2-th line latches in response to a load signal every horizontal scanning period. , I + 1-th line latch and i + 2-th line latch unit (36b, 37b, 38b), and

Digital pixel data held in the second i-th line latch, i + 1-th line latch, and i + 2-th line latch unit are simultaneously converted into analog signals, and applied to 3m lines of the liquid crystal panel. A liquid crystal display device comprising an A converter (39, 40, 41).

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