JP2008298630A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, having a test pad control circuit for so performing a breakdown voltage that relaxes the control so that the interference due to high voltage will not occur, by checking the state of high voltage when it is selected and when it is non-selected. <P>SOLUTION: This semiconductor integrated circuit comprises a first switch transistor 10 connected to an internal high-voltage power; a second switch transistor 17 connected to a pad; a first switch control circuit 30-1 turning on the first switch transistor 10 by a control signal and relieving the voltage, applied to the transistor circuit held therein by a first detection signal indicating that the internal high-voltage power exceeds a predetermined voltage; a second switch control circuit 30-2, turning on the second switch transistor 15 by a control signal and relieving the voltage applied to the transistor circuit held therein by a second detection signal, indicating that the voltage applied to the pad exceeds a predetermined voltage; and a level detection circuit 20, generating the second detection signal when the voltage applied to the pad exceeds the predetermined voltage. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a test pad control circuit.

  In the inspection of the semiconductor integrated circuit chip, there is a mode in which an internal power supply is taken out in a test mode and a voltage test is performed. In this case, a plurality of chips are mounted on a test board or substrate and tested. For this reason, the internal power supply voltage extraction pad of each chip is connected to a common check terminal, and only the internal power supply voltage of the selected chip is sequentially extracted and tested.

By the way, when the internal voltage to be measured is a high voltage, when the internal voltage of the chip at the time of selection exceeds a predetermined level, or when the voltage of the pad of the chip at the time of non-selection exceeds a predetermined level, the high voltage Some measures need to be taken to prevent the occurrence of voltage failure. In Patent Document 1, when testing a plurality of chips mounted on a multi-chip package through a common pad, a normal voltage of a power supply voltage level is input through an external pad instead of a high voltage necessary for a test mode. There is a description that the normal voltage is boosted inside the selected chip to prevent damage to other chips due to the high voltage.
JP-A-10-190377

  The present invention has been made to solve such a problem, and its purpose is to check the high voltage state at the time of selection and non-selection and to perform withstand voltage relaxation control so as not to cause a failure due to the high voltage. An object of the present invention is to provide a semiconductor integrated circuit having a test pad control circuit.

  A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a test pad control circuit, and includes a first switch transistor connected to an internal high voltage power supply, a second switch transistor connected to a pad, a control signal The first switch that turns on the first switch transistor and relaxes the voltage applied to the held transistor circuit by the first detection signal indicating that the internal high-voltage power supply has exceeded a predetermined voltage. The control circuit and the control signal turn on the second switch transistor, and the second detection signal indicating that the voltage applied to the pad has exceeded a predetermined voltage is applied to the transistor circuit that is held. A second switch control circuit for relaxing the voltage, and a level detection circuit for generating a second detection signal when the voltage applied to the pad exceeds a predetermined voltage. When the control signal is selected, the first and second switch control circuits of the semiconductor integrated circuit turn on the first and second switch transistors, and the first switch control circuit When the high-voltage power supply exceeds a predetermined voltage, the voltage applied to the transistor circuit that is held is relaxed by the first detection signal, and the second switch control circuit is held by the second detection signal. The first and second switch control circuits of the semiconductor integrated circuit turn off the first and second switch transistors and the second The switch control circuit is characterized in that when the voltage applied to the pad exceeds a predetermined voltage, the voltage applied to the held transistor circuit is relaxed by the second detection signal. That.

  The level detection circuit of the semiconductor integrated circuit according to the present invention has an independent pad for receiving an activation signal from an external tester, and is operated by the activation signal.

  According to the semiconductor integrated circuit of the present invention, a semiconductor integrated circuit having a test pad control circuit that checks a high voltage state at the time of selection and non-selection and performs withstand voltage relaxation control so that a failure due to the high voltage does not occur can be realized. Therefore, when the test pads of a plurality of semiconductor integrated circuit chips are connected in common and the internal power supply test is continuously performed, it is possible to provide a semiconductor integrated circuit that can safely perform the test.

  Embodiments of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings. FIG. 2 is a connection diagram showing a connection configuration in a test of a semiconductor integrated circuit chip according to the present invention. In FIG. 2, a plurality of semiconductor integrated circuit chips are connected to a memory tester. The internal voltage of each chip is sequentially controlled by the test pad control circuit 100, taken out to the pad, and inspected by the memory tester. Next, the operation of the chip test pad control circuit 100 will be described.

  FIG. 1 is a block diagram showing a circuit configuration of a test pad control circuit according to the present invention. In FIG. 1, the drain of the first switch transistor 10 and the drain of the second switch transistor 15 constituting the test pad control circuit 100 are connected to each other. The source of the first switch transistor 10 is connected to the first P well 12 and the internal high voltage power supply HVNEG. The source of the second switch transistor 15 is connected to the second P well 17 and the pad 25.

  The control signal input terminal IN of the first switch control circuit 30-1 is connected to the test enable signal TESTEN, the output terminal OUT is connected to the gate of the first switch transistor 10, and the detection signal input terminal HHDET is connected to the first switch control circuit 30-1. 1 is connected to the detection signal NEGDET, and the negative voltage input terminal VNEG is connected to the internal high voltage power supply HVNEG. The control signal input terminal IN of the second switch control circuit 30-2 is connected to the test enable signal TESTEN, the output terminal OUT is connected to the gate of the second switch transistor 15, and the negative voltage input terminal VNEG is connected to the pad. 25. The negative voltage input terminal VNEG of the level detection circuit 20 is connected to the pad 25, and the detection signal output terminal DETOUT is connected to the detection signal input terminal HHDET of the second switch control circuit 30-2. The level detection circuit 20 may be a known level detection circuit.

  In the chip selection mode in which the level of the internal high voltage power supply HVNEG is monitored by a tester, the first and second switch control circuits 30-1 and 30-2 receive the high level of the test enable signal TESTEN and receive the first and second The switch transistors 10 and 15 are turned on. Thereby, the internal high-voltage power supply HVNEG is transmitted to the pad 25 and monitored by a tester. In the non-select mode, the low level of the test enable signal TESTEN is received and the first and second switch transistors 10 and 15 are turned off so that the output of another chip sharing the pad is not taken into the chip. To do. As described above, the first and second switch control circuits 30-1 and 30-2 basically serve as level shifters for surely switching the first switch transistor 10 and the second switch transistor 15 respectively. It is working.

  FIG. 3 is a circuit diagram showing the first and second switch control circuits. In FIG. 3, the sources of PMOS transistors 31 and 32 and the sources of PMOS transistors 34 and 35 are connected to the output terminal of an inverter 38, respectively. The drains of the PMOS transistors 31 and 32 are connected to the drain of the NMOS 33 and to the gate of the PMOS transistor 34. The drains of the PMOS transistors 34 and 35 are connected to the drain of the NMOS 36 and to the gate of the PMOS transistor 32 and the output terminal OUT. The gate of the NMOS 33 is connected to the gate of the PMOS transistor 32, and the source is connected to the negative voltage input terminal VNEG. The gate of the NMOS 36 is connected to the gate of the PMOS transistor 34, and the source is connected to the negative voltage input terminal VNEG.

  The output terminal of the NOR circuit 37 is connected to the gate of the PMOS transistor 35, one input terminal is connected to the detection signal input terminal HHDET, and the other input terminal is connected to the gate of the PMOS transistor 31. The input terminal of the inverter 38 is connected to the detection signal input terminal HHDET. The output terminal of the NOR circuit 39 is connected to the gate of the PMOS transistor 31, one input terminal is connected to the detection signal input terminal HHDET, and the other input terminal is connected to the output terminal of the inverter 40. The input terminal of the inverter 40 is connected to the control signal input terminal IN.

  FIG. 4 is a voltage level table showing voltages at the respective nodes of the first and second switch control circuits. In FIG. 4a, the detection signal input when the test enable signal TESTEN at the control signal input terminal IN at the time of selection is at a high level and the internal high voltage power supply HVNEG is within a certain voltage range (for example, a range of 0 to -5V). When the first detection signal NEGDET at the terminal HHDET is in the low level 2, the level of the node LSVDD and the node B at the output terminal of the inverter 38 is high, and the level of the node A is low. Therefore, the PMOS transistor 35 and the NMOS transistor 33 are turned on, and the PMOS transistor 32 is turned off, so that the node C is at a low level. Here, since the PMOS transistor 34 is turned on and the NMOS transistor 36 is turned off, the output terminal OUT outputs the high level of the node LSVDD at the output terminal of the inverter 38 and turns on the first switch transistor 10. Similarly, the second switch transistor 15 is also turned on, and the internal high voltage power supply HVNEG is transmitted to the pad 25 and monitored by a tester.

  In addition, when the test enable signal TESTEN at the control signal input terminal IN that is not selected is at a low level and the internal high voltage power supply HVNEG is within a certain voltage range, the first detection signal NEGDET at the detection signal input terminal HHDET is In the state 1 that is at the low level, the level of the node B is at the low level, and the levels of the node LSVDD and the nodes A and C at the output end of the inverter 38 are at the high level. Therefore, since the PMOS transistors 34 and 35 are turned off and the NMOS 36 is turned on, the output terminal OUT outputs the level of the internal high voltage power supply HVNEG which is the voltage of the negative voltage input terminal VNEG, and the first switch transistor 10 is turned off. . Similarly, the second switch transistor 15 is also turned off, and the voltage applied to the pad 25 is not transmitted to the inside.

  From state 2, the first detection signal NEGDET of HVDET indicating that the internal high voltage power supply HVNEG has exceeded a predetermined value (for example, −5 V or less) is at a high level (generated in the semiconductor integrated circuit) 4 When the transition is made, the levels of the node LSVDD, the node A, and the node B at the output terminal of the inverter 38 become low level. At this time, the PMOS transistor 35 and the PMOS transistor 31 are turned off, but the logic state in the state 2 is held by the latch composed of the PMOS transistor 32, the PMOS transistor 34, the NMOS transistor 33, and the NMOS transistor 36. OUT outputs the low level of the node LSVDD at the output terminal of the inverter 38 and turns on the first switch transistor 10. Similarly, the second switch transistor 15 is also turned on.

  Thus, when the internal high voltage power supply HVNEG exceeds a predetermined value, the drain voltage of the NMOS transistor 36 is at the same low level as the node LSVDD at the output terminal of the inverter 38. By this breakdown voltage relaxation control operation, the sum of the voltage exceeding the predetermined value of the internal high voltage power supply HVNEG and the voltage VDD of the node LSVDD is not applied between the source and drain of the NMOS transistor 36, and breakdown voltage breakdown Can avoid such obstacles. Similarly, troubles such as breakdown voltage breakdown can be avoided for the PMOS transistors 31 and 32.

  Next, in the second switch control circuit 30-2 in the state 1, when the voltage applied to the pad 25 exceeds a predetermined value, the level detection circuit 20 detects this, and the second detection signal PADDET is at a high level. Transition to state 3. At this time, the levels of the node LSVDD, the node A, and the node B at the output terminal of the inverter 38 are low. Further, the PMOS transistor 31 and the PMOS transistor 35 are turned off, but the logic state in the state 1 is held by the latch composed of the PMOS transistor 32, the PMOS transistor 34, the NMOS transistor 33, and the NMOS transistor 36, so that the output terminal OUT outputs a level at which the voltage applied to the pad 25 exceeds a predetermined value, and maintains the OFF state of the second switch transistor 15.

  At this time, the drain voltage of the NMOS transistor 33 transitions from a high level to a low level, like the voltage of the node LSVDD. By this breakdown voltage relaxation control operation, the sum of the voltage of the pad 25 exceeding the predetermined value and the voltage VDD of the node LSVDD is not applied between the source and drain of the NMOS transistor 33, and breakdown voltage breakdown, etc. Can avoid obstacles. Similarly, troubles such as breakdown voltage breakdown can be avoided for the PMOS transistors 34 and 35. FIG. 4 b shows the voltage level of each node in states 1 to 4 when VDD = 1.8V, GND = 0V, VNEG = −5V, and the voltage exceeding a predetermined level = −10V.

  FIG. 5 is a voltage transition diagram showing changes in each voltage when transitioning from state 2 to state 4. In FIG. 5, the high level of the test enable signal TESTEN is applied to the first switch control circuit 30-1 for chip selection. If the voltage of the internal high voltage power supply HVNEG of the semiconductor integrated circuit is within a certain voltage range, the first detection signal NEGDET generated in the semiconductor integrated circuit is at a low level. At this time, the voltage of the node LSVDD at the output terminal of the inverter 38 becomes high level, and the high-level output signal OUT1 is output from the output terminal OUT. The same operation is performed in the second switch control circuit 30-2, and a high-level output signal OUT2 is output from the output terminal OUT. As a result, the first and second switch transistors 10 and 15 are turned on, the voltage of the internal high voltage power supply HVNEG is transmitted to the pad 25 as the pad voltage NEGPAD, and the test is started.

  During the test, when the internal high voltage power supply HVNEG exceeds a predetermined value, the first detection signal NEGDET becomes high level, the level detection circuit 20 also detects the voltage of the pad 25, and the second detection signal PADDET is high level. It becomes. In response to this, the voltage of the node LSVDD at the output terminal of the inverter 38 changes from the high level to the low level, and the NMOS transistor 36 and the PMOS transistors 31 and 32 are protected by the breakdown voltage relaxation control operation. Further, low-level output signals OUT1 and OUT2 are output from the output terminal OUT, respectively, and the first and second switch transistors 10 and 15 are turned on.

  FIG. 6 is a voltage transition diagram showing changes in each voltage when transitioning from the state 1 to the state 3. In FIG. 6, the low level of the test enable signal TESTEN is applied to the first switch control circuit 30-1 for non-selection of the chip. If the voltage of the internal high voltage power supply HVNEG of the semiconductor integrated circuit is within a certain voltage range, the first detection signal NEGDET generated in the semiconductor integrated circuit is at a low level. At this time, the voltage of the node LSVDD at the output terminal of the inverter 38 becomes high level, and the low-level output signal OUT1 is output from the output terminal OUT. In the second switch control circuit 30-2, when the voltage applied to the pad 25 exceeds a predetermined value, the level detector 20 detects this, and the second detection signal PADDET becomes high level. At this time, the voltage of the node LSVDD at the output terminal of the inverter 38 becomes low level, and the signal OUT2 having the same level as NEGPAD is output from the output terminal OUT. As a result, the first and second switch transistors 10 and 15 are turned off, and the voltage applied to the pad 25 is not transmitted to the inside.

  When the internal high voltage power supply HVNEG of another chip selected at this time exceeds a predetermined value, the level detection circuit 20 detects the voltage of the pad 25, and the second detection signal PADDET becomes high level. In response to this, the voltage at the node LSVDD at the output terminal of the inverter 38 changes from the high level to the low level, and the NMOS transistor 33 and the PMOS transistors 34 and 35 are protected by the breakdown voltage relaxation control operation. Further, the output signal OUT2 having the same level as NEGPAD is output from the output terminal OUT, and the second switch transistor 15 is kept off.

  FIG. 7 is a block diagram showing a circuit configuration in which the level detection circuit of the test pad control circuit of the present invention has an independent pad for receiving an activation signal. If the level detection circuit 20 is always operated after the semiconductor integrated circuit chip is turned on, the standby current specification may not be maintained. For this reason, an independent pad 27 for activating the level detection circuit 20 when it is not selected is provided to enable individual control from the tester. FIG. 8 is a connection diagram showing a test connection configuration of a semiconductor integrated circuit chip having an independent pad for receiving an activation signal by the level detection circuit of the present invention. As a result, the non-selected chip can be controlled to activate the detection circuit 20 with the independent pad 27, and both the relaxation of the breakdown voltage of the transistor circuit and the realization of the specifications of the standby current can be achieved.

  As described above, according to the present invention, a semiconductor integrated circuit having a test pad control circuit that checks a high voltage state at the time of selection and non-selection and performs a withstand voltage relaxation control so as not to cause a failure due to a high voltage is possible. Therefore, when the test pads of a plurality of semiconductor integrated circuit chips are connected in common and the internal power supply test is continuously performed, it is possible to provide a semiconductor integrated circuit that can safely perform the test. Furthermore, by providing an independent pad, it is possible to achieve both relaxation of the breakdown voltage of the transistor circuit and realization of the specifications of the standby current.

The block diagram which shows the circuit structure of the test pad control circuit of this invention. The connection diagram which shows the connection structure of the test of the semiconductor integrated circuit chip by this invention. The circuit diagram which shows the 1st and 2nd switch control circuit. The voltage level table | surface which shows the voltage in each node of a 1st, 2nd switch control circuit. The voltage transition diagram which shows the change of each voltage when changing from the state 2 to 4. FIG. The voltage transition diagram which shows the change of each voltage when it changes from the state 1 to 3. FIG. The block diagram which shows the circuit structure of the level detection circuit which has the independent pad of this invention. FIG. 3 is a test connection diagram of a semiconductor integrated circuit chip in which the level detection circuit of the present invention has independent pads.

Explanation of symbols

10 First switch transistor
12 First P-well
15 Second switch transistor
17 Second P-well
20 level detection circuit
25 pads
27 Independent pads
30-1 First switch control circuit
30-2 Second switch control circuit
31, 32, 34, 35 PMOS transistors
33, 36 NMOS transistor
37, 39 NOR circuit
38, 40 Inverter 100 Test pad control circuit IN Control signal input terminal OUT Output terminal HVDCET Detection signal input terminal VNEG Negative voltage input terminal DETOUT Detection signal output terminal HVNEG Internal high voltage power supply NEGDET First detection signal TESTEN Test enable signal PADDET Second Detection signal OUT1, 2 output signal LSVDD node of output terminal of inverter 38

Claims (2)

A semiconductor integrated circuit having a test pad control circuit,
A first switch transistor connected to the internal high voltage power supply; a second switch transistor connected to the pad;
The first switch transistor is turned on by the control signal, and the voltage applied to the held transistor circuit is relaxed by the first detection signal indicating that the internal high-voltage power source has exceeded a predetermined voltage. A first switch control circuit;
The voltage applied to the transistor circuit held by the second detection signal indicating that the second switch transistor is turned on by the control signal and the voltage applied to the pad exceeds a predetermined voltage. A second switch control circuit for relaxing
A level detection circuit that generates the second detection signal when a voltage applied to the pad exceeds the predetermined voltage;
At the time of selection by the control signal, the first and second switch control circuits of the semiconductor integrated circuit turn on the first and second switch transistors,
In addition, when the internal high voltage power supply exceeds the predetermined voltage, the first switch control circuit relaxes the voltage applied to the held transistor circuit by the first detection signal, and The switch control circuit 2 relaxes the voltage applied to the transistor circuit that it holds by the second detection signal,
When not selected, the first and second switch control circuits of the semiconductor integrated circuit turn off the first and second switch transistors,
In addition, when the voltage applied to the pad exceeds the predetermined voltage, the second switch control circuit relaxes the voltage applied to the held transistor circuit by the second detection signal. A semiconductor integrated circuit.   2. The semiconductor integrated circuit according to claim 1, wherein the level detection circuit has an independent pad for receiving an activation signal from an external tester and operates according to the activation signal.

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