JP2008293061A - Semiconductor device, and debugging method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To specify instruction data just before abnormal termination which was being executed by a processor. <P>SOLUTION: An LSI 10 comprises a processor 12 having a pipeline 15 which processes instruction data input to the processor 12 through a bus 13 and an arithmetic execution circuit 16 which perform, upon input of the instruction data processed by the pipeline 15 thereto, arithmetic processing according to the instruction data; and a storage circuit 14 which stores the instruction data input from the pipeline 15 to the arithmetic execution circuit 16. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of analyzing a cause when a processor enters an abnormal state.

  2. Description of the Related Art Conventionally, a debugging system that performs debugging by connecting an in-circuit emulator (hereinafter referred to as ICE) to a target processor and a debugger communicating with the processor via the ICE has been widely used. The debugger downloads a program to be executed by the processor via the ICE, sends a break request to the processor, temporarily stops the processing of the processor, and outputs the memory and register status to the debugger, and the memory and register data. The operation of the processor is checked by operating to rewrite In a state where the target processor is operating normally, such an operation is executed without delay.

  However, the processor may stop operating in a state where the bus interface connected to the external bus of the processor does not operate normally due to a defect such as hardware connected to the processor or silicon during manufacture of the processor. For example, a state in which a Ready signal indicating a response from the slave side of the external bus, that is, a hardware connected to the processor is not activated, a state in which a Wait signal for suspending the processor is not activated, or the like can be considered.

  Since ICE accesses memory and registers via the processor's bus interface, if the processor pauses while the bus interface cannot be used, the memory and registers cannot be accessed, and the debugger performs predetermined debugging processing. I can't. In the analysis of the defect in such a state, it is difficult to specify the defective part, and a very long time is spent on the debugging process.

  Patent Documents 1 and 2 disclose a mechanism in which a data storage circuit is provided separately from the main memory in the processor, and a program executed by the processor is stored in the data storage circuit. However, the LSIs described in Patent Document 1 and Patent Document 2 cannot output a program or the like stored in the data storage circuit to an external device such as ICE when the bus interface cannot be used.

In Patent Document 3, a dump bus for dumping memory data is provided separately from the common bus. Even when the common bus cannot be used, memory data is transferred to the outside using the dump bus when the control bus cannot be used. The technology to do is described.
JP 58-045445 A Japanese Patent Laid-Open No. 01-161544 JP 08-328914 A

  However, in the system memory described in Patent Document 3, instruction data between the pipeline and the operation execution circuit cannot be stored, and when the processor is suspended in a state where the bus interface cannot be used, the processor It is difficult to specify the instruction data that has been executed.

  A semiconductor device according to the present invention includes a pipeline that processes instruction data input to a processor via a bus, and an arithmetic execution that receives the instruction data processed by the pipeline and performs arithmetic processing according to the instruction data A processor having a circuit; and a storage circuit for storing the instruction data input from the pipeline to the arithmetic execution circuit.

  According to the semiconductor device of the present invention, by storing the instruction data output from the pipeline to the arithmetic execution circuit in the storage circuit, for example, the instruction stored in the storage circuit even when the processor ends abnormally By tracing the data, it is possible to identify the instruction data immediately before the abnormal termination that was being executed by the processor.

  According to the present invention, it is possible to specify the instruction data immediately before abnormal termination that has been executed by the processor.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[First Embodiment]
FIG. 1 is a block diagram showing an outline of an LSI 10 according to the present invention. In the embodiment, a semiconductor device according to the present invention will be described as LSI 10. The LSI 10 is connected to the analysis device 9 and the main memory 30. The processor 12 included in the LSI 10 calls the instruction data stored in the main memory 30 and executes predetermined arithmetic processing according to the instruction data. The LSI 10 stores instruction data input from the main memory 30 to the processor 12 in the storage circuit 14.

  The instruction data stored in the storage circuit 14 is output to the analysis device 9 when, for example, an abnormality occurs in the processor 12 and the operation of the processor 12 is stopped. The analysis device 9 can analyze the abnormality occurring in the processor 12 by analyzing the instruction data stored in the storage circuit 14.

  FIG. 2 is a block diagram showing a configuration example of the LSI 10 according to the first embodiment of the present invention. The LSI 10 includes a processor 12, a bus 13, and a storage circuit 14. The processor 12 accesses the main memory 30 connected to the bus 13. The processor 12 reads instruction data, numerical data, and the like stored in the main memory 30, executes predetermined arithmetic processing according to a program, and then outputs the arithmetic result to the bus 13. The bus 13 is an internal bus included in the LSI 10. The bus 13 is connected to hardware components such as the processor 12, the main memory 30, and functional modules (not shown).

  The bus 13 serves as a data transmission path between the processor 12 and the main memory or functional module. The storage circuit 14 sequentially stores instruction data flowing inside the processor 12 in the storage unit 18. The storage unit 18 has a FIFO (First In First Out) structure in which the latest instruction data is sequentially stored, and can store a predetermined capacity of the latest instruction data executed by the processor 12. That is, the storage unit 18 stores a certain amount of history of instruction data executed by the processor 12. The instruction data is, for example, information such as an instruction code for identifying the instruction and an address where the instruction is stored. The instruction data stored in the storage unit 18 can be output to the outside of the LSI 10 via the serial interface 19 of the LSI 10. The serial interface 19 is an interface that serially outputs data to the analysis device 9 or the like connected to the outside. The serial interface 19 is not connected to the bus 13 and can output the instruction data stored in the storage unit 18 regardless of the operating state of the processor 12 or the bus 13. The memory circuit 14 may be mounted on a chip different from the processor 12 or may be mounted inside the processor 12.

  The processor 12 includes a pipeline 15, an operation execution circuit 16, and an abnormal state detection circuit 17. The pipeline 15 is provided between the arithmetic execution circuit 16 and the bus 13. The pipeline 15 processes the instruction data input via the bus 13 so that the processing efficiency of the arithmetic execution circuit 16 is improved, and outputs the processed data to the arithmetic execution circuit 16. The processor 12 inputs the instruction data acquired from the bus 13 from the pipeline 15. The instruction data input to the pipeline 15 is pipeline processed and output to the operation execution circuit 16. The pipeline 15 also outputs the instruction data input from the bus 13 to the storage circuit 14. That is, the pipeline 15 outputs the input instruction data to the arithmetic execution circuit 16 and the storage circuit 14. The same instruction data as the instruction data input to the arithmetic execution circuit 16 is sequentially input to the memory circuit 14. The bus 13 is an external bus of the processor 12, whereas the bus between the pipeline 15 and the operation execution circuit 16 is an internal bus of the processor 12.

  The abnormal state detection circuit 17 is a circuit that detects any abnormal state that has occurred in the processor 12. For example, the abnormal state detection circuit 17 receives a signal notifying the abnormality from the operation execution circuit 16 when the instruction data taken into the operation execution circuit 16 is not defined in the processor 12, that is, is an undefined instruction. As a result, the abnormality of the processor 12 is detected. Alternatively, the abnormal state detection circuit 17 detects an abnormality of the processor 12 by detecting that there is no response from the bus 13 for a certain period.

  Alternatively, the abnormal state detection circuit 17 is configured to combine these and detect an abnormal state when an undefined instruction is executed or when there is no response from the bus 13 for a certain period of time. You can also. When the processor 12 detects an abnormal state, the abnormal state detection circuit 17 outputs an abnormal state detection signal to the storage circuit 14. When the abnormal state detection signal is input from the abnormal state detection circuit 16, the storage circuit 14 stops storing the instruction data.

  In the LSI 10 configured as described above, the instruction data input from the bus 13 to the pipeline 15 is sequentially stored in the storage circuit 14. If any abnormal state is detected by the processor 12 by the abnormal state detection circuit 17, the storage circuit 14 interrupts the storage of the instruction data. The instruction data stored by the storage circuit 14 is output to the outside of the LSI 10 via the serial interface 19. The analysis device 9 connected to the outside of the LSI 10 can analyze the abnormal state occurring in the processor 12 by tracing the instruction data stored in the storage circuit 14.

  Next, the operation of the LSI 10 configured as described above will be described. 3 to 5 are timing charts showing the operation of the LSI 10 in accordance with the operation state of the processor 12. FIG. 3 shows the operation of the LSI 10 when the processor 12 is operating normally, and FIGS. 4 and 5 show the operation of the LSI 10 when an abnormal state occurs in the processor 12. FIG. 4 shows an operation of the LSI 10 when an abnormal state occurs in which undefined instruction data is input to the processor 12 as an example, and FIG. 5 shows an abnormality in which a response from the bus 13 is stopped as another example. The operation of the LSI 10 when a state occurs is shown. 3 to 5, from the top, instruction data input from the bus 13 to the pipeline 15, instruction data input from the pipeline 15 to the operation execution circuit 16, instruction data stored in the storage circuit 14, and operation The instruction data executed by the execution circuit 16 is shown.

  FIG. 3 is a timing chart showing the operation of the LSI 10 when the processor 12 is operating normally. During normal operation of the processor 12, instruction data flowing on the bus 13 is input from the pipeline 15 to the processor 12. If the instruction data A to J flows through the bus 13, the instruction data A to J also flows through the pipeline 15. The instruction data input to the pipeline 15 is sequentially stored in the storage circuit 14. The storage circuit 14 writes the instruction data A to J in synchronization with the timing at which the instruction data is input from the pipeline 15 to the arithmetic execution circuit 16. Similarly, instruction data A to J are input from the pipeline 15 to the arithmetic execution circuit 16. The arithmetic execution circuit 16 executes predetermined arithmetic processing according to the instruction data A to J. As described above, while the arithmetic execution circuit 16 executes a predetermined arithmetic process, the storage circuit 14 stores the instruction data A to J executed by the arithmetic execution circuit 16.

  FIG. 4 is a timing chart showing the operation of the LSI 10 when an abnormal state occurs in which undefined instruction data is input to the processor 12. Here, it is assumed that the instruction data E is an undefined instruction in the processor 12. Instruction data A to J flow through the bus 13. The pipeline 15 receives instruction data A to J from the bus 13. The instruction data A to J input to the pipeline 15 are branched and output from the pipeline 15 to the storage circuit 14 and the operation execution circuit 16. The arithmetic execution circuit 16 executes arithmetic processing according to the instruction data input from the pipeline 15.

  In the operation execution circuit 16, for example, when operation data is stopped due to input of undefined instruction data E, the operation execution circuit 16 notifies the abnormal state detection circuit 17 that the operation has stopped. The abnormal state detection circuit 17 outputs an abnormal state detection signal to the storage circuit 14 when receiving a notification of the abnormal state from the arithmetic execution circuit 16. When the abnormal state detection signal is input from the abnormal state detection circuit 17, the storage circuit 14 stops storing the instruction data. That is, the instruction data A to E are stored in the memory circuit 14, and the storage of the instruction data F is interrupted. The history of the instruction data A to F is output to the external analysis device 9 via the serial interface 19.

  By using the analysis device 9 and tracing the instruction data A to F stored in the storage circuit 14, the cause of the occurrence of the abnormal state can be analyzed.

  FIG. 5 is a timing chart showing the operation of the LSI 10 when an abnormal state in which the response from the bus 13 is stopped occurs in the processor 12. The processor 12 fetches instruction data from the bus 13 and executes predetermined arithmetic processing in the arithmetic execution circuit 16. Here, it is assumed that the instruction data after the instruction data E does not flow between the bus 13 and the pipeline 15. If no response is obtained from the bus 13 and the instruction data to be executed cannot be obtained from the bus 13, the operation execution circuit 16 for the instruction data E continues to wait for the bus response until the instruction data is input from the bus 13. The abnormal state detection circuit 17 is connected to the bus 13 and outputs an abnormal state detection signal to the storage circuit 14 when detecting that there is no abnormal response from the bus 13 for a certain period of time. Alternatively, the abnormal state detection circuit 17 is connected to the arithmetic processing circuit 16, and when the arithmetic processing circuit 16 does not execute arithmetic processing for a certain period of time, it determines that there is no response from the bus 13 and outputs an abnormal state detection signal. The abnormal state detection circuit 17 is not limited to these configurations, and may be any configuration that can detect an abnormality of the processor 12.

  When the abnormal state detection signal is input from the abnormal state detection circuit 17, the storage circuit 14 stops storing the instruction data. The instruction data A to E stored in the storage circuit 14 are output to the external analysis device 9 and the like via the serial interface 19. By analyzing the instruction data A to E stored in the storage circuit 14 in the analysis device 9, it is possible to specify the instruction data that was executed immediately before the occurrence of the abnormal state. Thereby, the occurrence of an abnormal state of the processor 12 can be analyzed.

  As described above, in the LSI 10 according to the first embodiment, by providing the storage circuit 14 that stores the state of the pipeline 15 that is a bus inside the processor 12, even if the processor 12 is abnormally terminated, the processor 12 It is possible to specify the instruction data that has been executed. By outputting the instruction data stored in the storage circuit 14 to the outside via the serial interface 19, it is possible to acquire and analyze the instruction data regardless of the operating state of the processor 12 or the bus 13. The analysis device 9 connected to the serial interface 19 does not need to be connected to the LSI 10 at all times. Further, since the instruction data immediately before the occurrence of the abnormal state is automatically stored in the storage unit 18 of the storage circuit 14, it is not necessary to add data for analyzing the abnormal state to the software.

[Second Embodiment]
FIG. 6 is a block diagram showing a configuration example of the LSI 20 according to the second embodiment of the present invention. The feature of the LSI 10 according to the second embodiment is that a parallel interface 21 that outputs signals in parallel is used instead of the serial interface 19 according to the first embodiment. Since other configurations are substantially the same as those of the first embodiment, the same reference numerals are given to the same configurations as those of the first embodiment, and the description thereof is omitted.

  As shown in FIG. 6, in the LSI 20 according to the second embodiment, an interface for outputting instruction data from the storage circuit 14 to the outside is configured by a parallel interface 21. In general, the parallel interface 21 has more signal lines than the serial interface 19, and the serial interface 19 is often used to reduce the number of terminals. However, when the amount of data, that is, the instruction data output to the outside increases, it is preferable to use the parallel interface 21 as in the second embodiment. Thereby, the transfer speed of the instruction data is improved, and the instruction data can be output to the outside in a short time.

  FIG. 7 is a block diagram illustrating a configuration example of an LSI system 100 to which the LSI 20 according to the second embodiment is applied. In the LSI system 100, an LSI 20 including a processor 12 is connected to a main memory 30 via a bus 13. The instruction data of the processor 12 is stored in the main memory 30. Functional modules 31A and 31B are connected to the bus 13 as hardware components of the LSI system 100.

  Next, the operation of the LSI system 100 configured as described above will be described. When activated, the processor 20 starts to acquire instruction data from the bus 13 from the address set in the reset vector from the data stored in the main memory 30. The main memory 30 outputs the reset vector to the bus 13 in response to the reset vector acquisition request from the processor 12. Subsequently, the main memory 30 sequentially outputs instruction data to the bus 13 in response to a request from the processor 12. These data are input to the processor 12 via the bus 13.

  As shown in FIG. 6, instruction data is input to the arithmetic execution circuit 16 through the pipeline 15 inside the processor 20. Data flowing through the pipeline 15 is sequentially output to the storage circuit 14. The storage circuit 14 stores the latest command data in a fixed capacity. The arithmetic execution circuit 16 sequentially executes arithmetic processing according to the instruction data. Here, if undefined instruction data that cannot be processed is input to the processor 12 due to a program generation error or the like, or if the input of instruction data from the bus 13 is stopped, an abnormal state occurs. An abnormal state detection signal is output from the detection circuit 17 to the storage circuit 14. For example, in the arithmetic execution circuit 16, when the arithmetic processing is stopped or when the data on the bus 13 is stopped, it is determined that an abnormality has occurred in the processor 12. As a cause of the stop of the input of the instruction data from the bus 13, for example, a case where the function of the bus 13 is stopped due to a malfunction of the functional modules 31A and 31B connected to the bus 13 can be considered.

  When the abnormal state detection signal is input from the abnormal state detection circuit 17, the storage circuit 14 stops storing the instruction data. This instruction data is output to the outside via the parallel interface 21, and the analysis of the instruction data is executed by the external analysis device 9 or the like. Thereby, in the LSI system 100, the instruction executed by the processor 12 immediately before the abnormality occurs in the processor 12 can be analyzed, and the cause of the abnormality of the processor 12 can be specified.

  The present invention is not limited to the above-described embodiment, and various configurations can be changed as long as the configuration includes a storage circuit 14 that stores instruction data input to the arithmetic execution circuit 16. .

It is a block diagram which shows the outline | summary of LSI10 of this invention. 1 is a block diagram showing a configuration example of an LSI 10 according to a first embodiment of the present invention. 4 is a timing chart showing the operation of the LSI 10 when the processor 12 is operating normally. 6 is a timing chart showing the operation of the LSI 10 when an abnormal state occurs in which undefined instruction data is input to the processor 12. 6 is a timing chart showing an operation of the LSI 10 when an abnormal state in which a response from the bus 13 is stopped occurs in the processor 12. It is a block diagram showing an example of 1 composition of LSI20 concerning a 2nd embodiment of the present invention. It is a block diagram which shows one structural example of the whole LSI system 100 incorporating LSI20 which concerns on 2nd Embodiment.

Explanation of symbols

9 Analysis device 10, 20 LSI
12 processor 13 bus 14 storage circuit 15 pipeline 16 operation execution circuit 17 abnormal state detection circuit 19 serial interface 21 parallel interface 30 main memory 31A, 31B functional module 100 LSI system

Claims (9)

A pipeline that processes instruction data input to the processor via the bus, and a processor having an operation execution circuit that receives the instruction data processed by the pipeline and performs arithmetic processing according to the instruction data;
And a storage circuit for storing the instruction data input from the pipeline to the arithmetic execution circuit. The semiconductor device according to claim 1, further comprising an interface for outputting the instruction data stored in the storage circuit to the outside. The semiconductor device according to claim 1, wherein the storage circuit stores a constant capacity of data updated by the latest instruction data input from the pipeline to the arithmetic execution circuit. The semiconductor device according to claim 1, further comprising an abnormal state detection circuit that detects that the processor has entered an abnormal state. The semiconductor device according to claim 4, wherein the storage circuit stops storing the instruction data when the abnormal state of the processor is detected by the abnormal state detection circuit. The semiconductor device according to claim 2, wherein the interface is a parallel interface that outputs data in parallel. The semiconductor device according to claim 2, wherein the interface is a serial interface that serially outputs data. Pipeline the instruction data input to the processor via the bus,
A semiconductor device debugging method for storing instruction data when performing arithmetic processing according to the pipelined instruction data. The semiconductor device debugging method according to claim 8, wherein an abnormal state of the semiconductor device is analyzed based on the stored instruction data.

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