JP2008288984A - Failure detection method and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To autonomously specify a failure bit between a transmitter and a receiver in generation of a parity error while holding advantages of a normal parity check method, to avoid the failure bit to continue operations. <P>SOLUTION: When the parity error is detected by the receiver 200 with respect to normal data from the transmitter 100, switching to a debug mode is performed in both of the transmitter and the receiver 100, 200 in accordance with detection. With this, pattern data to which parities are added by every bit is transmitted from the transmitter 100 and parity check is performed to the pattern data on the side of the receiver 200. Thus, the parity check is performed by every bit to specify the failure bit. Thus, the transmitter 100 recognizes, for example, which of a high order or lower order there is the failure bit, or what is the failure bit and the operations are continued by normal one either of the high order or low order bit strings of the normal data by transmitting a certain predetermined piece of data from the receiver 200 to the transmitter 100 after specifying the failure bit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a failure detection method and apparatus, and more particularly to a failure bit detection method and apparatus applied to a bus connection including parity bits frequently used in general electric circuits.

  The general parity check method using the parity check bit diagnoses the normality of the data bus. However, since the failure bit cannot be specified by the general parity check method, the investigator himself / herself is informed when a parity error occurs. However, the troublesome trouble of having to specify the failure bit using a measuring instrument or the like has occurred.

  Therefore, a data holding method has been proposed in which data when a parity error occurs is held on the transmission / reception side, and an investigator compares these data (see, for example, Patent Document 1).

  That is, in this prior art, a parity bit is added to the data bus and a parity check is performed at the data receiving side node. At that time, if a parity error is detected at the receiving side node, by enabling the signal line indicating the data error, the data transmitting side node is notified that the parity error has been detected in the data and received. Hold the data. The data transmission side node always saves the transmitted data temporarily. When a data error occurs, the error bit can be specified by reading the data held on the data transmission / reception side and comparing them.

Note that there is a data comparison circuit according to the following reference (for example, see Patent Document 2).
That is, data A (A0 to A7) and data B (B0 to B7) and parity bits AP and BP of data A and B are input to the 2-input exclusive OR circuit, respectively, When they match, the output is 0, and when they do not match, it is 1 and is input to the 9-input OR circuit. The 9-input OR circuit outputs 0 when all input signals are 0, and outputs 1 when any one is 1. Further, the output of the 2-input exclusive OR circuit is input to the parity check circuit, and when the number of logic 1s of the input signal is an odd number, 1 is output, and when the number is an even number, 0 is output. Thus, the presence / absence of an error is determined based on whether the logical value of the output signal is 1, and the error signal is input to the error processing circuit to report the presence / absence of the error to the main control circuit.
Japanese Patent Laid-Open No. 11-85551 JP 55-066031

  In the above Patent Document 1, when a parity error is detected, only the data held on the transmission / reception side is compared, and the failure bit is not identified autonomously between the transmission / reception devices. There was a problem that the operation could not be continued between the transmitting and receiving devices.

  Accordingly, the present invention provides a failure detection method capable of continuing to operate while avoiding the bit by autonomously identifying a failure bit between transmission / reception devices when a parity error occurs while retaining the advantages of the normal parity check method An object is to provide an apparatus.

  In order to achieve the above object, the failure detection method (or apparatus) according to the present invention is a pattern for performing a parity check for each bit when a transmission apparatus receives a parity error occurrence notification for transmitted normal data. A first means (or means) for transmitting data, and a second step (or means) for detecting the failure bit when data specifying the failure bit is received in response to the transmission of the pattern data, The first and second steps (or means) are executed by switching from the normal data access mode to the debug mode.

  Further, in the present invention, as a receiving device, when a parity error is detected by a parity check performed on received normal data, the first step (or means) for notifying the occurrence of the parity error and the occurrence notification A second step (or means) for generating and transmitting data specifying a faulty bit from the pattern data when pattern data for performing a parity check for each bit in response is received; and The second step (or means) may be executed by switching from the normal data access mode to the debug mode.

  The present invention can further include a step (or means) for performing communication using a bit string that does not include the failure bit in the normal data access mode after canceling the debug mode, in common with the transmission / reception apparatus.

  In other words, in the present invention, when a parity error is detected in the receiving device with respect to the normal data from the transmitting device, the transmission mode is switched to the debug mode in both the transmitting and receiving devices, and a parity is added for each bit from the transmitting device. The transmitted pattern data is transmitted, and the parity check is performed on the receiving apparatus side. As a result, since a parity check is performed for each bit, it is possible to identify a faulty bit. After the failure bit is identified in this way, by transferring certain data from the reception device to the transmission device, the transmission device can determine whether the failure bit is in the upper or lower order, for example, or which failure bit is present. It is possible to continue the operation with the normal one of the upper and lower bit strings of the normal data.

  As described above, the system autonomous detection of the failure bit can be easily realized only by adding the status signal between the transmitting and receiving apparatuses and determining the failure bit search method.

Here, the occurrence notification of the parity error and the switching / cancellation of the debug mode are performed via a line different from the normal data bus, and the pattern data and the failure specifying data are transmitted via the normal bus. And can be sent.
The pattern data may be configured by adding 1-bit parity to a bit string in which “1” and “0” are alternately set for each bit.

  Further, the failure bit specifying data is data in which only the upper or lower bit string including the failure bit is set to a predetermined value in the normal data or data in which only the failure bit is set to a predetermined value. Good.

  Note that the above processing may be realized only by hardware or software.

  The advantage of the present invention is that a failure bit can be detected autonomously between transmitting and receiving apparatuses. Therefore, the following effects are mentioned.

 1) The trouble bit investigation work itself becomes unnecessary.

 2) When a parity error occurs, the faulty bit can be identified immediately, so that the data bus operation can be continued while avoiding that bit.

 3) Applicable to all data buses using the parity check method. In this case, the number of parity bits and the number of data are not limited, and can be easily applied to a 1: n-connected data bus if statuses are exchanged between transmitting and receiving apparatuses. In addition, one-way, two-way, clock synchronization, and clock asynchrony may be used.

Device configuration example: Fig. 1
FIG. 1 shows an example of the configuration of an apparatus for realizing the fault detection method according to the present invention. In short, in this configuration example, in addition to the normal data bus BUS and the parity bit line PL, an additional line L for debugging is provided between the transmission device 100 and the reception device 200, and the transmission device is provided by this additional line L. This is different from the prior art in that debug function units 130 and 230 provided in 100 and receiving apparatus 200 are connected to each other. The additional line L includes three hard lines including a parity error (Perr) line L1, a debug (Dbg) line L2, and a response (Ack) line L3.

  More specifically, the transmission apparatus 100 includes a normal control unit 110, a parity generation unit 120, a debug function unit 130, a data transmission / reception unit 140, a parity transmission unit 150, and a data reception unit 160. The receiving apparatus 200 includes a normal control unit 210, a parity check unit 220, a debug function unit 230, a data reception unit 240, a parity reception unit 250, and a data transmission unit 260.

  The normal control unit 110 of the transmission device 100 and the normal control unit 210 of the reception device 200 function via the data transmission unit 140 and the data reception unit 240 during normal data bus BUS access. Parity bits are generated by the parity generation unit 120 under the control of the normal control unit 110 of the transmission device 100, and sent from the parity transmission unit 150 to the parity reception unit 250 of the reception device 200 via the parity bit line PL, and parity check After the parity check in the unit 220, the check result is sent to the normal control unit 210.

  When a parity error occurs, the debug function units 130 and 230 function instead of the normal control units 110 and 210, respectively. The debug function units 130 and 230 monitor a series of failure bit specific sequences, and when an abnormality such as the response signal Ack not being returned is detected, the abnormality of the debug function itself is notified by a register or the like. Interrupt a bit specific sequence. After the interruption, it is possible to return to the normal function and retry the access in which the parity error has occurred, or to stop the operation of the normal data bus BUS itself.

  The normal data bus BUS is defined as an 8-bit a to h data bus (the upper 4 bits are a, b, c, d, and the lower 4 bits are e, f, g, h), and the bit f fails. An example of the operation in the case of the above will be described.

Operation example [1]: Fig. 2 and Fig. 3
First, as an initial state, the data transmission unit 140 of the transmission device 100 is enabled, the data reception unit 160 is disabled, the data reception unit 240 of the reception device 200 is enabled, and the data transmission unit 260 is disabled. .

Step S1:
The normal control unit 110 of the transmission device 100 sends normal data from the data transmission unit 140 to the data reception unit 240 and the normal control unit 210 of the reception device 200 via the normal data bus BUS (normal data bus access mode). The parity bits generated by the parity generation unit 120 based on the data are sent from the parity transmission unit 150 to the parity reception unit 250 via the parity bit line PL.

Step S2:
Receiving the parity bit from the parity receiving unit 250, the parity check unit 220, when detecting a parity error, notifies the normal control unit 210 and the debug function unit 230 of the occurrence (detection) of the parity error. Here, a register (not shown) or the like can be provided so that the user can set in advance whether or not to enable the debug function.

Step S3:
When the debug function is enabled, the debug function unit 230 notifies the debug function unit 130 of the transmission device 100 of the occurrence of a parity error using the parity error signal Perr via the parity error line L1, and the normal control unit 210 It is stored as a log in a parity error occurrence notification register (not shown). In the case of invalid setting, the debug function unit 230 ignores the parity error occurrence notification.

Step S4:
When receiving the parity error signal Perr signal, the debug function unit 130 of the transmission device 100 stops the bus control of the normal control unit 110 for switching to the debug mode.

Step S5:
The debug function unit 130 requests the debug function unit 230 of the reception device 200 to switch the reception device 200 to the debug mode by the debug signal Dbg via the debug line L2.

Step S6:
The debug function unit 230 of the receiving apparatus 200 can be provided with a register (not shown) or the like so that the user can set in advance whether or not to enable the debug function. When enabling the debug mode request, the control of the normal control unit 210 is stopped, and at the same time, the parity check unit 220 is controlled to perform a parity check of each bit according to a procedure according to the failure bit search sequence shown in FIG. Switch to debug mode). When invalidating the debug mode request, the debug function unit 230 ignores the debug signal Dbg. In this case, since the receiving apparatus 200 has a structure that merely relays the parity error signal Perr to the transmitting apparatus 100, there is no problem even if the debug signal Dbg is not returned.

Step S7:
In order to notify the debug function unit 130 of the transmission device 100 that the reception device 200 has also switched to the debug mode, the response signal Ack is returned via the response line L3. In this case, the receiving device 200 is merely a slave, and the receiving device 200 should not be switched to the debug mode unless the master transmitting device 100 is switched to the debug mode.

Step S8:
When receiving the response signal Ack, the debug function unit 130 of the transmission device 100 transmits the patterned data to the parity generation unit 120 and the data transmission unit 140 in a procedure according to the illustrated failure bit search sequence. .

  An example of pattern data at this time is shown in Fig. 3. In order to detect the state stuck to "L" level or "H" level due to failure, each bit is set to "1" and "0" Alternate access with. Bits other than the parity addition target are don't care, and either “1” or “0” may be transmitted.

  That is, for example, in the case of bit a, 9-bit data (a (0) + Ptg) in which parity bit P is added to 8-bit data in which the first bit is “1” and the remaining 7 bits are don't care is transmitted. Next, 9-bit data (a (1) + Ptg) in which parity bit P is added to 8-bit data with the first bit set to “0” and the remaining 7 bits as don't cares is sent. In this way, pattern data of 8 bits × 2 = 16 is transmitted as shown.

  After transmitting the pattern data, the debug function unit 130 immediately controls the data transmission unit 140 to the disabled state and the data reception unit 160 to the enabled state.

  Further, the debug function unit 230 of the receiving device 200, when configured as an 8-bit bus + 1-bit parity bus as shown in FIG. Since the parity check unit 220 detects a parity error, the failure bit can be specified. Here, it is assumed that a failure of the bit f is detected as shown in FIG.

Step S9:
The debug function unit 230 stores the failure bit as a log in a register (not shown) or the like, and controls the data reception unit 240 to be in a disabled state and the data transmission unit 260 to be in an enabled state so that a bit string (a, b, c, d) = (1, 1, 1, 1) is transmitted. At this time, the bit string (e, f, g, h) including the failure bit f may be don't care. On the other hand, if the upper bit, for example, bit a has failed, a bit string (e, f, g, h) = (1, 1, 1, 1) is transmitted.

Step S10:
The debug function unit 130 of the transmission device 100 receives (a, b, c, d) = (1, 1, 1, 1) and recognizes the failure of the lower 4 bits.

Step S11:
Simultaneously with the recognition of the bit failure, the debug signal Dbg of the line L2 is promptly negated and a debug mode release request is made.

Step S12:
When the debug function unit 230 of the receiving device 200 knows that the debug mode cancellation request is made by the debug signal Dbg, the debug function unit 230 controls the data reception unit 240 to be enabled and the data transmission unit 260 to be disabled to cancel the debug mode. .

Step S13:
The debug function unit 230 gives a control right to the normal control unit 210 at the same time as sending back the response signal Ack to the transmission device 100 via the line L3 and performing a debug mode release response.

Step S14:
When the debug function unit 130 of the transmission device 100 knows that the reception device 200 has released the debug mode by receiving the response signal Ack, the debug function unit 130 controls the data transmission unit 140 to the enabled state and the data reception unit 160 to the disabled state ( Debug mode is released) and the control right is given to the normal control unit 110 as the upper 4 bit mode.

Step S15:
Since the normal control unit 110 of the transmitting device 100 is notified of the failure on the lower 4 bits side from the debug function unit 130, the normal bus access mode is resumed using only the upper 4 bits.

Operation example [2]: Fig. 3 and Fig. 4
In the case of the operation example [1] shown in FIG. 2, when the failure bit notification (step S9) is performed in the receiving apparatus 200, the upper bit string or the lower bit string not including the failure bit f is set to “1” (others Don't care) is sent to the transmitting device 100. In this operation example [2], only the failure bit f is set to “0” and the others are set to “1” as shown in step S9 ′ of FIG. Thus, the transmitting device 100 detects that there is a failure in the bit f (step S10 ′), and the operation example [1] in the upper 4 bits a to d excluding the lower bit string e to h to which the failure bit f belongs. Similarly, normal data bus access (step S15) is performed.

  It should be noted that the present invention is not limited to the above-described embodiments, and it is apparent that various modifications can be made by those skilled in the art based on the description of the scope of claims.

  For example, a failure bit is not detected in the failure bit search sequence, or a failure that does not operate according to the sequence is conceivable. In this case, the debug mode may be canceled halfway, and the debug function unit error may be displayed as a log in a register or the like, and a retry operation can be easily realized.

It is the block diagram which showed the Example of the apparatus (transmitter and receiver) which implement | achieves the failure detection method which concerns on this invention. FIG. 5 is a sequence diagram showing an operation example [1] of the failure detection method and apparatus used in the present invention. It is the figure which showed the example of pattern data used for the failure bit specific sequence used for this invention. FIG. 6 is a sequence diagram showing an operation example [2] of the failure detection method and apparatus used in the present invention.

Explanation of symbols

100 Transmitter
200 Receiver
110, 210 Normal control unit
120, 220 Parity generator
130, 230 Debug function
140, 240 Data transmitter
150, 250 Parity transmitter
160, 260 Data receiver
BUS Normal data bus
PL Parity bit line
L Additional line
L1 Parity error (Perr) line
L2 debug (Dbg) track
L3 response (Ack) line In the figure, the same reference numerals indicate the same or corresponding parts.

Claims (6)

A first step of transmitting pattern data for performing a parity check for each bit when a notification of occurrence of a parity error with respect to the transmitted normal data is received;
A second step of detecting the failure bit when data specifying the failure bit is received in response to the transmission of the pattern data;
The failure detection method is characterized in that the first and second steps are executed by switching from the normal data access mode to the debug mode. A first step of notifying the occurrence of a parity error when a parity error is detected by a parity check performed on the received normal data;
A second step of generating and transmitting data specifying a faulty bit from the pattern data when receiving pattern data for performing a parity check for each bit in response to the occurrence notification;
The failure detection method is characterized in that the first and second steps are executed by switching from the normal data access mode to the debug mode. In claim 1 or 2,
A failure detection method further comprising the step of performing communication using a bit string not including the failure bit in the normal data access mode after canceling the debug mode. In claim 1 or 2,
Notification of occurrence of the parity error and switching / canceling of the debug mode are performed via a line different from the normal data bus, and the pattern data and the fault identification data are transmitted via the normal bus. Fault detection method characterized by being performed. A first means for transmitting pattern data for performing a parity check for each bit when a notification of occurrence of a parity error with respect to the transmitted normal data is received;
A second means for detecting the failure bit when data specifying the failure bit is received in response to the transmission of the pattern data;
A fault detection apparatus, wherein the first and second means are executed by switching from the normal data access mode to the debug mode. A first means for notifying the occurrence of a parity error when a parity error is detected by a parity check performed on the received normal data;
A second means for generating and transmitting data specifying a faulty bit from the pattern data when pattern data for performing a parity check for each bit is received in response to the occurrence notification;
A fault detection apparatus, wherein the first and second means are executed by switching from the normal data access mode to the debug mode.

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