JP2008287195A - Display device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of suppressing an influence of characteristic variation of a drive transistor while securing current supply capability of the drive transistor. <P>SOLUTION: A pixel 2 is separated into an emitting part C including a light emitting element EL, and a drive part for driving the light emitting element EL. The drive part includes at least a sampling transistor Tr1, a drive transistor Tr2, and a holding capacity Ccs. The sampling transistor Tr1 switches on in response to a control signal supplied from a scanning line WS to sample a video signal Vsig supplied from a signal line SL so as to be written in the holding capacity Ccs. The drive transistor Trd supplies a drive current corresponding to the video signal written in the holding capacity Ccs to the light emitting element EL. The pixel 2 includes two drive parts A, B for one light emitting element EL and simultaneously supplies the drive current from two drive transistors Trda, Trdb to the one light emitting element EL. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device that performs display by driving a light emitting element arranged for each pixel. More specifically, the present invention relates to a so-called active matrix type image display device that controls an amount of current supplied to a light emitting element such as an organic EL by an insulated gate field effect transistor provided in each pixel circuit. The present invention also relates to an electronic apparatus using such an image display device as a display.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  A conventional display device includes row-like scanning lines, column-like signal lines, and matrix-like pixels arranged at portions where each scanning line and each signal line intersect. Each pixel is divided into a light emitting unit including a light emitting element and a driving unit for driving the light emitting element. The drive unit includes at least a sampling transistor, a drive transistor, and a storage capacitor. The sampling transistor is turned on in response to the control signal supplied from the scanning line, samples the video signal supplied from the signal line, and writes it in the storage capacitor. The drive transistor supplies a drive current to the light emitting element according to the video signal written in the storage capacitor.

  The drive transistor receives the video signal held in the holding capacitor as an input voltage at the gate, passes an output current Ids between the source and the drain, and energizes the light emitting element. In general, the light emission luminance of a light emitting element is proportional to the amount of current applied. Further, the output current supply amount of the drive transistor is controlled by the gate voltage Vgs, that is, the input voltage written in the storage capacitor. This pixel circuit controls the amount of current supplied to the light emitting element by changing the input voltage applied to the gate of the drive transistor in accordance with the input video signal.

Here, the operating characteristic of the drive transistor is expressed by the following Equation 1.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ² Formula 1
In the transistor characteristic formula 1, Ids represents a drain current flowing between the source and the drain, and is an output current supplied to the light emitting element in the pixel circuit. Vgs represents a gate voltage applied to the gate with reference to the source, and is the above-described input voltage in the pixel circuit. Vth is the threshold voltage of the transistor. Μ represents the mobility of the semiconductor thin film constituting the channel of the transistor. In addition, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from the transistor characteristic equation 1, when the thin film transistor operates in the saturation region, if the gate voltage Vgs increases beyond the threshold voltage Vth, the thin film transistor is turned on and the drain current Ids flows. In principle, as shown in the above transistor characteristic equation 1, if the gate voltage Vgs is constant, the same amount of drain current Ids is always supplied to the light emitting element. Therefore, if video signals of the same level are supplied to all the pixels constituting the screen, all the pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

  However, actually, individual drive transistors formed in each pixel have variations in threshold voltage Vth and mobility μ. As apparent from the transistor characteristic equation 1 above, if the mobility μ and the threshold voltage Vth vary, even if the input voltage Vgs is the same, the output current Ids is different, and the uniformity of the screen is obtained. I can't. Therefore, a display device in which a threshold voltage correction function and a mobility correction function of a drive transistor are incorporated in each pixel circuit has been conventionally known.

  On the other hand, the size of the drive transistor is determined by the factor W / L included in the transistor characteristic equation 1 described above. W / L may be referred to as a size factor. As the channel width W increases and the channel length L decreases, the size factor W / L increases and the current supply capability increases. When the size factor of the drive transistor is increased, the on-resistance of the channel region is decreased, so that a large output current Ids can be obtained even with the same input voltage Vgs. Therefore, a conventional display device employs a method of designing a large drive transistor size factor in order to obtain high luminance with a limited power supply voltage.

  However, when the size of the drive transistor is increased, the influence of variations in mobility μ and threshold voltage Vth increases accordingly. Only with the mobility correction function and the threshold voltage correction function incorporated in the pixel circuit, it is difficult to suppress the characteristic variation, and there is a problem that the uniformity of the screen is impaired.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a display device capable of suppressing the influence of variation in characteristics of drive transistors while ensuring the current supply capability of the drive transistors. In order to achieve this purpose, the following measures were taken. That is, the present invention includes row-like scanning lines, column-like signal lines, and matrix-like pixels arranged at portions where each scanning line and each signal line intersect, and each pixel includes a light emitting element. The driving unit includes at least a sampling transistor, a drive transistor, and a storage capacitor, and a control terminal of the sampling transistor is connected to the scanning line. The pair of current ends are connected between the signal line and the control end of the drive transistor, and the drive transistor has one of the pair of current ends connected to a power source and the other connected to the light emitting element, The holding capacitor is connected to a control terminal of the drive transistor, and the sampling transistor is turned on in response to a control signal supplied from the scanning line and receives a video signal supplied from the signal line. And the drive transistor supplies a driving current corresponding to the video signal written in the storage capacitor to the light emitting element, and the pixel is connected to one light emitting element. On the other hand, two drive units are included, and a drive current is supplied simultaneously from two drive transistors to one light emitting element.

  Preferably, the pixel operates in a light emission period and a non-light emission period, and each driving unit has a storage capacitor connected between a control terminal and a current terminal of the drive transistor, and the video signal is output in the non-light emission period. In the storage capacitor, the drive current is negatively fed back to the storage capacitor for a predetermined correction time, and the correction for the mobility of the drive transistor is applied to the video signal held in the storage capacitor. A drive current is simultaneously supplied to the light emitting element in accordance with the corrected video signal. In addition, the drive transistor included in each drive unit is half the transistor size set when a drive current is supplied to one light emitting element with a single drive transistor, and two drive transistors. The drive currents supplied by the drive transistors included in the unit are combined to supply the required drive current to one light emitting element, and the two drive transistors are used together to average the characteristic variation within the pixel.

  According to the present invention, each pixel includes two drive units for one light-emitting element, and simultaneously supplies a drive current from two drive transistors to one light-emitting element. A required driving current can be supplied to one light emitting element by combining the driving currents supplied by the drive transistors included in the two driving units. On the other hand, by using two drive transistors together, it is not necessary to increase the size of one drive transistor. Accordingly, the influence of the variation in characteristics of the drive transistor is reduced. In addition, by incorporating two drive transistors in the pixel, it is possible to average the characteristic variation between the two in the pixel. As a result, the variation in characteristics of the drive transistor can be sufficiently canceled by the mobility correction function and the threshold voltage correction function incorporated in the pixel circuit, and the screen uniformity can be remarkably improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an image display apparatus according to the present invention. As shown in the figure, this image display apparatus basically includes a pixel array unit 1, a scanner unit, and a signal unit. The pixel array unit 1 includes a scanning line WS, a scanning line AZ1, a scanning line AZ2, and a scanning line DS arranged in rows, a signal line SL arranged in a column, and these scanning lines WS, AZ1, AZ2, DS. And the matrix-like pixels 2 connected to the signal lines SL, and a plurality of power supply lines for supplying the first potential Vofs, the second potential Vini, and the third potential Vcc necessary for the operation of each pixel 2. The signal unit includes a horizontal selector 3 and supplies a video signal to the signal line SL. The scanner unit includes a write scanner 4, a drive scanner 5, a first correction scanner 71, and a second correction scanner 72, and supplies control signals to the scanning line WS, the scanning line DS, the scanning line AZ1, and the scanning line AZ2, respectively. The pixels 2 are sequentially scanned for each row. Each pixel 2 is assigned with three primary colors RGB, and is displayed in color. However, the present invention is not limited to this, and can be applied to a single color display.

  FIG. 2 is a circuit diagram illustrating a configuration example of a pixel incorporated in the image display device illustrated in FIG. As illustrated, the pixel 2 includes a sampling transistor Tr1, a drive transistor Trd, a first switching transistor Tr2, a second switching transistor Tr3, a third switching transistor Tr4, a storage capacitor Ccs, and a light emitting element EL. . The sampling transistor Tr1 conducts according to a control signal supplied from the scanning line WS during a predetermined sampling period, and samples the signal potential of the video signal supplied from the signal line SL into the holding capacitor Ccs. The holding capacitor Ccs applies the input voltage Vgs to the gate G of the drive transistor Trd in accordance with the signal potential of the sampled video signal. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL. The light emitting element EL emits light with a luminance corresponding to the signal potential of the video signal by the output current Ids supplied from the drive transistor Trd during a predetermined light emission period. An auxiliary capacitor Ccsub is connected in parallel with the light emitting element EL.

  The first switching transistor Tr2 is turned on in response to a control signal supplied from the scanning line AZ2 prior to the sampling period, and sets the gate G of the drive transistor Trd to the first potential Vofs. The second switching transistor Tr3 is turned on according to the control signal supplied from the scanning line AZ1 prior to the sampling period, and sets the source S of the drive transistor Trd to the second potential Vini. The third switching transistor Tr4 is turned on in response to a control signal supplied from the scanning line DS prior to the sampling period to connect the drive transistor Trd to the third potential Vcc, and thus corresponds to the threshold voltage Vth of the drive transistor Trd. The voltage is held in the holding capacitor Ccs to correct the influence of the threshold voltage Vth. Further, the third switching transistor Tr4 is turned on again in response to the control signal supplied from the scanning line DS during the light emission period, connects the drive transistor Trd to the third potential Vcc, and causes the output current Ids to flow through the light emitting element EL.

  As is apparent from the above description, the pixel circuit 2 includes five transistors Tr1 to Tr4 and Trd, one holding capacitor Ccs, and one light emitting element EL. The transistors Tr1 to Tr3 and Trd are N channel type polysilicon TFTs. Only the transistor Tr4 is a P-channel type polysilicon TFT. However, the present invention is not limited to this, and N-channel and P-channel TFTs can be mixed as appropriate. The light emitting element EL is, for example, a diode type organic EL device having an anode and a cathode. However, the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

  FIG. 3 is a timing chart of the pixel circuit shown in FIG. With reference to FIG. 3, the operation of the pixel circuit shown in FIG. 2 will be specifically described. FIG. 3 shows the waveforms of control signals applied to the scanning lines WS, AZ1, AZ2, and DS along the time axis T. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Since the transistors Tr1, Tr2, and Tr3 are N-channel type, they are turned on when the scanning lines WS, AZ2, and AZ1 are at a high level and turned off when the scanning lines are at a low level. On the other hand, since the transistor Tr4 is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. This timing chart also shows the potential change Vg of the gate G and the potential change Vs of the source S of the drive transistor Trd, along with the waveforms of the control signals WS, AZ1, AZ2, and DS.

  In this display device, each row of the pixel array is sequentially scanned once during one field. The timing chart shows the waveforms of the control signals WS, AZ1, AZ2, and DS applied to the pixels for one row. Before the timing T1 when the field starts, all the control signals WS, AZ1, AZ2, and DS are at a low level. Therefore, the N-channel transistors Tr1, Tr2, Tr3 are in the off state, while only the P-channel transistor Tr4 is in the on state. Therefore, since the drive transistor Trd is connected to the power supply Vcc via the transistor Tr4 in the on state, the output current Ids is supplied to the light emitting element EL according to the predetermined input voltage Vgs. Therefore, the light emitting element EL emits light. At this time, the input voltage Vgs applied to the drive transistor Trd is represented by the difference between the gate potential Vg and the source potential Vs.

  At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. As a result, the transistor Tr4 is turned off and the drive transistor Trd is disconnected from the power supply Vcc, so that the light emission stops and the non-light emission period starts. Therefore, at the timing T1, all the transistors Tr1 to Tr4 are turned off.

  Subsequently, at timing T2, the control signal AZ1 becomes high level, so that the switching transistor Tr3 is turned on. As a result, the source S of the drive transistor Trd is connected to the reference potential Vini.

  Subsequently, at timing T3, since the control signal AZ2 becomes high level, the switching transistor Tr2 is also turned on. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vofs. Here, Vofs−Vini> Vth is satisfied, and by setting Vofs−Vini = Vgs> Vth, preparation for Vth correction performed at timing T5 is performed. In other words, the period T2-T3 corresponds to a reset period of the drive transistor Trd. When the threshold voltage of the light emitting element EL is VthEL, VthEL> Vini is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normally performing the Vth correction operation and the mobility correction operation to be performed later.

  Thereafter, at timing T4, the control signal AZ1 is returned to the low level, the switching transistor Tr3 is turned off, and the source S of the drive transistor Trd is disconnected from the reference potential Vini. On the other hand, the control signal AZ2 remains at the high level, and the gate G of the drive transistor Trd is continuously connected to the reference potential Vofs.

  Subsequently, at timing T5, the control signal DS becomes low level, and the switching transistor Tr4 is turned on. As a result, the drain current Ids flows into the storage capacitor Ccs, and the Vth correction operation (Vth cancellation operation) is started. At this time, the gate G of the drive transistor Trd is held at Vofs, and the current Ids flows until the drive transistor Trd is cut off. When cut off, the source potential Vs of the drive transistor Trd becomes Vofs−Vth.

  At timing T6 after the drain current Ids is cut off, the control signal DS is returned to the high level again, and the switching transistor Tr4 is turned off. Further, at timing T7, the control signal AZ2 is also returned to the low level, and the switching transistor Tr2 is also turned off. As a result, the gate G of the drive transistor Trd is also disconnected from Vofs, and Vth is held and fixed in the holding capacitor Ccs. Thus, the timing T5-T6 is a period for detecting the threshold voltage Vth of the drive transistor Trd. Here, this detection period T5-T6 is called a Vth correction period (Vth cancellation period).

  After performing the Vth correction in this way, the control signal WS is switched to the high level at the timing T8, the sampling transistor Tr1 is turned on, and the video signal Vsig is written in the storage capacitor Ccs. The storage capacitor Ccs is sufficiently smaller than the equivalent capacitor Coled of the light emitting element EL. As a result, most of the video signal Vsig is written in the storage capacitor Ccs. Precisely, the difference Vsig−Vofs of Vsig with respect to Vofs is written in the storage capacitor Ccs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig−Vofs + Vth) obtained by adding Vth previously detected and held and Vsig−Vofs sampled this time. In the following description, when Vofs = 0 V for simplification of explanation, the gate / source voltage Vgs becomes Vsig + Vth as shown in the timing chart of FIG. The sampling of the video signal Vsig is performed until timing T10 when the control signal WS returns to the low level. That is, the timing T8-T10 corresponds to the sampling period.

  At timing T9 after timing T8 and before timing T10, the control signal DS becomes low level and the switching transistor Tr4 is turned on. As a result, the drive transistor Trd is connected to the power supply Vcc, so that the pixel circuit transitions from the non-light emitting period to the light emitting period. Here, the mobility of the drive transistor Trd is corrected in a period T9-T10 in which the sampling transistor Tr1 is still in the on state and the switching transistor Tr4 is in the on state. That is, in this example, the mobility correction is performed in the period T9-T10 in which the rear part of the sampling period and the head part of the light emission period overlap. Note that, at the beginning of the light emission period in which the mobility correction is performed, the light emitting element EL is actually in a reverse bias state, and thus does not emit light. In the mobility correction period T9-T10, the drain current Ids flows through the drive transistor Trd while the gate G of the drive transistor Trd is fixed at the level of the video signal Vsig. Here, by setting Vofs−Vth <VthEL, the light emitting element EL is placed in a reverse bias state, so that it exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd is written in a capacitor C = Ccs + Coled + Ccsub that combines the holding capacitor Ccs, the equivalent capacitor Coled of the light emitting element EL, and the auxiliary capacitor Ccsub. As a result, the source potential Vs of the drive transistor Trd increases. In the timing chart of FIG. 3, this increase is represented by ΔV. Since this increase ΔV is eventually subtracted from the gate / source voltage Vgs held in the holding capacitor Ccs, negative feedback is applied. In this way, the mobility μ can be corrected by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T9-T10.

At timing T10, the control signal WS becomes low level and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the video signal Vsig is cancelled, the gate potential Vg of the drive transistor Trd can be increased and increases with the source potential Vs. Meanwhile, the gate / source voltage Vgs held in the holding capacitor Ccs maintains a value of (Vsig−ΔV + Vth). As the source potential Vs rises, the reverse bias state of the light emitting element EL is canceled, so that the light emitting element EL actually starts to emit light by the inflow of the output current Ids. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the following equation 2 by substituting Vsig−ΔV + Vth into Vgs of the previous transistor characteristic equation 1.
Ids = kμ (Vgs−Vth) ² = kμ (Vsig−ΔV) ² Equation 2
In the above formula 2, k = (1/2) (W / L) Cox. It can be seen from the characteristic formula 2 that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the video signal Vsig. At that time, Vsig is corrected by the feedback amount ΔV. This correction amount ΔV acts so as to cancel the effect of the mobility μ located in the coefficient part of the characteristic formula 2 just. Therefore, the drain current Ids substantially depends only on the video signal Vsig.

  FIG. 4 is a graph showing the relationship between the output current Ids of the drive transistor and the mobility correction time t. The vertical axis represents the drain current Ids, and the horizontal axis represents the mobility correction period t. For comparison, the relationship between the mobility correction time t and the drain current Ids is measured for both samples of a drive transistor having a large size factor and a drive transistor having a small size factor. In addition, a sample having a larger size and a smaller mobility μ are prepared for a large-sized drive transistor, and data obtained by comparing the two are obtained. In the graph, the characteristic curve of a sample having a large mobility μ is represented by a solid line, and the characteristic curve of a drive transistor having a small mobility μ is represented by a chain line. The same applies to a small drive transistor.

  First, focusing on a drive transistor having a large size factor and a large mobility μ, this has the highest drain current supply capability. At the mobility correction start timing T9, negative feedback to the storage capacitor Ccs starts and Vgs is compressed, so that the drain current Ids decreases with time. A large and μ-sized drive transistor has a high drive current capability, and a current drop is abrupt.

  On the other hand, the large and small samples have a slightly lower current supply capability than the large and large samples, and the drain current Ids starts to decrease at the correction start timing T9, but the slope is relatively gentle. At the timing T10L, the sample having a large size and μ size and the output current level are reversed. In other words, at the timing T10L, the sample having just the high mobility μ and the sample having the low mobility μ are at the same drain current Ids level. If the mobility correction operation is completed at this timing, the same drain current Ids level is obtained regardless of the magnitude of the mobility μ, and the mobility correction can be performed completely. In other words, the period from timing T9 to timing T10L is the optimum mobility correction time t for a large drive transistor.

  On the other hand, looking at the small size drive transistor, the current supply capability is halved compared to the large size sample. That is, this example is a case where a small sample has a size factor that is exactly half that of a large sample. Here, when attention is focused on the larger μ, the drain current Ids decreases at the correction start timing T9, but the tendency is gentler than that of the large sample. Since the drain current Ids tends to decrease more slowly in the sample with a small mobility μ, the characteristic curves of both samples intersect at the timing T10S, and the levels of the drain current Ids match. If the mobility correction operation is terminated here, the optimum mobility correction operation can be applied to the small-sized drive transistor. In other words, the period from timing T9 to timing T10S is the optimum mobility correction time for a small-sized drive transistor.

  As is apparent from the graph of FIG. 4, the large size optimum mobility correction period T10L-T9 is shorter than the optimum mobility correction time T10S-T9 of the small size drive transistor. As the optimum mobility correction time t becomes shorter, the control becomes difficult and variations occur. Therefore, in order to increase the accuracy of mobility correction, the optimal mobility correction time t should be longer. In this aspect, a drive transistor having a small size factor is more advantageous than a drive transistor having a large size.

  On the other hand, a large drive transistor has a higher current supply capability than a small drive transistor. Therefore, when the power supply voltage and the signal voltage are made constant, higher luminance can be obtained by using a large size drive transistor. Alternatively, if the luminance is the same, the signal voltage and the power supply voltage can be reduced by using a large drive transistor. Therefore, from the viewpoint of screen brightness, a large drive transistor is more advantageous than a small drive transistor.

  In view of the above-described problems, an object of the present invention is to provide a pixel circuit configuration that can suppress variation in characteristics such as mobility μ while securing current supply capability of a drive transistor. In order to achieve this object, the pixel circuit configuration shown in FIG. 5 is adopted. FIG. 5 is a circuit diagram showing a first embodiment of one pixel included in the display device according to the present invention. The main pixel 2 is arranged at a portion where each scanning line WS and each signal line SL intersect. The pixel 2 is divided into a light emitting unit including a light emitting element and a driving unit for driving the light emitting element. As a feature of the present invention, the pixel 2 includes two drive units A and B for one light emitting unit C, and a drive current is simultaneously applied to one light emitting element EL from two drive transistors Trd. Supply.

  The light emitting part C of the pixel circuit 2 includes a light emitting element EL and an auxiliary capacitor Ccsub connected in parallel thereto. On the other hand, one drive unit A is basically the same as the configuration of the pixel 2 shown in FIG. 2, and corresponding portions are denoted by corresponding reference numerals. However, in order to distinguish each element included in the drive unit A from each element included in the drive unit B, a braille a is added to a reference symbol of each element. Similarly, each element belonging to the drive unit B has a braille b added to its reference symbol.

  The drive unit A includes at least a sampling transistor Tr1a, a drive transistor Trda, and a storage capacitor Ccsa. In addition, this embodiment includes a switching transistor Tr2a, a switching transistor Tr3a, and a switching transistor Tr4a. Up to this point, the configuration is the same as that of the pixel 2 shown in FIG. In this embodiment, in addition to these five transistors, an additional switching transistor Tr5a is provided. A pair of current ends of the switching transistor Tr5a are connected between the source S of the drive transistor Trda and the anode of the light emitting element EL. A control signal TSa is applied from the additional scanning line TSa to the gate of the switching transistor Tr5a.

  The sampling transistor Tr1a has a control terminal connected to the scanning line WSa, and a pair of current terminals connected between the signal line SL and the control terminal (gate G) of the drive transistor Trda. The drive transistor Trda has one of a pair of current ends connected to the power supply Vcc via the switching transistor Tr4a, and the other connected to the anode of the light emitting element EL via the switching transistor Tr5a. The storage capacitor Ccsa is connected between the gate G and the source S of the drive transistor Trda. In such a configuration, the sampling transistor Tr1a is turned on in response to the control signal WSa supplied from the scanning line WSa, samples the video signal Vsig supplied from the signal line SL, and writes it to the holding capacitor Ccsa. The drive transistor Trda supplies a drive current Ids corresponding to the video signal Vsig written in the storage capacitor Ccsa to the light emitting element EL.

  The pixel circuit 2 of the present embodiment operates in a light emitting period and a non-light emitting period. The drive unit A writes the video signal Vsig into the holding capacitor Ccsa during a part of the non-light emitting period, and negatively feeds back the driving current Ids to the holding capacitor Ccsa for a predetermined mobility correction time to correct the mobility of the drive transistor Trda. The video signal held in the holding capacitor Ccsa is applied. In the light emission period, the drive unit A supplies the drive current Ids to the light emitting element EL according to the corrected video signal.

  The other drive unit B has the same circuit configuration as the drive unit A. That is, the sampling transistor Tr1b has a control terminal (gate) connected to the scanning line WSb, and a pair of current terminals connected between the signal line SL and the control terminal (gate G) of the drive transistor Trdb. In the drive transistor Trdb, one (drain) of a pair of current ends is connected to the power supply Vcc via the switching transistor Tr4b, and the other (source S) is connected to the anode of the light emitting element EL via the switching transistor Tr5b. The storage capacitor Ccsb is connected between the gate G and the source S of the drive transistor Trdb. In such a configuration, the sampling transistor Tr1b is turned on in response to the control signal WSb supplied from the scanning line WSb, samples the video signal Vsig supplied from the signal line SL, and writes it to the holding capacitor Ccsb. The drive transistor Trdb supplies a drive current Ids corresponding to the video signal Vsig written in the storage capacitor Ccsb to the light emitting element EL. Similar to the drive unit A, the drive unit B writes the video signal Vsig into the storage capacitor Ccsb during a part of the non-light emission period, and negatively feeds back the drive current Ids to the storage capacitor Ccsb for a predetermined correction time, thereby driving the drive transistor Trdb. Is applied to the video signal Vsig held in the holding capacitor Ccsb. In the light emission period, the driving unit B supplies the driving current Ids to the light emitting element EL according to the corrected video signal simultaneously with the driving unit A.

  In the present embodiment, when the drive transistors Trda and Trdb included in the drive units A and B supply the drive current Ids to one light emitting element EL with the single drive transistor Trd shown in FIG. Compared to the set transistor size, the transistor size is half, and the drive current supplied from the drive transistors Trda and Trdb included in the two drive units A and B is combined to emit one drive current. This is supplied to the element EL. By using both drive transistors Trda and Trdb in this way, the characteristic variation can be averaged within the pixel 2.

  As is apparent from the above description, the present embodiment combines the drive transistors Trda and Trdb to emit light simultaneously even though the size factor of the drive transistors Trda and Trdb is half that of the drive transistor Trd shown in FIG. A necessary drain current is secured by driving the element EL. On the other hand, each of the drive transistors Trda and Trdb can take a longer optimum mobility correction time as the size factor becomes smaller. Therefore, the accuracy of the mobility correction operation is increased, and the uniformity of the screen is improved. In addition, since the characteristic variations of both drive transistors Trda and Trdb are averaged within the same pixel 2, the characteristic variations are reduced accordingly.

  FIG. 6 is a timing chart for explaining the operation of the pixel shown in FIG. The waveforms of the control signals applied to the gates of the sampling transistor and switching transistor belonging to the driving unit A and the driving unit B are shown in time series. The period from the timing T1 to the timing T10 is a non-light emission period, and the light emission period starts after the timing T10. In the first half A of the non-light emission period, the drive unit A performs a predetermined correction operation. That is, after shifting to the non-light emitting period at timing T1, Vth cancellation A is performed between timing T5a and timing T6a. Further, the operation of signal writing A is performed between timing T8a and timing T10a. During this period, the operation of μ correction A is performed between timing T9a and timing T10a. The mobility correction periods T9a to T10a are extended by halving the size of the drive transistor Trda.

  Subsequently, in the second half B of the non-light emission period, the drive unit B performs the Vth cancel B operation, the signal write B operation, and the μ correction B operation in the same manner. Thereafter, at timing T10, the light emission period starts and the control signal TSa is switched from the low level to the high level. At this time, the control signal TSb continues to maintain a high level. Therefore, since both the switching transistor Tr5a on the driving unit A side and the switching transistor Tr5b on the driving unit B side are in the on state, the driving current supplied from both the driving unit A and the driving unit B is the switching transistor Tr5a in the on state. , Tr5b to be supplied to the common light emitting element EL.

  FIG. 7 is a schematic circuit diagram showing a second embodiment of the pixel 2 incorporated in the display device according to the present invention. Similar to the first embodiment, in this embodiment as well, the pixel 2 includes a pair of driving units A and B and a single light emitting unit C. The light emitting unit C includes a light emitting element EL and an auxiliary capacitor Ccsub.

  The second embodiment shown in FIG. 7 is basically similar to the first embodiment shown in FIG. 5, and corresponding reference numerals are assigned to corresponding parts for easy understanding. The difference is that in the first embodiment, the driving units A and B are operated in a time-sharing manner, whereas in the present embodiment, the driving unit A and the driving unit B are simultaneously operated in parallel in a non-light emitting period. . In this relationship, a common scanning line is connected to the transistor belonging to the drive unit A and the transistor belonging to the drive unit B. For example, a common scanning line WS is connected to the sampling transistor Tr1a on the drive unit A side and the sampling transistor Tr1ab on the drive unit B side. Similarly, a common scanning line DS is connected to the switching transistor Tr4a on the driving unit A side and the switching transistor Tr4b on the driving unit B side. Unlike the first embodiment, in this embodiment, the source S of the drive transistor Trda on the drive unit A side is directly connected to the anode of the light emitting element EL. Similarly, the source S of the drive transistor Trdb on the drive unit B side is also directly connected to the anode of the light emitting element EL.

  FIG. 8 is a timing chart for explaining the operation of the pixel according to the second embodiment shown in FIG. Basically, it is the same as the timing chart shown in FIG. 3, and the period from timing T1 to timing T10 is a non-light emitting period, and the timing shifts to the light emitting period after timing T10. In the non-light emitting period T1-T10, the pair of driving units A and B operate simultaneously and in parallel to perform Vth cancellation, signal writing, and mobility correction. In the timing chart of FIG. 8, the operations of the corresponding drive unit A and drive unit B are shown separately for part A and part B for easy understanding.

  The display device according to the present invention has a thin film device configuration as shown in FIG. This figure shows a schematic cross-sectional structure of a pixel formed on an insulating substrate. As shown in the figure, the pixel includes a transistor part (a single TFT is illustrated in the figure) including a plurality of thin film transistors, a capacitor part such as a storage capacitor, and a light emitting part such as an organic EL element. A transistor portion and a capacitor portion are formed on a substrate by a TFT process, and a light emitting portion such as an organic EL element is laminated thereon. A transparent counter substrate is pasted thereon via an adhesive to form a flat panel.

  The display device according to the present invention includes a flat module-shaped display as shown in FIG. For example, a pixel array unit in which pixels made up of organic EL elements, thin film transistors, thin film capacitors and the like are integrated in a matrix is provided on an insulating substrate, and an adhesive is disposed so as to surround the pixel array unit (pixel matrix unit). Then, a counter substrate such as glass is attached to form a display module. If necessary, this transparent counter substrate may be provided with a color filter, a protective film, a light shielding film, and the like. For example, an FPC (flexible printed circuit) may be provided in the display module as a connector for inputting / outputting a signal to / from the pixel array unit from the outside.

  The display device according to the present invention described above has a flat panel shape and is input to an electronic device such as a digital camera, a notebook personal computer, a mobile phone, or a video camera, or an electronic device. It is possible to apply to the display of the electronic device of all fields which display the image signal produced | generated in the inside as an image or an image | video. Examples of electronic devices to which such a display device is applied are shown below.

  FIG. 11 shows a television to which the present invention is applied, which includes a video display screen 11 including a front panel 12, a filter glass 13, and the like, and is manufactured by using the display device of the present invention for the video display screen 11. .

  FIG. 12 shows a digital camera to which the present invention is applied, in which the top is a front view and the bottom is a rear view. This digital camera includes an imaging lens, a light emitting unit 15 for flash, a display unit 16, a control switch, a menu switch, a shutter 19, and the like, and is manufactured by using the display device of the present invention for the display unit 16.

  FIG. 13 shows a notebook personal computer to which the present invention is applied. The main body 20 includes a keyboard 21 that is operated when inputting characters and the like, and the main body cover includes a display unit 22 that displays an image. This display device is used for the display portion 22.

  FIG. 14 shows a mobile terminal device to which the present invention is applied. The left side shows an open state and the right side shows a closed state. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub-display 27, a picture light 28, a camera 29, and the like, and includes the display device of the present invention. The display 26 and the sub-display 27 are used.

  FIG. 15 shows a video camera to which the present invention is applied. The video camera includes a main body 30, a lens 34 for photographing a subject, a start / stop switch 35 at the time of photographing, a monitor 36, etc. on the side facing forward. It is manufactured by using the device for its monitor 36.

1 is a block diagram showing an overall configuration of an image display device according to the present invention. It is a circuit diagram which shows the pixel formed in the image display apparatus shown in FIG. 3 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 2. It is a graph explaining the mobility correction | amendment operation | movement of an image display apparatus. 1 is a circuit diagram showing a first embodiment of an image display apparatus according to the present invention. It is a timing chart with which it uses for operation | movement description of 1st Embodiment. It is a circuit diagram which shows 2nd Embodiment of the image display apparatus concerning this invention. It is a timing chart with which it uses for operation | movement description of 2nd Embodiment. It is sectional drawing which shows the device structure of the display apparatus concerning this invention. It is a top view which shows the module structure of the display apparatus concerning this invention. It is a perspective view which shows the television set provided with the display apparatus concerning this invention. It is a perspective view which shows the digital still camera provided with the display apparatus concerning this invention. 1 is a perspective view illustrating a notebook personal computer including a display device according to the present invention. It is a schematic diagram which shows the portable terminal device provided with the display apparatus concerning this invention. It is a perspective view which shows the video camera provided with the display apparatus concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array part, 2 ... Pixel, 3 ... Horizontal selector, 4 ... Write scanner, 5 ... Drive scanner, 71 ... First correction scanner, 72 ... 1st Double correction scanner, Tr1... Sampling transistor, Tr2... First switching transistor, Tr3... Second switching transistor, Tr4... Third switching transistor, Trd. Retention capacity, EL ... Light emitting element, WS ... Scanning line, AZ1 ... Scanning line, AZ2 ... Scanning line, DS ... Scanning line, A ... Drive unit, B ... Drive Part, C ... light emitting part

Claims (4)

It consists of row-like scanning lines, column-like signal lines, and matrix-like pixels arranged at the intersection of each scanning line and each signal line,
Each pixel is divided into a light emitting unit including a light emitting element and a driving unit for driving the light emitting element.
The drive unit includes at least a sampling transistor, a drive transistor, and a storage capacitor,
The sampling transistor has a control end connected to the scanning line, a pair of current ends connected between the signal line and the control end of the drive transistor,
The drive transistor has one of a pair of current ends connected to a power source and the other connected to the light emitting element,
The storage capacitor is connected to the control terminal of the drive transistor,
The sampling transistor is turned on in response to a control signal supplied from the scanning line, samples a video signal supplied from the signal line, and writes it to the storage capacitor,
The drive transistor is a display device that supplies a drive current corresponding to a video signal written to the storage capacitor to the light emitting element,
The display device is characterized in that the pixel includes two drive units for one light emitting element, and simultaneously supplies a drive current from two drive transistors to one light emitting element. The pixel operates in a light emitting period and a non-light emitting period,
Each drive unit has a storage capacitor connected between the control terminal and the current terminal of the drive transistor,
A video signal is written to the holding capacitor in a non-light emitting period, and the drive current is negatively fed back to the holding capacitor for a predetermined correction time to apply a correction for the mobility of the drive transistor to the video signal held in the holding capacitor,
The display device according to claim 1, wherein each driving unit simultaneously supplies a driving current to the light emitting element in accordance with the corrected video signal when the light emitting period starts. The drive transistor included in each drive unit is half the transistor size compared to the transistor size set when a single drive transistor supplies drive current to one light emitting element,
While combining the drive currents supplied by the drive transistors included in the two drive units and supplying the required drive current to one light emitting element,
2. The display device according to claim 1, wherein both drive transistors are used together, and the characteristic variation is averaged within the pixel.   An electronic device comprising the display device according to claim 1.

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