JP2008277475A5 - - Google Patents

Claims (5)

Forming an island-like semiconductor layer,
Forming a first insulating layer on the semiconductor layer;
Selectively etching the first insulating layer to locally expose the semiconductor layer;
Etching the surface of the semiconductor layer in the exposed region to locally thin the semiconductor layer;
Forming a second insulating layer on the thinned region of the semiconductor layer and the remaining first insulating layer;
Forming a conductive layer on the second insulating layer;
Forming a third insulating layer having a planarized surface using a coating method on the conductive layer;
Etching the third insulating layer and the conductive layer at substantially the same etching rate until the second insulating layer formed on the first insulating layer or the first insulating layer is exposed. , Forming the gate electrode by leaving the conductive layer in the thinned region of the semiconductor layer,
Etching the second insulating layer and the first insulating layer or the first insulating layer using the gate electrode as a mask exposes the semiconductor layer in a region that does not overlap the gate electrode;
An impurity element is added to the semiconductor layer using the gate electrode as a mask, a pair of impurity regions are formed in a self-aligned manner, and a channel formation region is formed between the pair of impurity regions ,
The method for manufacturing a semiconductor device is characterized in that the channel formation region is thinner than the pair of impurity regions . Forming an island-like semiconductor layer,
Forming a first insulating layer on the semiconductor layer;
Selectively etching the first insulating layer to locally expose the semiconductor layer;
By etching the surface of the semiconductor layer in the exposed region, the semiconductor layer is locally thinned,
Forming a second insulating layer on the thinned region of the semiconductor layer and the remaining first insulating layer;
Forming a conductive layer on the second insulating layer;
Forming a third insulating layer having a planarized surface using a coating method on the conductive layer;
Etching the third insulating layer and the conductive layer at substantially the same etching rate until the second insulating layer formed on the first insulating layer or the first insulating layer is exposed. , Forming the gate electrode by leaving the conductive layer in the thinned region of the semiconductor layer,
Etching the second insulating layer and the first insulating layer or the first insulating layer using the gate electrode as a mask exposes the semiconductor layer in a region that does not overlap the gate electrode;
An impurity element is added to the semiconductor layer using the gate electrode as a mask, a pair of impurity regions are formed in a self-aligned manner, and a channel formation region is formed between the pair of impurity regions,
Forming a fourth insulating layer covering the semiconductor layer and the gate electrode;
By anisotropically etching the fourth insulating layer, a sidewall insulating layer is formed on the side wall of the gate electrode, and a part of the impurity region formed in the semiconductor layer is exposed,
Forming a metal layer on the exposed impurity region;
By performing heat treatment, a silicide region is formed in the impurity region ,
The method for manufacturing a semiconductor device, wherein the channel formation region is thinner than the impurity region . In claim 2,
The metal layer is formed using a metal element selected from nickel, titanium, cobalt, or platinum, or an alloy material containing the metal element. In any one of Claim 1 thru | or 3,
The third insulating layer is formed using a coating method selected from a spin coating method, a scanning method, and an ink jet method. In any one of Claims 1 thru | or 4,
The method for manufacturing a semiconductor device is characterized in that the channel formation region is formed with a thickness of 5 nm to 50 nm.