JP2008270625A - Method for manufacturing ferroelectric memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a ferroelectric memory device having satisfactory characteristics. <P>SOLUTION: An MOS type transistor 3 is formed in an MOS type transistor region 1b of a semiconductor substrate 1, and an inter-layer layer 4 is formed in the MOS type transistor region 1b and a ferroelectric gate FET region 1a of the semiconductor substrate 1, and the ferroelectric gate FET region 1a of the inter-layer layer 4 is opened, and the ferroelectric gate FET 6 is formed in an opening 5 of the ferroelectric gate FET region 1a. Thus, it is possible to manufacture the ferroelectric memory device whose reliability is improved. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a ferroelectric memory device, and more particularly to a method for manufacturing a ferroelectric memory device including a MOS transistor and a ferroelectric gate transistor using a ferroelectric layer in the gate portion of a field effect transistor.

  A 1T (Transistor) type strong transistor composed of one ferroelectric gate transistor (hereinafter referred to as a ferroelectric gate FET (Field Effect Transistor)) in which a ferroelectric layer is used for the gate portion of the field effect transistor. The dielectric memory device is characterized by being capable of miniaturization and non-destructive reading as compared with the conventional 1T · 1C (Capacitor) type ferroelectric memory device. Has been developed.

  On the other hand, the ferroelectric layer in the gate portion of the ferroelectric gate FET is formed on a silicon (Si) substrate (this is referred to as “MFS (Metal / Ferroelectric / Semiconductor) structure”). For this reason, during the heat treatment for crystallizing the ferroelectric layer for forming the ferroelectric gate FET, metal atoms of the ferroelectric layer diffuse into the Si substrate, and the interface between the ferroelectric layer and the Si substrate. As a result, it was impossible to obtain good characteristics.

  Therefore, a buffer layer is formed between the ferroelectric layer and the Si substrate (this is called “MFIS (Metal / Ferroelectric / Insulator / Semiconductor) structure”). In other words, the formed buffer layer prevents the diffusion of metal atoms in the ferroelectric layer into the Si substrate, whereby the stable characteristics of the ferroelectric gate FET can be obtained.

Note that an insulator material having a low leakage current, a high dielectric constant, and a characteristic stability at high temperature is used for the buffer layer in order to improve device characteristics. As a material satisfying these characteristics, a high dielectric constant (high-k) gate insulating film such as hafnium oxide (HfO ₂ ) has been applied.

  In order to manufacture a ferroelectric memory device, peripheral circuits such as MOS (Metal-Oxide-Semiconductor) FETs are mounted along with ferroelectric gate FETs using such a high dielectric constant gate insulating film. It is necessary (see, for example, Patent Document 1).

  However, in such a ferroelectric memory device, it is very difficult to form the ferroelectric gate FET and the MOSFET simultaneously because the materials constituting the ferroelectric gate FET and the MOSFET are greatly different. .

Therefore, a method has been considered in which a MOSFET is formed first and then a ferroelectric gate FET is formed.
An outline of manufacturing a ferroelectric memory device in which a MOSFET is mounted together with a ferroelectric gate FET will be described below.

10 to 14 are schematic sectional views of a conventional method for manufacturing a ferroelectric memory device.
First, an element isolation region 102 is formed on a P-type Si substrate 101, and a ferroelectric gate FET region 100a and a MOSFET region 100b are provided (FIG. 10A).

  In the ferroelectric gate FET region 100a, a resist 103 having an N-well pattern is formed on the P-type Si substrate 101 by a lithography process. Then, for example, phosphorus (P) ions are implanted into the opening to form the N-well 104 (FIG. 10B).

In the MOSFET region 100b, after removing the resist 103, silicon oxide (SiO ₂ ) is formed as a gate insulating film in the active region on the P-type Si substrate 101, and polycrystalline silicon (Polysilicon) is formed as a gate electrode thereon. -Si).

After pattern formation by a lithography process, etching is performed to form sidewalls, whereby a gate portion 105 is formed (FIG. 11A).
In the MOSFET region 100b, a resist 103a having a pattern for an N-type conductive region is formed by a lithography process, and, for example, arsenic (As) ions are implanted into the opening to form an N-type conductive region 106 (FIG. 11 ( B)).

  In the ferroelectric gate FET region 100a, a resist 103b having a pattern for a P-type conductive region is formed by a lithography process, and, for example, boron (B) ions are implanted into the opening to form a P-type conductive region 107. (FIG. 12 (A)).

In the ferroelectric gate FET region 100a and the MOSFET region 100b, the resist 103b is removed, and the entire surface is formed by using, for example, a CVD (Chemical Vapor Deposition) method using HfO ₂ as the buffer layer 108. After the formation of the buffer layer 108, an annealing process is performed, and a bismuth strontium tantalate (SBT) film, for example, is formed as a ferroelectric layer 109 on the entire surface of the buffer layer 108 by using a CVD method or the like and crystallized. . Further, an electrode 110 is formed on the entire surface of the ferroelectric layer 109 (FIG. 12B).

  An electrode pattern resist 103c is formed on the entire surface of the electrode 110 by a lithography process, and the electrode 110 and the ferroelectric layer 109 are etched using RIE (Reactive Ion Etching) (FIG. 13A).

  The resist 103c is removed and an annealing process is performed. An interlayer layer 111 is formed on the entire surface by, for example, a low temperature CVD method, and the surface of the interlayer layer 111 is planarized by CMP (Chemical Mechanical Polishing) (FIG. 13B).

A contact hole 112a is formed in the interlayer 111 using the contact hole resist 103d for connection to the source and drain as a mask (FIG. 14A).
A wiring 112 is formed using aluminum (Al) in the contact hole 112a formed in the interlayer 111 (FIG. 14B).

Through the above steps, a general ferroelectric memory device configured by mounting a MOSFET together with a ferroelectric gate FET is manufactured.
JP 2003-68890 A

  However, in the process of manufacturing such a ferroelectric memory device, when etching the electrodes and the ferroelectric layer constituting the ferroelectric gate FET, the surface of the MOSFET is also etched, and the MOSFET is damaged. As a result, the characteristics of the MOSFET deteriorate, and as a result, the characteristics of the ferroelectric memory device deteriorate.

  The present invention has been made in view of these points, and an object thereof is to provide a method for manufacturing a ferroelectric memory device having good characteristics.

  In the present invention, in order to solve the above problems, in a method for manufacturing a ferroelectric memory device including a MOS transistor 3 and a ferroelectric gate FET 6 using a ferroelectric layer in the gate portion of a field effect transistor, FIG. As shown in FIG. 2, a step of forming a MOS transistor 3 in the MOS transistor region 1b of the semiconductor substrate 1 and an interlayer layer 4 in the MOS transistor region 1b and the ferroelectric gate FET region 1a of the semiconductor substrate 1 are formed. A step of opening the ferroelectric gate FET region 1a of the interlayer layer 4, and a step of forming the ferroelectric gate FET 6 in the opening 5 of the ferroelectric gate FET region 1a. A method for manufacturing a ferroelectric memory device is provided.

  According to such a method of manufacturing a ferroelectric memory device, the MOS transistor is formed in the MOS transistor region of the semiconductor substrate, and the interlayer layer is formed in the MOS transistor region and the ferroelectric gate FET region of the semiconductor substrate. Then, the ferroelectric gate FET region in the interlayer layer is opened, and the ferroelectric gate FET is formed in the opening of the ferroelectric gate FET region.

  In the present invention, the MOS transistor is formed in the MOS transistor region of the semiconductor substrate, the interlayer layer is formed in the MOS transistor region and the ferroelectric gate FET region of the semiconductor substrate, and the ferroelectric gate FET region of the interlayer layer is formed. The ferroelectric gate FET is formed in the opening of the ferroelectric gate FET region. As a result, damage to the surface of the MOS transistor can be reduced, and the buffer layer existing between the semiconductor substrate and the interlayer film and the ferroelectric film serves as a barrier layer that prevents deterioration of the characteristics of the ferroelectric film. A ferroelectric memory device with improved reliability can be manufactured.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, after describing the outline of the present invention, embodiments will be described. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

FIG. 1 is a conceptual diagram of the present invention.
FIG. 1 conceptually shows a manufacturing process of a ferroelectric memory device using the manufacturing method of the present invention. A method for manufacturing a ferroelectric memory device according to the present invention will be described below with reference to FIG.

First, a ferroelectric gate FET region 1a and a MOS transistor region 1b are provided on the semiconductor substrate 1 by the element isolation region 2.
In the ferroelectric gate FET region 1a, a well region and a conductive region for the ferroelectric gate FET 6 to be formed later are formed.

On the other hand, the MOS transistor 3 is formed in the MOS transistor region 1b (FIG. 1A).
An interlayer 4 is formed on the entire surface of the ferroelectric gate FET region 1a and the MOS transistor region 1b (FIG. 1B).

An opening 5 is formed in the ferroelectric gate FET region 1a of the interlayer 4 formed on the entire surface of the ferroelectric gate FET region 1a and the MOS transistor region 1b (FIG. 1C).
A ferroelectric gate FET 6 is formed in the opening 5 of the interlayer layer 4 (FIG. 1D).

  A wiring process is performed on the ferroelectric gate FET 6 and the MOS transistor 3 formed as described above, and a ferroelectric memory device in which the MOS transistor 3 is mounted together with the ferroelectric gate FET 6 is completed.

  As already described, in the conventional method for manufacturing a ferroelectric memory device, an MOS transistor and a ferroelectric gate FET are formed in this order, and then an interlayer is formed. However, in this conventional manufacturing method, after the formation of the MOS transistor, the ferroelectric layer constituting the ferroelectric gate FET is etched. At this time, even the surface of the MOS transistor is etched, and the MOS transistor is damaged, so that the characteristics of the ferroelectric memory device are deteriorated.

  On the other hand, in the method for manufacturing a ferroelectric memory device of the present invention, an interlayer layer and a ferroelectric gate FET are sequentially formed on a semiconductor substrate on which a MOS transistor has been formed. In the manufacturing method of the present invention, since the interlayer layer is formed on the entire surface of the semiconductor substrate including the previously formed MOS type transistor, damage to the MOS type transistor caused by forming the ferroelectric gate FET is reduced. This can be reduced by the interlayer. Therefore, it is possible to reduce the damage to the MOS transistor and form the ferroelectric gate FET. Therefore, it is possible to manufacture a ferroelectric memory device having good characteristics.

Next, two embodiments using the outline of the present embodiment will be described.
First, the first embodiment will be described.
2 to 7 are schematic cross-sectional views of the method of manufacturing the ferroelectric memory device according to the first embodiment.

  First, by forming an element isolation region 12 on a P-type conductive Si substrate (hereinafter referred to as a P-type Si substrate 11), a ferroelectric gate FET according to two types of transistors to be formed later. Region 11a and MOSFET region 11b are set (FIG. 2A).

  An N-well pattern is formed in the ferroelectric gate FET region 11a by a lithography process on the P-type Si substrate 11 in which the ferroelectric gate FET region 11a and the MOSFET region 11b are set. Then, using the resist 13 covering the MOSFET region 11b as a mask, for example, P ions are implanted to form an N-well 14 (FIG. 2B).

After removing the resist 13, a SiO ₂ film (thickness: 7 nm) is formed as a gate film as an active region in the MOSFET region 11b, and a Poly-Si film (thickness: 180 nm) is formed thereon as a gate electrode. Form.

  After a pattern is formed on the Poly-Si film by a lithography process, etching is performed using the pattern as a mask, and a sidewall is formed to form the gate portion 15 (FIG. 3A).

  Furthermore, a pattern for an N-type conductive region is formed in the MOSFET region 11b by a lithography process. Then, using the resist 13a covering the ferroelectric gate FET region 11a as a mask, for example, As ions are implanted to form the N-type conductive region 16 (FIG. 3B).

  After removing the resist 13a, a pattern for a P-type conductive region is formed again in the ferroelectric gate FET region 11a by a lithography process. Then, using the resist 13b covering the MOSFET region 11b as a mask, for example, B ions are implanted to form the P-type conductive region 17 (FIG. 4A).

In addition, after removing the resist 13b, in order to activate the N-well 14, the N-type conductive region 16, and the P-type conductive region 17, for example, a thermal annealing process is performed at 1000 ° C.
After the thermal annealing process, an interlayer layer 18 (thickness: 300 nm) is formed on the entire surface of the ferroelectric gate FET 11a and the MOSFET 11b by using, for example, a thermal CVD method, and a planarization process is performed by the CMP method (FIG. 4). (B)).

  After the planarization process, a pattern is formed in the ferroelectric gate FET region 11a by a lithography process. Using the resist 13c having the opening 19 as a mask, the interlayer layer 18 is etched to expose the P-type Si substrate 11 (FIG. 5A).

  After removing the resist 13c, hafnium nitride silicate (HfSiON) is formed as a buffer layer 20 (thickness: 4 nm) on the entire surface of the P-type Si substrate 11 including the opening 19 by using, for example, a CVD method.

Even if HfO ₂ , hafnium aluminate (HfAlO), HfO ₂ / HfSiON, HfO ₂ / HfAlO is used for the buffer layer 20 instead of HfSiON, the same effect as HfSiON can be obtained. Further, instead of the CVD method of forming, a film can be similarly formed by an e-beam method or the like.

After the thermal annealing process is performed on the buffer layer 20, an SBT film is formed as a ferroelectric layer 21 (thickness: 300 nm) by using, for example, a CVD method (FIG. 5B).
Note that the same effect as that of the SBT film can be obtained even if a bismuth lanthanum titanate (BLT) film, a bismuth niobium titanate (BNT) film, or the like is formed on the ferroelectric layer 21 instead of the SBT film. Further, instead of the CVD method, the film can be formed similarly by a sol-gel method, a sputtering method, or the like.

  By the way, when using the sol-gel method, the sol-gel solution is spin-coated, dried at a temperature of 240 ° C. for about 5 minutes, and then heated at a temperature of 750 ° C. for about 1 minute with a rapid heating apparatus (for example, an RTA furnace). To do. By repeating this process (coating → drying → heating) five or six times, an SBT film having a film thickness of 300 nm can be formed. After forming the film, the SBT film is crystallized by heating at a temperature of 750 ° C. for about 30 minutes in an oxygen atmosphere.

After the formation of the ferroelectric layer 21, the ferroelectric layer 21 on the interlayer layer 18 is removed (FIG. 6A).
As a removal method, etching by RIE using argon (Ar) -chlorine (Cl ₂ ) gas (flow ratio: Ar: Cl ₂ = 2: 1, gas pressure: 10 mTorr, Rf Power: 600 W), or CMP For example, the ferroelectric layer 21 can be removed. In the present embodiment, an example is shown in which the buffer layer 20 is left on the interlayer film 18, but both the ferroelectric layer 21 and the buffer layer 20 are removed in the process of removing the ferroelectric layer 21. It may be.

  After removing the ferroelectric layer 21 on the interlayer 18, an upper electrode is formed on the ferroelectric layer 21 a by using, for example, platinum (Pt), for example, by sputtering or electron beam evaporation. A pattern of the upper electrode is formed by a lithography process, and unnecessary portions are etched using the formed resist (not shown) as a mask to form the upper electrode 22 (FIG. 6B).

In order to remove damage to the ferroelectric layer 21a due to etching for forming the upper electrode 22, recovery annealing is performed at a temperature of 750 ° C. for about 30 minutes, for example, in an oxygen (O ₂ ) atmosphere. .

  After the recovery annealing, a wiring pattern is formed by a lithography process for the wiring process. Using the formed resist 13d as a mask, the interlayer layer 18 is etched and wiring to the source and drain regions (N-type conductive region 16 or P-type conductive region 17) of the gate is performed. Express (FIG. 7A).

After the etching, the wiring 23 is formed with an Al film (FIG. 7B).
Through the above steps, a ferroelectric memory device in which the wiring 23 is formed is manufactured.
Next, a second embodiment will be described.

  In the second embodiment, a case where a dummy gate portion is formed in the ferroelectric gate FET region 11a simultaneously with the formation of the gate portion 15 in the first embodiment will be described as an example.

8 and 9 are schematic cross-sectional views of a method for manufacturing a ferroelectric memory device according to the second embodiment.
In the manufacturing method of the second embodiment, the steps used in the first embodiment (FIGS. 2, 5 to 7) are the same as those used in the first embodiment. The same reference numerals as those in the first embodiment are used.

  First, by forming the element isolation region 12 on the P-type Si substrate 11, the ferroelectric gate FET region 11a and the MOSFET region 11b are set according to two types of transistors to be formed later (FIG. 2A). ).

  An N-well pattern is formed in the ferroelectric gate FET region 11a by a lithography process on the P-type Si substrate 11 in which the ferroelectric gate FET region 11a and the MOSFET region 11b are set. Then, using the resist 13 covering the MOSFET region 11b as a mask, for example, P ions are implanted to form an N-well 14 (FIG. 2B).

After the resist 13 is removed, a SiO ₂ film (thickness: 7 nm) is formed as a gate film which is an active region in the ferroelectric gate FET region 11a and the MOSFET region 11b, and a Poly- A Si film (thickness: 180 nm) is formed.

  After a pattern is formed on the Poly-Si film by a lithography process, etching is performed using the pattern as a mask, and sidewalls are further formed to form dummy gate portions 15a and gate portions 15 (FIG. 8A).

  Furthermore, a pattern for an N-type conductive region is formed in the MOSFET region 11b by a lithography process. Then, using the resist 13a covering the dummy gate portion 15a in the ferroelectric gate FET region 11a as a mask, for example, As ions are implanted to form the N-type conductive region 16 (FIG. 8B).

  After removing the resist 13a, a pattern for a P-type conductive region is formed again in the ferroelectric gate FET region 11a by a lithography process. Then, using the resist 13b covering the MOSFET region 11b as a mask, for example, B ions are implanted to form the P-type conductive region 17 (FIG. 9A).

In addition, after removing the resist 13b, in order to activate the N-well 14, the N-type conductive region 16, and the P-type conductive region 17, for example, a thermal annealing process is performed at 1000 ° C.
After the thermal annealing process, an interlayer 18 (thickness: 300 nm) is formed on the entire surface of the ferroelectric gate FET 11a and the MOSFET 11b by using, for example, a thermal CVD method, and a planarization process is performed by the CMP method (FIG. 9). (B)).

  After the planarization process, a pattern is formed in the ferroelectric gate FET region 11a by a lithography process. Using the resist 13c having the opening 19 as a mask, the dummy gate portion 15a and the interlayer layer 18 are etched to expose the P-type Si substrate 11 (FIG. 5A).

After removing the resist 13c, HfSiON is formed as a buffer layer 20 (thickness: 4 nm) on the entire surface of the P-type Si substrate 11 including the opening 19 by using, for example, a CVD method.
Even if HfO ₂ , HfAlO, HfO ₂ / HfSiON, HfO ₂ / HfAlO is used for the buffer layer 20 instead of HfSiON, the same effect as HfSiON can be obtained. Further, instead of the CVD method of forming, a film can be similarly formed by an e-beam method or the like.

Thereafter, the same process (FIGS. 6 and 7) as in the first embodiment is performed to manufacture a ferroelectric memory device in which wiring is formed.
As described above, in the method for manufacturing a ferroelectric memory device according to the present invention, the interlayer layer and the ferroelectric gate FET are sequentially formed on the semiconductor substrate on which the MOS transistor has been formed. In the manufacturing method of the present invention, since the interlayer layer is formed on the entire surface of the semiconductor substrate including the previously formed MOS type transistor, damage to the MOS type transistor caused by forming the ferroelectric gate FET is reduced. This can be reduced by the interlayer. Therefore, it is possible to reduce the damage to the MOS transistor and form the ferroelectric gate FET. In addition, since the buffer layer that exists between the semiconductor substrate and interlayer film and the ferroelectric film serves as a barrier layer that prevents deterioration of the characteristics of the ferroelectric film, the ferroelectric gate FET with improved reliability can be formed. Is possible. Therefore, it is possible to manufacture a ferroelectric memory device having good characteristics.

It is a conceptual diagram of this invention. It is a cross-sectional schematic diagram (the 1) of the manufacturing method of the ferroelectric memory device in 1st Embodiment. FIG. 6 is a schematic cross-sectional view (No. 2) of the method for manufacturing the ferroelectric memory device in the first embodiment. FIG. 6 is a schematic cross-sectional view (No. 3) of the method for manufacturing the ferroelectric memory device in the first embodiment. FIG. 6 is a schematic cross-sectional view (No. 4) of the method for manufacturing the ferroelectric memory device in the first embodiment. FIG. 10 is a schematic cross-sectional view (No. 5) of the method for manufacturing the ferroelectric memory device in the first embodiment. FIG. 6 is a schematic cross-sectional view (No. 6) of the method for manufacturing the ferroelectric memory device in the first embodiment. It is a cross-sectional schematic diagram (the 1) of the manufacturing method of the ferroelectric memory device in 2nd Embodiment. It is a cross-sectional schematic diagram (the 2) of the manufacturing method of the ferroelectric memory device in 2nd Embodiment. It is a cross-sectional schematic diagram (No. 1) of a conventional method for manufacturing a ferroelectric memory device. It is a cross-sectional schematic diagram (No. 2) of the manufacturing method of the conventional ferroelectric memory device. It is a cross-sectional schematic diagram (the 3) of the manufacturing method of the conventional ferroelectric memory device. It is a cross-sectional schematic diagram (the 4) of the manufacturing method of the conventional ferroelectric memory device. It is a cross-sectional schematic diagram (the 5) of the manufacturing method of the conventional ferroelectric memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Ferroelectric gate FET area | region 1b MOS type transistor area | region 2 Element isolation area | region 3 MOS type transistor 4 Interlayer 5 Opening part 6 Ferroelectric gate FET

Claims (7)

In a method for manufacturing a ferroelectric memory device comprising a MOS type transistor and a ferroelectric gate transistor using a ferroelectric layer in a gate portion of a field effect transistor,
Forming the MOS transistor in the MOS transistor region of the semiconductor substrate;
Forming an interlayer in the MOS transistor region and the ferroelectric gate transistor region of the semiconductor substrate;
Opening the ferroelectric gate transistor region of the interlayer layer;
Forming the ferroelectric gate transistor in the opening of the ferroelectric gate transistor region;
A method for manufacturing a ferroelectric memory device, comprising:   2. The ferroelectric memory device according to claim 1, wherein the MOS transistor is formed in the MOS transistor region, and a dummy MOS transistor is formed in the ferroelectric gate transistor region. Production method.   3. The method of manufacturing a ferroelectric memory device according to claim 1, wherein the ferroelectric gate transistor has a buffer layer between the semiconductor substrate and the ferroelectric layer.   4. The method of manufacturing a ferroelectric memory device according to claim 3, wherein the buffer layer uses hafnium oxide, hafnium nitride silicate, hafnium aluminate, hafnium oxide and hafnium silicate, or hafnium oxide and hafnium aluminate. Method.   5. The method of manufacturing a ferroelectric memory device according to claim 4, wherein the buffer layer is formed using a CVD method or an e-beam method.   4. The method of manufacturing a ferroelectric memory device according to claim 3, wherein the ferroelectric layer uses bismuth strontium titanate, bismuth lanthanum titanate, and bismuth niobium titanate.   7. The method of manufacturing a ferroelectric memory device according to claim 6, wherein the ferroelectric layer is formed using a CVD method, a sol-gel method, or a sputtering method.

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