JP2008270597A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2008270597A
JP2008270597A JP2007112922A JP2007112922A JP2008270597A JP 2008270597 A JP2008270597 A JP 2008270597A JP 2007112922 A JP2007112922 A JP 2007112922A JP 2007112922 A JP2007112922 A JP 2007112922A JP 2008270597 A JP2008270597 A JP 2008270597A
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package
substrate
chip
chips
semiconductor device
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Tetsuya Yamamoto
本 哲 也 山
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To reduce an inter-terminal short circuit between terminals connecting an upper-stage package and a lower-stage package by decreasing the height of a stacked package. <P>SOLUTION: The semiconductor device has the upper-stage package P2 which has a substrate 21 and a chip 23 formed on a top surface of the substrate 21 and also has a hole H formed in an area blow the chip 23 on the substrate 21; the lower-stage package P1 which has a substrate 11 and a chip 13 mounted on a top surface of the substrate 11; and a conductive ball 1 provided between a reverse surface of the substrate 21 and the top surface of the substrate 11 to electrically connect the upper-stage package P2 and lower-stage package P1 to each other, the chip 13 being disposed below the hole H. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置に関するものである。   The present invention relates to a semiconductor device.

近年、電子機器の小型化、薄型化に伴い、電子機器内に搭載される半導体装置に対する小型化、薄型化の要求が高まっている。このような要求に応える手段の１つとしてＢＧＡ（Ball Grid Array）やＬＧＡ（Land Grid Array）のような半導体パッケージを複数積層し、上段パッケージと下段パッケージとをはんだボール等の導電性ボールで電気的に結合する積層型パッケージが提案されている（例えば特許文献１参照）。   In recent years, with the downsizing and thinning of electronic devices, there is an increasing demand for downsizing and thinning of semiconductor devices mounted in the electronic devices. As one of the means to meet such a demand, a plurality of semiconductor packages such as BGA (Ball Grid Array) and LGA (Land Grid Array) are stacked, and the upper package and the lower package are electrically connected with conductive balls such as solder balls. A stacked package that can be coupled to each other has been proposed (see, for example, Patent Document 1).

また、このような積層型パッケージの総厚を小さくする要求が強く、そのため、パッケージの各部位を薄くする必要がある。しかし、パッケージの基板に搭載されるチップの薄厚加工はチップクラック等の問題を生じ、基板の薄厚化はパッケージ製造工程でのフレーム曲折等の問題を生じる虞がある。   In addition, there is a strong demand for reducing the total thickness of such a stacked package, and therefore it is necessary to make each part of the package thinner. However, thin processing of the chip mounted on the substrate of the package may cause problems such as chip cracks, and thinning the substrate may cause problems such as frame bending in the package manufacturing process.

また、電子機器の高機能化の要求によりチップの搭載数が増加し、下段パッケージが厚くなる。これにより上段パッケージと下段パッケージを接続する導電性ボールが大きくなり、隣接端子間のショート不良が増加する虞がある。
特開２０００−２９９４３３号公報 In addition, the number of mounted chips increases due to the demand for higher functionality of electronic devices, and the lower package becomes thicker. As a result, the conductive ball connecting the upper package and the lower package becomes large, and there is a possibility that short-circuit defects between adjacent terminals may increase.
JP 2000-299433 A

本発明は積層型パッケージの高さを低減し、上段パッケージと下段パッケージを接続する端子の端子間ショート不良を低減できる半導体装置を提供することを目的とする。   It is an object of the present invention to provide a semiconductor device that can reduce the height of a stacked package and reduce short-circuit defects between terminals of an upper package and a lower package.

本発明の一態様による半導体装置は、第１の基板及び前記第１の基板上面に搭載された第１のチップを有し、前記第１の基板の前記チップ下方領域にホールが形成されている第１のパッケージと、第２の基板及び前記第２の基板上面に搭載された第２のチップを有する第２のパッケージと、前記第１の基板下面と前記第２の基板上面との間に設けられ、前記第１のパッケージと前記第２のパッケージとを電気的に接続する導電性ボールと、を備え、前記第２のパッケージの上部が前記ホール内に配置されるものである。   A semiconductor device according to one embodiment of the present invention includes a first substrate and a first chip mounted on an upper surface of the first substrate, and a hole is formed in the lower region of the chip of the first substrate. A first package; a second package having a second substrate and a second chip mounted on the upper surface of the second substrate; and a lower surface of the first substrate and an upper surface of the second substrate. And a conductive ball that electrically connects the first package and the second package, and an upper portion of the second package is disposed in the hole.

また、本発明の一態様による半導体装置は、第１の基板及び前記第１の基板上面に搭載された第１のチップを有し、前記第１の基板の下面の所定領域に凹部が形成されている第１のパッケージと、第２の基板及び前記第２の基板上面に搭載された第２のチップを有する第２のパッケージと、前記第１の基板下面と前記第２の基板上面との間に設けられ、前記第１のパッケージと前記第２のパッケージとを電気的に接続する導電性ボールと、を備え、前記第２のパッケージの上部が前記凹部内に配置されるものである。   A semiconductor device according to one embodiment of the present invention includes a first substrate and a first chip mounted on the upper surface of the first substrate, and a recess is formed in a predetermined region of the lower surface of the first substrate. A second package having a second substrate and a second chip mounted on the upper surface of the second substrate, a lower surface of the first substrate, and an upper surface of the second substrate Conductive balls provided between the first package and the second package are provided, and an upper part of the second package is disposed in the recess.

また、本発明の一態様による半導体装置は、積層された複数の第１のチップと、上面に前記積層された複数の第１のチップが搭載された第１の基板と、前記第１の基板と前記複数の第１のチップとを電気的に接続する複数の第１のワイヤと、前記複数の第１のチップ及び前記複数の第１のワイヤを封止する第１のモールド樹脂と、を有し、前記第１の基板の下面の所定領域に凹部が形成されている第１のパッケージと、積層された複数の第２のチップと、上面に前記積層された複数の第２のチップが搭載された第２の基板と、前記第２の基板と前記複数の第２のチップとを電気的に接続する複数の第２のワイヤと、前記複数の第２のチップ及び前記複数の第２のワイヤを封止する第２のモールド樹脂と、を有する第２のパッケージと、前記第１の基板下面と前記第２の基板上面との間に設けられ、前記第１のパッケージと前記第２のパッケージとを電気的に接続する導電性ボールと、を備え、前記第２のモールド樹脂の上部が前記凹部内に配置されるものである。   A semiconductor device according to one embodiment of the present invention includes a plurality of stacked first chips, a first substrate on which the plurality of stacked first chips are mounted, and the first substrate. And a plurality of first wires that electrically connect the plurality of first chips, and a first mold resin that seals the plurality of first chips and the plurality of first wires. A first package having a recess formed in a predetermined region of the lower surface of the first substrate; a plurality of second chips stacked; and a plurality of second chips stacked on the upper surface. A mounted second substrate, a plurality of second wires that electrically connect the second substrate and the plurality of second chips, the plurality of second chips, and the plurality of second chips. A second mold resin that seals the second wire, and the second package A conductive ball provided between the lower surface of the substrate and the upper surface of the second substrate and electrically connecting the first package and the second package; The upper part is disposed in the recess.

本発明によれば、積層型パッケージの高さを低減し、上段パッケージと下段パッケージを接続する端子の端子間ショート不良を低減できる。   According to the present invention, it is possible to reduce the height of the stacked package and reduce the short circuit between terminals of the terminals connecting the upper package and the lower package.

以下、本発明の実施の形態による半導体装置を図面に基づいて説明する。   Hereinafter, semiconductor devices according to embodiments of the present invention will be described with reference to the drawings.

図１に本発明の実施形態に係る半導体装置の概略構成を示す。半導体装置は下段側パッケージＰ１と上段側パッケージＰ２を備え、下段側パッケージＰ１と上段側パッケージＰ２は導電性ボール１により電気的に接続されている。導電性ボール１は例えばはんだボールである。   FIG. 1 shows a schematic configuration of a semiconductor device according to an embodiment of the present invention. The semiconductor device includes a lower package P1 and an upper package P2, and the lower package P1 and the upper package P2 are electrically connected by a conductive ball 1. The conductive ball 1 is, for example, a solder ball.

下段側パッケージＰ１はインターポーザー（基板）１１、インターポーザー１１の上面にダイボンディング材１２を介して搭載されたチップ１３、インターポーザー１１の上面に形成されたパッド１４とチップ１３を接続する導電性ワイヤ１５、チップ１３及び導電性ワイヤ１５を封止するモールド樹脂１６を有する。   The lower package P1 includes an interposer (substrate) 11, a chip 13 mounted on the upper surface of the interposer 11 via a die bonding material 12, and a pad 14 formed on the upper surface of the interposer 11 and a conductive material for connecting the chip 13 A mold resin 16 is provided to seal the wire 15, the chip 13, and the conductive wire 15.

同様に、上段側パッケージＰ２はインターポーザー２１、インターポーザー２１の上面にダイボンディング材２２を介して搭載されたチップ２３（チップ２３ａと２３ｂの積層構造）、インターポーザー２１の上面に形成されたパッド２４とチップ２３を接続する導電性ワイヤ２５、チップ２３及び導電性ワイヤ２５を封止するモールド樹脂２６を有する。   Similarly, the upper package P2 includes an interposer 21, a chip 23 (stacked structure of chips 23a and 23b) mounted on the upper surface of the interposer 21 via a die bonding material 22, and a pad formed on the upper surface of the interposer 21. 24 and a conductive resin 25 for connecting the chip 23 and a mold resin 26 for sealing the chip 23 and the conductive wire 25.

例えばチップ１３はＣＰＵ、チップ２３はメモリである。また、モールド樹脂１６、２６は例えばエポキシ樹脂である。   For example, the chip 13 is a CPU and the chip 23 is a memory. The mold resins 16 and 26 are, for example, epoxy resins.

上段側パッケージＰ２の下面、下段側パッケージＰ１の上面にはそれぞれ導電性ボール用ランド２が形成されており、対応する導電性ボール用ランド２間に導電性ボール１が形成される。   Conductive ball lands 2 are respectively formed on the lower surface of the upper package P2 and the upper surface of the lower package P1, and the conductive balls 1 are formed between the corresponding conductive ball lands 2.

下段側パッケージＰ１の下面には導電性ボール用ランド３、導電性ボール４が形成されており、マザーボード（図示せず）と下段側パッケージＰ１とを電気的に接続する。   Conductive ball lands 3 and conductive balls 4 are formed on the lower surface of the lower package P1 to electrically connect a mother board (not shown) and the lower package P1.

下段側パッケージＰ１、上段側パッケージＰ２にはそれぞれ導電性ボール用ランド２とパッド１４、２４を接続する配線（図示せず）が形成されており、配線上にはソルダーレジスト５が形成されている。ソルダーレジスト５は配線の腐食、隣接する異電位の配線間ショートを防止する。   A wiring (not shown) for connecting the conductive ball land 2 and the pads 14 and 24 is formed in the lower package P1 and the upper package P2, respectively, and a solder resist 5 is formed on the wiring. . The solder resist 5 prevents wiring corrosion and short-circuiting between adjacent wirings of different potentials.

上段側パッケージＰ２のインターポーザー２１はチップ２３下方部分にホールＨが形成されており、ホールＨに下段側パッケージＰ１のモールド樹脂１６が配置される。これにより、上段側パッケージＰ２のインターポーザー２１にホールＨが形成されていない場合と比較して、半導体装置の総厚をインターポーザー２１の厚さ分低減することができる。   The interposer 21 of the upper package P2 has a hole H formed in a lower portion of the chip 23, and the mold resin 16 of the lower package P1 is disposed in the hole H. Thereby, compared with the case where the hole H is not formed in the interposer 21 of the upper package P2, the total thickness of the semiconductor device can be reduced by the thickness of the interposer 21.

また、厚さが低減できるため、下段側パッケージＰ１と上段側パッケージＰ２とを接続する導電性ボール１、導電性ボール用ランド２のサイズを小さくすることができ、隣接端子間のショート不良を低減できる。また、単位面積当たりの設置端子数を多くすることができる。   Further, since the thickness can be reduced, the size of the conductive balls 1 and the conductive ball lands 2 that connect the lower package P1 and the upper package P2 can be reduced, and short-circuit defects between adjacent terminals can be reduced. it can. Moreover, the number of installation terminals per unit area can be increased.

図２（ａ）に示すように、チップ２３ａ、２３ｂ及び導電性ワイヤ２５をモールド樹脂２６で封止した後にドリル等でホールＨを形成することができる。また、図２（ｂ）に示すように、あらかじめホールＨを形成したインターポーザー２１上にチップ２３ａ、２３ｂを搭載し、上段側パッケージＰ２を形成するようにしても良い。また、チップ２３下面の周辺部のみにダイボンディング材を供給し、ホールＨを介してチップ２３下面が露出するようにしてもよい。ホールＨのサイズはインターポーザー２１上に搭載されるチップ２３ａのサイズよりも小さいものとなる。   As shown in FIG. 2A, after the chips 23a and 23b and the conductive wire 25 are sealed with the mold resin 26, the hole H can be formed with a drill or the like. Further, as shown in FIG. 2B, the chips 23a and 23b may be mounted on the interposer 21 in which the holes H are formed in advance to form the upper package P2. Alternatively, the die bonding material may be supplied only to the peripheral portion of the lower surface of the chip 23 so that the lower surface of the chip 23 is exposed through the hole H. The size of the hole H is smaller than the size of the chip 23 a mounted on the interposer 21.

図３に示すように、例えば上段側パッケージＰ２の右側部分Ｒ２から出力される信号を下段側パッケージＰ１の左側部分Ｌ１から出力する場合、右側部分Ｒ２から出力される信号を一旦下段側パッケージＰ１の右側部分Ｒ１へ出力し、下段側パッケージＰ１の配線を用いて下段側パッケージＰ１の左側部分Ｌ１から出力するようにしても良い。ホールＨの形成により配線面積が減少する上段側パッケージＰ２に代わり、下段側パッケージＰ１の配線を利用して信号を伝送するものである。   As shown in FIG. 3, for example, when a signal output from the right portion R2 of the upper package P2 is output from the left portion L1 of the lower package P1, the signal output from the right portion R2 is temporarily stored in the lower package P1. The output may be output to the right portion R1 and output from the left portion L1 of the lower package P1 using the wiring of the lower package P1. Instead of the upper package P2 whose wiring area is reduced by forming the hole H, signals are transmitted using the wiring of the lower package P1.

このように本実施形態による半導体装置により積層型パッケージの高さを低減し、上段パッケージと下段パッケージを接続する端子の端子間ショート不良を低減できる。   As described above, the height of the stacked package can be reduced by the semiconductor device according to the present embodiment, and the short-circuit failure between the terminals connecting the upper package and the lower package can be reduced.

上述した実施の形態は一例であって制限的なものではないと考えられるべきである。   The above-described embodiment is an example and should not be considered restrictive.

例えば上記実施形態では下段側パッケージＰ１に１つのチップ、上段側パッケージＰ２に２つのチップを搭載していたが、それぞれ搭載されるチップ数は１つでも良いし、２つ以上でも良い。   For example, in the above embodiment, one chip is mounted on the lower package P1 and two chips are mounted on the upper package P2. However, the number of chips mounted may be one, or two or more.

また、上記実施形態では上段側パッケージＰ２のインターポーザー２１にホールＨを形成していたが、図４に示すように、ホールではなく凹部４１を形成するようにしても良い。ホールＨを形成するよりも低減できる半導体装置（積層型パッケージ）の総厚は小さくなるが、インターポーザーが残る分装置の強度を増すことができる。   In the above embodiment, the hole H is formed in the interposer 21 of the upper package P2, but a recess 41 may be formed instead of the hole as shown in FIG. Although the total thickness of the semiconductor device (stacked package) that can be reduced is smaller than that of forming the hole H, the strength of the device can be increased as much as the interposer remains.

また、図５に示すように、下段側パッケージＰ１、上段側パッケージＰ２にそれぞれ複数（ここでは４つ）のフラッシュメモリ５１を所定間隔ずつずらして搭載し、上段側パッケージＰ２の基板５２に凹部５３を形成し、下段側パッケージＰ１のモールド樹脂５４を凹部５３に配置するような構成に適用しても良い。所定間隔ずつずらすのはワイヤ５５のボンディング領域を確保するためである。１つの基板に８つのフラッシュメモリを搭載するよりも、１つの基板に４つのフラッシュメモリを搭載する方が歩留まりが高いため、製造コストを低減できる。   Further, as shown in FIG. 5, a plurality of (four in this case) flash memories 51 are mounted on the lower package P1 and the upper package P2 while being shifted by a predetermined interval, respectively, and a recess 53 is formed on the substrate 52 of the upper package P2. May be applied to a configuration in which the mold resin 54 of the lower package P1 is disposed in the recess 53. The reason for shifting by a predetermined interval is to secure a bonding region of the wire 55. Since the yield is higher when four flash memories are mounted on one substrate than when eight flash memories are mounted on one substrate, the manufacturing cost can be reduced.

また、上記実施形態による半導体装置は下段側パッケージＰ１と上段側パッケージＰ２の２つのパッケージを備えていたが、図６に示すように３つのパッケージＰ６１〜６３を備える構成にしても良いし、また４つ以上でも良い。   In addition, the semiconductor device according to the above embodiment includes the two packages of the lower package P1 and the upper package P2. However, as illustrated in FIG. 6, the semiconductor device may include three packages P61 to 63. Four or more may be sufficient.

また、上記実施形態ではチップはインターポーザーとワイヤボンディング接続されていたが、フリップチップ接続にしてもよい。その場合、モールド樹脂を形成しなくても良い。   In the above embodiment, the chip is connected to the interposer by wire bonding, but may be flip chip connected. In that case, the molding resin may not be formed.

本発明の技術的範囲は特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

本発明の実施形態による半導体装置の概略構成図である。1 is a schematic configuration diagram of a semiconductor device according to an embodiment of the present invention. 同実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the same embodiment. 信号出力経路の一例を示す図である。It is a figure which shows an example of a signal output path | route. 変形例による半導体装置の概略構成図である。It is a schematic block diagram of the semiconductor device by a modification. 変形例による半導体装置の概略構成図である。It is a schematic block diagram of the semiconductor device by a modification. 変形例による半導体装置の概略構成図である。It is a schematic block diagram of the semiconductor device by a modification.

符号の説明Explanation of symbols

１、４ 導電性ボール
２、３ 導電性ボール用ランド
１１、２１ インターポーザー
１２、２２ ダイボンディング材
１３、２３ チップ
１４、２４ パッド
１５、２５ 導電性ワイヤ
１６、２６ モールド樹脂
Ｐ１ 下段側パッケージ
Ｐ２ 上段側パッケージ 1, 4 Conductive ball 2, 3 Conductive ball land 11, 21 Interposer 12, 22 Die bonding material 13, 23 Chip 14, 24 Pad 15, 25 Conductive wire 16, 26 Mold resin P1 Lower package P2 Upper Side package

Claims (5)

第１の基板及び前記第１の基板上面に搭載された第１のチップを有し、前記第１の基板の前記チップ下方領域にホールが形成されている第１のパッケージと、
第２の基板及び前記第２の基板上面に搭載された第２のチップを有する第２のパッケージと、
前記第１の基板下面と前記第２の基板上面との間に設けられ、前記第１のパッケージと前記第２のパッケージとを電気的に接続する導電性ボールと、
を備え、
前記第２のパッケージの上部が前記ホール内に配置されることを特徴とする半導体装置。 A first package having a first substrate and a first chip mounted on the upper surface of the first substrate, wherein a hole is formed in the chip lower region of the first substrate;
A second package having a second substrate and a second chip mounted on the upper surface of the second substrate;
A conductive ball provided between the lower surface of the first substrate and the upper surface of the second substrate and electrically connecting the first package and the second package;
With
A semiconductor device, wherein an upper portion of the second package is disposed in the hole. 第１の基板及び前記第１の基板上面に搭載された第１のチップを有し、前記第１の基板の下面の所定領域に凹部が形成されている第１のパッケージと、
第２の基板及び前記第２の基板上面に搭載された第２のチップを有する第２のパッケージと、
前記第１の基板下面と前記第２の基板上面との間に設けられ、前記第１のパッケージと前記第２のパッケージとを電気的に接続する導電性ボールと、
を備え、
前記第２のパッケージの上部が前記凹部内に配置されることを特徴とする半導体装置。 A first package having a first substrate and a first chip mounted on the upper surface of the first substrate, wherein a recess is formed in a predetermined region of the lower surface of the first substrate;
A second package having a second substrate and a second chip mounted on the upper surface of the second substrate;
A conductive ball provided between the lower surface of the first substrate and the upper surface of the second substrate and electrically connecting the first package and the second package;
With
The semiconductor device, wherein an upper portion of the second package is disposed in the recess. 前記第２のパッケージは、前記第２のチップと前記第２の基板を電気的に接続するワイヤと、前記第２のチップ及び前記ワイヤを封止するモールド樹脂と、をさらに備えることを特徴とする請求項１又は２に記載の半導体装置。   The second package further includes a wire that electrically connects the second chip and the second substrate, and a mold resin that seals the second chip and the wire. The semiconductor device according to claim 1 or 2. 積層された複数の第１のチップと、上面に前記積層された複数の第１のチップが搭載された第１の基板と、前記第１の基板と前記複数の第１のチップとを電気的に接続する複数の第１のワイヤと、前記複数の第１のチップ及び前記複数の第１のワイヤを封止する第１のモールド樹脂と、を有し、前記第１の基板の下面の所定領域に凹部が形成されている第１のパッケージと、
積層された複数の第２のチップと、上面に前記積層された複数の第２のチップが搭載された第２の基板と、前記第２の基板と前記複数の第２のチップとを電気的に接続する複数の第２のワイヤと、前記複数の第２のチップ及び前記複数の第２のワイヤを封止する第２のモールド樹脂と、を有する第２のパッケージと、
前記第１の基板下面と前記第２の基板上面との間に設けられ、前記第１のパッケージと前記第２のパッケージとを電気的に接続する導電性ボールと、
を備え、
前記第２のモールド樹脂の上部が前記凹部内に配置されることを特徴とする半導体装置。 Electrically connecting a plurality of stacked first chips, a first substrate on which the plurality of stacked first chips are mounted, and the first substrate and the plurality of first chips. A plurality of first wires connected to the first chip, and a first mold resin for sealing the plurality of first chips and the plurality of first wires, and a predetermined lower surface of the first substrate. A first package having a recess in the region;
Electrically connecting a plurality of stacked second chips, a second substrate on which the plurality of stacked second chips are mounted, and the second substrate and the plurality of second chips. A second package comprising: a plurality of second wires connected to the plurality of second chips; and a second mold resin for sealing the plurality of second chips and the plurality of second wires;
A conductive ball provided between the lower surface of the first substrate and the upper surface of the second substrate and electrically connecting the first package and the second package;
With
An upper portion of the second mold resin is disposed in the recess. 前記複数の第１のチップ、前記複数の第２のチップはそれぞれ所定間隔ずつずらして積層されることを特徴とする請求項４に記載の半導体装置。   The semiconductor device according to claim 4, wherein the plurality of first chips and the plurality of second chips are stacked with a predetermined interval.
JP2007112922A 2007-04-23 2007-04-23 Semiconductor device Pending JP2008270597A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010263192A (en) * 2009-05-08 2010-11-18 Samsung Electronics Co Ltd Package on package to prevent circuit pattern lift defect and method of fabricating the same
KR20110055299A (en) * 2009-11-19 2011-05-25 삼성전자주식회사 Semiconductor package having multi pitch ball land
CN112563213A (en) * 2019-09-10 2021-03-26 铠侠股份有限公司 Semiconductor device and method for manufacturing the same
CN112614830A (en) * 2020-11-30 2021-04-06 华为技术有限公司 Encapsulation module and electronic equipment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010263192A (en) * 2009-05-08 2010-11-18 Samsung Electronics Co Ltd Package on package to prevent circuit pattern lift defect and method of fabricating the same
KR20110055299A (en) * 2009-11-19 2011-05-25 삼성전자주식회사 Semiconductor package having multi pitch ball land
KR101665556B1 (en) * 2009-11-19 2016-10-13 삼성전자 주식회사 Semiconductor package having multi pitch ball land
CN112563213A (en) * 2019-09-10 2021-03-26 铠侠股份有限公司 Semiconductor device and method for manufacturing the same
CN112563213B (en) * 2019-09-10 2024-04-05 铠侠股份有限公司 Semiconductor device and method for manufacturing the same
CN112614830A (en) * 2020-11-30 2021-04-06 华为技术有限公司 Encapsulation module and electronic equipment

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