JP2008270265A - Substrate for semiconductor device and its production process - Google Patents
Substrate for semiconductor device and its production process Download PDFInfo
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- JP2008270265A JP2008270265A JP2007107181A JP2007107181A JP2008270265A JP 2008270265 A JP2008270265 A JP 2008270265A JP 2007107181 A JP2007107181 A JP 2007107181A JP 2007107181 A JP2007107181 A JP 2007107181A JP 2008270265 A JP2008270265 A JP 2008270265A
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- plating layer
- gold plating
- gold
- semiconductor device
- metal plate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000007747 plating Methods 0.000 claims abstract description 152
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 81
- 229910052737 gold Inorganic materials 0.000 claims abstract description 81
- 239000010931 gold Substances 0.000 claims abstract description 81
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 22
- 229910052763 palladium Inorganic materials 0.000 claims description 12
- 230000007935 neutral effect Effects 0.000 claims description 9
- 230000002378 acidificating effect Effects 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 4
- 229910001252 Pd alloy Inorganic materials 0.000 claims description 4
- BBKFSSMUWOMYPI-UHFFFAOYSA-N gold palladium Chemical compound [Pd].[Au] BBKFSSMUWOMYPI-UHFFFAOYSA-N 0.000 claims description 4
- PQTCMBYFWMFIGM-UHFFFAOYSA-N gold silver Chemical compound [Ag].[Au] PQTCMBYFWMFIGM-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 abstract description 22
- 229920005989 resin Polymers 0.000 abstract description 22
- 238000007789 sealing Methods 0.000 abstract description 21
- 239000010935 stainless steel Substances 0.000 description 16
- 229910001220 stainless steel Inorganic materials 0.000 description 16
- 206010040844 Skin exfoliation Diseases 0.000 description 7
- 239000002585 base Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- KERTUBUCQCSNJU-UHFFFAOYSA-L nickel(2+);disulfamate Chemical compound [Ni+2].NS([O-])(=O)=O.NS([O-])(=O)=O KERTUBUCQCSNJU-UHFFFAOYSA-L 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
本発明は、めっきによって半導体装置の端子部となる部分を形成する半導体装置用基板及びその製造方法に関するものである。 The present invention relates to a semiconductor device substrate on which a portion to be a terminal portion of a semiconductor device is formed by plating and a method for manufacturing the same.
半導体装置の小型・薄型化は年々進み、図４（Ｃ）に示すような封止樹脂２３の裏面に外部との接続部（端子部）２５を有する半導体装置が増えてきた。このような半導体装置のパッド部や端子部は、銅系合金や鉄・ニッケル合金をエッチング加工やプレス加工により所定のパターンに形成したリードフレームを用いることが一般的だった。しかし、このリードフレームは、０．１２５〜０．２０ｍｍの板厚のものが主に使用され、薄型化を妨げる要因の一つとなっていた。 As the size and thickness of semiconductor devices have been reduced year by year, the number of semiconductor devices having an external connection portion (terminal portion) 25 on the back surface of the sealing resin 23 as shown in FIG. In general, a pad frame or a terminal portion of such a semiconductor device uses a lead frame in which a copper alloy or iron / nickel alloy is formed in a predetermined pattern by etching or pressing. However, the lead frame having a thickness of 0.125 to 0.20 mm is mainly used, which has been one of the factors hindering thinning.
近年、このリードフレームの代わりに、金属板に０．１ｍｍ以下の厚さでめっき層を形成した半導体装置用基板を用いて、パッド部や端子部をめっき層で形成した薄型の半導体装置が現れてきた。
このめっき層によりパッド部や端子部を形成する半導体装置は、図２に示すように、金属板１０上にめっき層によりパッド部３や端子部２となる部分を形成した半導体装置用基板１を用い、これに図４（Ａ）に示すようにパッド部３に半導体素子２１を搭載し、ワイヤボンディング２２、樹脂封止等の組み立て工程を経て、その後金属板のみを溶解する方法やあるいは引き剥がす方法により、金属板を除去することで封止樹脂の裏面にめっき層の外部接続部を有する半導体装置を得ている。
In recent years, instead of this lead frame, a thin semiconductor device in which a pad portion and a terminal portion are formed of a plating layer using a substrate for a semiconductor device in which a plating layer is formed on a metal plate with a thickness of 0.1 mm or less has appeared. I came.
As shown in FIG. 2, the semiconductor device in which the pad portion and the terminal portion are formed by the plating layer includes a semiconductor device substrate 1 in which a portion that becomes the pad portion 3 and the terminal portion 2 is formed on the metal plate 10 by the plating layer. 4A, a semiconductor element 21 is mounted on the pad portion 3 as shown in FIG. 4A, an assembly process such as wire bonding 22 and resin sealing is performed, and then only a metal plate is melted or peeled off. By removing the metal plate by the method, the semiconductor device having the external connection portion of the plating layer on the back surface of the sealing resin is obtained.
ところで、銅系合金を金属板とする場合は、機械的に容易に引き剥がすことができないため、樹脂封止後に金属板である銅系合金のエッチング処理が必要となり、製造工程が複雑となり、経済性も悪かった。 By the way, when a copper alloy is used as a metal plate, it cannot be easily mechanically peeled off. Therefore, after the resin sealing, the copper alloy, which is a metal plate, needs to be etched, making the manufacturing process complicated and economical. The nature was also bad.
また、ステンレス鋼を金属板として、樹脂封止後にステンレス鋼を引き剥がす場合は、通常、端子部となる部分を形成するめっき層のステンレス鋼に対する完全な密着性が得づらく、その結果封止樹脂がステンレス鋼と金めっきの間に回りこむ問題があった。 In addition, when stainless steel is used as a metal plate and the stainless steel is peeled off after resin sealing, it is usually difficult to obtain complete adhesion to the stainless steel of the plating layer that forms the terminal portion. However, there was a problem of getting around between stainless steel and gold plating.
その上、この金属板を引き剥がす方法に用いる半導体装置用基板は、組み立て工程においてめっき層が金属板から剥離せず、また封止樹脂が金属板とめっき層の間に回り込むことなく密着している必要があり、且つ、金属板を引き剥がした後は、引き剥がした金属板にパッド部や端子部となるめっき層が残らず、封止樹脂と密着して封止樹脂から浮いた状態や剥離する事態が生じないようにすることが必要である。つまり、金属板とめっき層が、半導体装置の組み立て工程中は剥がれることなく密着している必要がある。一方、金属板のみを除去する工程においては、めっき層が封止樹脂と密着するとともに金属板とめっき層の間が剥がれ易いという相反する機能が要求される。 In addition, the substrate for a semiconductor device used in the method of peeling off the metal plate is in close contact without the plating layer peeling off from the metal plate in the assembly process, and without the sealing resin flowing between the metal plate and the plating layer. After the metal plate is peeled off, there is no plating layer remaining as a pad part or a terminal part on the peeled metal plate, and it is in contact with the sealing resin and floated from the sealing resin. It is necessary to prevent the situation of peeling. That is, the metal plate and the plating layer need to be in close contact with each other without being peeled off during the assembly process of the semiconductor device. On the other hand, in the process of removing only the metal plate, a conflicting function is required in which the plating layer is in close contact with the sealing resin and the metal plate and the plating layer are easily peeled off.
そして、特許文献１には、金属板上に形成するめっき層は、基材上に金めっき層、ニッケルめっき層、金めっき層で構成された半導体装置用基板が開示されている。この半導体装置用基板は、樹脂封止後に基材部をエッチング除去するようにした半導体装置であり、基材部を引き剥がす方法ではないため、金属板にパッド部や端子部となるめっき層が残る問題はない。 Patent Document 1 discloses a substrate for a semiconductor device in which a plating layer formed on a metal plate is composed of a gold plating layer, a nickel plating layer, and a gold plating layer on a base material. This substrate for a semiconductor device is a semiconductor device in which the base material portion is removed by etching after resin sealing, and is not a method of peeling off the base material portion. Therefore, a plating layer that becomes a pad portion or a terminal portion is formed on the metal plate. There is no problem left.
また、特許文献２には金属板の表面にブラスト処理などによって凹凸を設け、且つ剥離性をもたせる酸化膜を形成する剥離処理を行った後に、めっき層を形成する技術が開示されている。しかし、金属板の一面に凹凸を付ける表面処理工程と、剥離性をもたせる剥離処理工程が新たに必要となる。また、めっき層を形成する片面側に凹凸を設けることで、反りが発生する問題がある。
本発明は、このような問題点を解決するためになされたものであり、その目的とするところは、半導体装置の製造に用いる基板について、金属板を引き剥がす際に、引き剥がした金属板にパッド部や端子部となるめっき層が残らず、一方パッド部や端子部が封止樹脂から浮いた状態や剥離する事態が生じないように封止樹脂と良好に密着しためっき層を有する半導体装置用基板及び半導体装置を提供することである。 The present invention has been made in order to solve such problems, and the object of the present invention is to remove the metal plate from the substrate used for manufacturing the semiconductor device. A semiconductor device having a plating layer that is in close contact with the sealing resin so that no plating layer remains as a pad portion or a terminal portion, while the pad portion or the terminal portion does not float or peel off from the sealing resin. And providing a semiconductor substrate and a semiconductor device.
上記の目的を達成するために、本発明の半導体装置用基板は、金属板上に、粒状の第１の金めっき層と、その上に成膜しためっき層が形成されているものである。 In order to achieve the above object, the substrate for a semiconductor device of the present invention is such that a granular first gold plating layer and a plating layer formed thereon are formed on a metal plate.
また、本発明の別の態様は、金属板上に、粒状の第１の金めっき層と、その上に成膜した第２の金めっき層が形成されているとともに、第２の金めっき層の上にさらにめっき層が形成されているものである。 In another aspect of the present invention, a granular first gold plating layer and a second gold plating layer formed thereon are formed on a metal plate, and the second gold plating layer is formed. Further, a plating layer is formed thereon.
そして、本発明の別の態様は、前記発明に加えて第２の金めっき層の上に形成されるめっき層として、第２の金めっき層の上に少なくとも、ニッケル又は銅のめっき層と、金又は銀又はパラジウムあるいはこれらの合金のめっき層が積層されているものである。 And, in another aspect of the present invention, as a plating layer formed on the second gold plating layer in addition to the above invention, at least a nickel or copper plating layer on the second gold plating layer, A plated layer of gold, silver, palladium, or an alloy thereof is laminated.
一方、本発明の半導体装置用基板の製造方法は、金属板上に、酸性浴による第１の金めっき層を形成した後、前記第１の金めっき層の上に成膜させためっき層を形成するようにしたものである。 On the other hand, in the method for manufacturing a substrate for a semiconductor device according to the present invention, after forming a first gold plating layer by an acidic bath on a metal plate, a plating layer formed on the first gold plating layer is formed. It is to be formed.
そして、本発明の半導体装置用基板の製造方法の別の態様は、金属板上に、酸性浴による第１の金めっき層を形成した後、前記第１の金めっき層の上に中性浴による第２の金めっき層を形成し、さらに前記第２の金めっき層の上にめっき層を形成するようにしたものである。 And another aspect of the manufacturing method of the board | substrate for semiconductor devices of this invention is a neutral bath on the said 1st gold plating layer, after forming the 1st gold plating layer by an acidic bath on a metal plate. A second gold plating layer is formed, and a plating layer is further formed on the second gold plating layer.
また、本発明の半導体装置用基板の製造方法の別の態様は、金属板上に、酸性浴による第１の金めっき層を形成した後、前記第１の金めっき層の上に中性浴による第２の金めっき層を形成し、次にその上に直接あるいはパラジウムめっき層を形成後ニッケル又は銅のめっき層を形成し、さらにその上に中性浴による金めっき層あるいは銀又はパラジウム又は金銀合金又は金パラジウム合金の何れか一つ以上のめっき層を形成するようにしたものである。 In another aspect of the method for manufacturing a substrate for a semiconductor device of the present invention, after forming a first gold plating layer by an acid bath on a metal plate, a neutral bath is formed on the first gold plating layer. And then forming a nickel or copper plating layer directly or after forming a palladium plating layer directly thereon, and further forming a gold plating layer or silver or palladium by a neutral bath thereon One or more plating layers of gold-silver alloy or gold-palladium alloy are formed.
さらに、本発明の別の態様は、前記発明に加えてｐＨ０．１〜１．０の強酸性浴を用いて金属板上に第１の金めっき層を形成するようにしたものである。 Furthermore, in another aspect of the present invention, a first gold plating layer is formed on a metal plate using a strongly acidic bath having a pH of 0.1 to 1.0 in addition to the above invention.
また、本発明の別の態様は、前記発明に加えて電流密度を０．３〜１．０Ａ／ｄｍ２ で金めっき層を形成するようにしたものである。 Another aspect of the present invention is such that a gold plating layer is formed at a current density of 0.3 to 1.0 A / dm 2 in addition to the above-described invention.
半導体装置の組み立て工程において、金属板上に形成されるめっき層が金属板から剥離せず、また封止樹脂が金属板とめっき層の間に回り込むこともなく密着していて、なおかつ、引き剥がした金属板にパッド部や端子部となるめっき層が残らず、そしてパッド部や端子部が封止樹脂から浮いた状態や剥離する事態が生ぜず、封止樹脂と良好に密着しためっき層を有する半導体装置用基板を得ることが可能となる。 In the assembly process of the semiconductor device, the plating layer formed on the metal plate does not peel off from the metal plate, and the sealing resin does not wrap around between the metal plate and the plating layer, and is peeled off. There is no plating layer left on the metal plate that becomes the pad or terminal, and there is no situation where the pad or terminal is lifted from the sealing resin or peeled off. It is possible to obtain a semiconductor device substrate.
金属板上にレジストにより所定のパターンを形成し、めっき前処理を行った後、パターン間から露出する金属板の部分に、ｐＨ０．１〜１．０の強酸性浴を用いて電流密度０．３〜１．０Ａ／ｄｍ２ のめっき条件下で、粒状に形成される第１の金めっき層を１０〜２０ｎｍの厚さで形成する。 After a predetermined pattern is formed on the metal plate with a resist and pre-plating treatment is performed, the current density is set to 0. 0 using a strongly acidic bath having a pH of 0.1 to 1.0 on the portion of the metal plate exposed from between the patterns. Under a plating condition of 3 to 1.0 A / dm 2, a first gold plating layer formed in a granular shape is formed with a thickness of 10 to 20 nm.
次に、第２の金めっき層として中性の一般的な金めっき層を約０．１μｍ形成し、その上に一般的なスルファミン酸ニッケルめっきによりニッケルめっき層を約１０μｍ形成し、その上に中性の一般的な金めっき層を約３μｍ形成して、レジストを剥離し、水洗と乾燥などの後処理を行って、本発明の半導体装置用基板を得ることができる。 Next, a neutral general gold plating layer of about 0.1 μm is formed as the second gold plating layer, and a nickel plating layer of about 10 μm is formed thereon by a general nickel sulfamate plating. A neutral general gold plating layer is formed to a thickness of about 3 μm, the resist is peeled off, and post-treatment such as water washing and drying is performed to obtain the substrate for a semiconductor device of the present invention.
次に、図１〜図３に基づいて本発明の半導体装置用基板及び半導体装置用基板の製造方法について説明する。
まず図３（Ａ）に示すように、金属板１０として板厚０．２ｍｍのステンレス鋼（ＳＵＳ４３０）を用いて、脱脂処理と酸洗浄処理を行った後、厚さ０．０２５ｍｍの感光性ドライフィルムレジスト１４をラミネートロールで上記ステンレス鋼（金属板１０）の両面に貼り付けた。
Next, the semiconductor device substrate and the method for manufacturing the semiconductor device substrate of the present invention will be described with reference to FIGS.
First, as shown in FIG. 3 (A), a stainless steel plate (SUS430) having a thickness of 0.2 mm is used as the metal plate 10, and then a degreasing treatment and an acid cleaning treatment are performed, followed by a photosensitive dry treatment having a thickness of 0.025mm. The film resist 14 was affixed on both surfaces of the stainless steel (metal plate 10) with a laminate roll.
次に、後でめっき層を形成する部分を黒く、それ以外を透明にしたガラスマスクをドライフィルムレジストの上から被せて、さらにその上から紫外光を照射することで露光を行い、ドライフィルムレジスト１４に所定のパターン１５を作製した。なお、このときのパターン１５は、めっき層を形成するめっきエリアとして、３ｍｍ角のパッド部３とその周囲に０．３ｍｍ角の端子部２を２８個配置したものを準備し、このようなものを幅１００ｍｍの金属板のうち中央部で幅５０ｍｍの部分に１０個均等に並ぶように作製した。 Next, the portion where the plating layer is to be formed later is black, and a glass mask with the other portions made transparent is covered from above the dry film resist, and further, exposure is performed by irradiating ultraviolet light from above. A predetermined pattern 15 was prepared on 14. The pattern 15 at this time is prepared by preparing a 3 mm square pad portion 3 and 28 0.3 mm square terminal portions 2 around it as a plating area for forming a plating layer. 10 were prepared so as to be evenly arranged in a central portion of a metal plate having a width of 100 mm in a portion having a width of 50 mm.
次に、炭酸ナトリウム溶液を用いて、紫外光の照射が遮られて感光しなかった未硬化のドライフィルムレジストを溶かす現像処理を行って、図３（Ｂ）に示すようにめっき層を形成するための材料を完成させた。
次に、めっき前処理として、まずアルカリ浸漬し、その後に３ｍｏｌ／Ｌの塩酸に浸漬させた。
Next, using a sodium carbonate solution, a development process is performed to dissolve the uncured dry film resist that has not been exposed to the exposure to ultraviolet light, and a plating layer is formed as shown in FIG. Completed the material for.
Next, as a pretreatment for plating, the substrate was first immersed in an alkali, and then immersed in 3 mol / L hydrochloric acid.
以上の前処理を行った後、図３（Ｃ）に示すようにｐＨ０．８の金めっき浴を用いて、浴温２５℃、電流密度０．５Ａ／ｄｍ２ に設定して３０秒のめっき処理を行い、ステンレス鋼（金属板１０）上に第１の金めっき層１１Ａとなる下地金めっきを形成した。次に、第２の金めっき層１１Ｂとして中性の一般的な金めっきを約０．１μｍ施し金めっき層１１を形成した。そしてその上にニッケルめっき層１２として一般的なスルファミン酸ニッケルめっきを１０μｍ施し、さらにその上に中性の一般的な金めっき１３を３μｍ施した。そして最後に図３（Ｄ）に示すように水酸化ナトリウム溶液でドライフィルムレジストを剥離し、水洗と乾燥を行った後に、１００ｍｍ×２００ｍｍの大きさに切断して半導体装置用基板１を得た。 After performing the above pretreatment, as shown in FIG. 3 (C), using a gold plating bath having a pH of 0.8, the bath temperature is set to 25 ° C. and the current density is set to 0.5 A / dm 2. The base gold plating used as 11A of 1st gold plating layers was formed on stainless steel (metal plate 10). Next, about 0.1 μm of neutral general gold plating was applied as the second gold plating layer 11B to form the gold plating layer 11. Then, 10 μm of general nickel sulfamate plating as a nickel plating layer 12 was applied thereon, and further 3 μm of neutral general gold plating 13 was applied thereon. Finally, as shown in FIG. 3D, the dry film resist was peeled off with a sodium hydroxide solution, washed with water and dried, and then cut into a size of 100 mm × 200 mm to obtain a semiconductor device substrate 1. .
次に、上記半導体装置用基板１を用いて半導体装置を製造する方法を図４に基づいて説明する。
まず、図４（Ａ）に示すように上記実施例１の方法により製造した半導体装置用基板１を用いて、パッド部３に半導体素子２１をダイボンド用ペーストを用いて搭載し、半導体素子２１の電極と端子部２をワイヤボンディング２２した後、樹脂封止を行う。そして図４（Ｂ）に示すように、封止樹脂２３硬化後にステンレス鋼（金属板１０）と樹脂封止された部分とを引き剥がした。そして、これを図４（Ｃ）に示すように個片化して半導体装置を得た。
Next, a method for manufacturing a semiconductor device using the semiconductor device substrate 1 will be described with reference to FIG.
First, as shown in FIG. 4A, the semiconductor device substrate 1 manufactured by the method of Example 1 is used to mount the semiconductor element 21 on the pad portion 3 using a die-bonding paste. After wire bonding 22 between the electrode and the terminal portion 2, resin sealing is performed. And as shown in FIG.4 (B), after sealing resin 23 hardening, stainless steel (metal plate 10) and the resin-sealed part were peeled off. And this was separated into pieces as shown in FIG. 4C to obtain a semiconductor device.
引き剥がしたステンレス鋼（金属板１０）側を観察した結果、めっきが残っている部分はなかった。また樹脂封止された部分の、ステンレス鋼と接していた金めっき側を確認すると、封止樹脂２３の回り込みもなく、樹脂からめっき層が浮いたり剥離したりすることなく保持されていることが確認できた。さらにこの第１の金めっき層１１Ａである金めっき面のはんだ濡れ性を溶融はんだで確認したところ、金めっき面全域にきれいに半田付けができた。 As a result of observing the peeled stainless steel (metal plate 10) side, there was no portion where plating remained. Further, when the gold-plated side in contact with the stainless steel in the resin-sealed portion is confirmed, the sealing resin 23 does not wrap around, and the plating layer is held without being lifted or peeled off from the resin. It could be confirmed. Furthermore, when the solder wettability of the gold-plated surface as the first gold-plated layer 11A was confirmed by molten solder, it was possible to cleanly solder the entire gold-plated surface.
次に、金めっき層を粒状に形成するための適切なめっき電流密度を確認するために、ｐＨ０．８の金めっき浴を用いて、浴温２５℃、の条件下で、めっきの電流密度を［低］として０．２Ａ／ｄｍ２ 、［中］として０．７Ａ／ｄｍ２ 、［高］として１．２Ａ／ｄｍ２ 、の３種類に分けて、ステンレス鋼上に、本発明の第１の金めっき層のみを施して、断面ＴＥＭにて金めっきの状態を観察した。 Next, in order to confirm an appropriate plating current density for forming a gold plating layer in a granular form, the plating current density is adjusted under the condition of a bath temperature of 25 ° C. using a gold plating bath having a pH of 0.8. The first gold plating of the present invention on stainless steel, divided into three types of [low] 0.2 A / dm2, [medium] 0.7 A / dm2, [high] 1.2 A / dm2. Only the layer was applied, and the state of gold plating was observed with a cross-sectional TEM.
観察結果は図６に示す通りである。電流密度［低］及び［中］では金めっきは粒状に、［高］では膜状となっており、断面から推察される本発明の金めっき層の厚みは１０〜２０ｎｍ程度となっていた。
すなわち、樹脂封止後にステンレス鋼を引き剥がす場合、１０〜２０ｎｍ程度の厚みで、電流密度１．０Ａ／ｄｍ２ 以下の条件で成膜させず粒状に形成された本発明の第１の金めっき層が最適であることがわかった。
The observation results are as shown in FIG. In the current densities [low] and [medium], the gold plating is granular, and in the [high] film form, the thickness of the gold plating layer of the present invention inferred from the cross section is about 10 to 20 nm.
That is, when the stainless steel is peeled off after resin sealing, the first gold plating layer of the present invention formed in a granular shape without forming a film with a thickness of about 10 to 20 nm and a current density of 1.0 A / dm 2 or less. Was found to be optimal.
次に、ステンレス鋼と第１の金めっき層の密着力が電流密度によりどのように変化するかを確認するために、ｐＨ０．８の金めっき浴を用いて、浴温２５℃の条件下で、ステンレス鋼上に幅５ｍｍ、長さ１００ｍｍの帯状にめっき層を形成した。その際、電流密度を図５に示すような５種類として、帯状パターンの端を少し引き剥がしてから、ステンレス鋼の素材に固定して、帯状パターンを上方向に引っ張り上げるかたちで、ピール強度を測定した。測定結果を図５に示すように、電流密度により比例的にピール強度が変化することが確認できた。 Next, in order to confirm how the adhesion between the stainless steel and the first gold plating layer changes depending on the current density, a gold plating bath having a pH of 0.8 is used under the condition of a bath temperature of 25 ° C. A plating layer was formed in a strip shape having a width of 5 mm and a length of 100 mm on stainless steel. At that time, the current density is made into five types as shown in FIG. 5, the end of the strip pattern is peeled off a little, and then fixed to the stainless steel material, and the strip pattern is pulled up to increase the peel strength. It was measured. As shown in FIG. 5, it was confirmed that the peel strength changed proportionally with the current density.
すなわち、本発明の第１の金めっき層の形成において、電流密度を０．３Ａ／ｄｍ２ 〜１．０Ａ／ｄｍ２ に設定することにより、ステンレス鋼とめっき層の密着力の強弱を付けることができることが確認できた。 That is, in the formation of the first gold plating layer of the present invention, the strength of adhesion between the stainless steel and the plating layer can be increased or decreased by setting the current density to 0.3 A / dm 2 to 1.0 A / dm 2. Was confirmed.
また、図７は本発明の半導体装置用基板の他例の概略断面図を示したものである。本実施例では、金属板１０上に第１の金めっき層１１Ａとなる粒状の下地金めっきが形成してあり、その上に第２の金めっき層１１Ｂとして成膜した金めっき層が形成してある。そして、第２の金めっき層の上はめっき層無し若しくはパラジウムめっき層１６となっている。そして、その上はニッケル又は銅のめっき層１７となっている。さらに、その上はめっき層無し若しくはパラジウム又は金のめっき層１８となっている。そして、その上は金又は銀又はパラジウム又は金銀合金又は金パラジウム合金のめっき層１９となっている。 FIG. 7 is a schematic cross-sectional view of another example of the substrate for a semiconductor device of the present invention. In the present embodiment, a granular base gold plating serving as the first gold plating layer 11A is formed on the metal plate 10, and a gold plating layer formed as the second gold plating layer 11B is formed thereon. It is. Then, the second gold plating layer has no plating layer or a palladium plating layer 16. On top of that, a nickel or copper plating layer 17 is formed. Further, there is no plating layer, or a plating layer 18 of palladium or gold. On top of that, a plating layer 19 of gold, silver, palladium, gold-silver alloy or gold-palladium alloy is formed.
１ 半導体装置用基板
２ 端子部
３ パッド部
１０ 金属板
１１ 金めっき層（第１の金めっき層＋第２の金めっき層）
１１Ａ 第１の金めっき層
１１Ｂ 第２の金めっき層
１２ ニッケルめっき層
１３ 金めっき層
１４ レジスト
１５ レジストにより形成されたパターン
１６ めっき層無し若しくはパラジウムめっき層
１７ ニッケル又は銅のめっき層
１８ めっき層無し若しくはパラジウム又は金のめっき層
１９ 金又は銀又はパラジウム又は金銀合金又は金パラジウム合金のめっき層
２０ 半導体装置
２１ 半導体素子
２２ ワイヤボンディング
２３ 封止樹脂
２４ ボンディング部
２５ 外部接続部
DESCRIPTION OF SYMBOLS 1 Substrate for semiconductor devices 2 Terminal part 3 Pad part 10 Metal plate 11 Gold plating layer (1st gold plating layer + 2nd gold plating layer)
11A 1st gold plating layer 11B 2nd gold plating layer 12 nickel plating layer 13 gold plating layer 14 resist 15 pattern 16 formed by resist 16 no plating layer or palladium plating layer 17 nickel or copper plating layer 18 no plating layer Alternatively, palladium or gold plating layer 19 gold, silver, palladium, gold-silver alloy, or gold-palladium alloy plating layer 20 Semiconductor device 21 Semiconductor element 22 Wire bonding 23 Sealing resin 24 Bonding portion 25 External connection portion
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5493639A (en) * | 1977-12-30 | 1979-07-24 | Seiko Epson Corp | Plating method |
| JPS59208756A (en) * | 1983-05-12 | 1984-11-27 | Sony Corp | Manufacture of semiconductor device package |
| JPH1050885A (en) * | 1996-05-27 | 1998-02-20 | Dainippon Printing Co Ltd | Circuit member for semiconductor device semiconductor device using it, and manufacture of them |
| JP2003268586A (en) * | 2002-03-15 | 2003-09-25 | Ne Chemcat Corp | Gold plating electrolytic solution and gold plating method |
| JP2004214265A (en) * | 2002-12-27 | 2004-07-29 | Kyushu Hitachi Maxell Ltd | Semiconductor device and its manufacturing method |
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2007
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5493639A (en) * | 1977-12-30 | 1979-07-24 | Seiko Epson Corp | Plating method |
| JPS59208756A (en) * | 1983-05-12 | 1984-11-27 | Sony Corp | Manufacture of semiconductor device package |
| JPH1050885A (en) * | 1996-05-27 | 1998-02-20 | Dainippon Printing Co Ltd | Circuit member for semiconductor device semiconductor device using it, and manufacture of them |
| JP2003268586A (en) * | 2002-03-15 | 2003-09-25 | Ne Chemcat Corp | Gold plating electrolytic solution and gold plating method |
| JP2004214265A (en) * | 2002-12-27 | 2004-07-29 | Kyushu Hitachi Maxell Ltd | Semiconductor device and its manufacturing method |
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| Title |
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