JP2008268071A - Lsi tester and test system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LSI tester and a test system capable of improving an operating rate by forecasting a test ending time on a wafer basis with high accuracy. <P>SOLUTION: The LSI tester and the test system for testing respective LSIs formed on a wafer is characterized by that the LSI tester is structured so as to forecast and calculate an ending time of measurement of all of the LSIs in real time every time the respective LSI tests are ended, and that the plurality of the LSI testers are connected by a network. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an LSI tester and a test system, and more particularly, to an improvement in operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.

  FIG. 4 is a conceptual diagram showing an example of a conventional LSI tester. The operation terminal 10 controls the test head 30 via the control unit 20 to execute a test for individual LSIs formed on the wafer 40 placed on the test head 30 as an object to be measured. The progress and results of these tests are displayed on the display screen.

  In the control unit 20, the test execution unit 21 performs control so as to execute a predetermined test on each LSI formed on the wafer 40.

  The average test time storage unit 22 stores an average test time required for performing a test on each LSI measured in advance.

  The test time measuring unit 23 measures a test time required for performing a test on each LSI.

  The test pass / fail judgment unit 24 judges pass / fail of the test result every time the test for each LSI is completed, and displays the result on the display screen of the operation terminal 10.

  The measurement LSI counting unit 25 sequentially counts the number of non-defective products, the number of defective products, and the number of remaining measurement LSIs to be tested each time the test for each LSI is completed.

  The end time prediction calculation unit 26 is based on the average test time stored in the average test time storage unit 22 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25. The time when the measurement of all the LSIs formed on 40 is completed is predicted and displayed on the display screen of the operation terminal 10.

  The test time accumulating unit 27 sequentially accumulates test times required for performing tests on individual LSIs to obtain a sum of test times for all LSIs formed on the wafer 40 currently being tested. Used to calculate average test time in wafer test.

  According to such a configuration, the average test time storage unit 22 stores in advance the average time required to measure one LSI formed on the wafer 40, and the measurement LSI counting unit 25 must test. Since the remaining number of measurement LSIs is sequentially counted, the end time prediction calculation unit 26 can predict and calculate the time when the measurement of all the LSIs formed on the wafer 40 ends.

  The measurement operator can perform a reverse calculation from the estimated end time and prepare for replacement of the wafer placed on the test head 30 as the object to be measured, and after the test for the previous wafer is completed, the next new wafer is prepared. It is possible to increase the test execution availability by minimizing the test pause time of the tester until it is replaced and the test is restarted.

  Patent Document 1 discloses a test apparatus for a semiconductor device configured to increase an operation rate of a tester by predicting an end time in performing parallel measurement by combining one tester and two probing apparatuses. Test methods are described.

JP-A-8-327694

  If the measurement times of all the LSIs formed on the wafer 40 have shifted based on the average time stored in the average test time storage unit 22, the next wafer replacement is performed based on the estimated end time. As a result, the test execution time can be increased by minimizing the test pause time of the tester.

  However, in general, since LSIs formed on the wafer include those that have failed, measurement of all LSIs does not end normally and does not coincide with the predicted end time. There are many cases.

  Then, if the measurement of a certain wafer 40 is completed early and the mounting of the next wafer is delayed, the test pause time of the tester becomes long, and the tester operating rate decreases. On the other hand, if the measurement of the wafer 40 does not end even after the scheduled time, an operator standby time occurs.

  In the case of the technique described in Patent Document 1, the estimated end time is an average for each wafer, but as described above, the LSI formed on the wafer includes a failing LSI. There are many. When the LSI fails, the test time is shortened, so that the average end predicted time for each wafer including the failing LSI becomes low accuracy.

  The present invention pays attention to such conventional problems, and an object of the present invention is to provide an LSI tester and a test system capable of increasing the operation rate by predicting the test end time in wafer units with high accuracy. It is to provide.

  The invention according to claim 1 which achieves such a problem is an LSI tester for testing individual LSIs formed on a wafer, and the time at which the measurement of all LSIs is completed is determined by each LSI test. It is configured to perform prediction calculation in real time every time it ends.

  According to a second aspect of the present invention, there is provided an LSI tester for testing individual LSIs formed on a wafer, the means for measuring the test time of each LSI, and the pass / fail judgment for the test result of each LSI. Means for counting the number of non-defective products tested, means for determining a cumulative value of normal test times for LSIs determined to be non-defective, and a normal test based on the cumulative values of normal test times and the count values of good LSIs Means to obtain the average value of time, and predict the time when measurement of all LSIs currently formed on the wafer under test is completed based on the average value of normal test time and the remaining number of measurement LSIs that must be tested Means for calculating.

  The invention of claim 3 is a test system in which a plurality of LSI testers for testing individual LSIs formed on a wafer are connected to an integrated terminal TC via a network, and the LSI testers are all The time at which the measurement of the LSI is completed is predicted and calculated in real time every time the test of the individual LSI is completed.

  The invention of claim 4 is a test system in which a plurality of LSI testers for testing individual LSIs formed on a wafer are connected to an integrated terminal TC via a network. Means for measuring the test time of the LSI, means for determining pass / fail for the test result of each LSI, means for counting the number of non-defective products tested, and accumulation of normal test time of the LSI determined to be good A means for obtaining a value, a means for obtaining an average value of normal test times based on a cumulative value of normal test times and a count value of non-defective LSIs, and an average value of normal test times and the remaining number of measurement LSIs to be tested. And a means for predicting and calculating the time at which measurement of all the LSIs currently formed on the wafer under test is completed.

  As a result, the test end time can be predicted on a wafer basis in real time with high accuracy, and the operating rate of the LSI tester and the test system can be increased.

  Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a specific example of the present invention, and the same reference numerals are given to portions common to FIG. In the configuration of FIG. 1, a normal test time accumulation unit 28 and a normal test time average unit 29 are provided instead of the average test time storage unit 22 and the test time accumulation unit 27 in the configuration of FIG. 4.

  The normal test time accumulating unit 28 uses the test time required to perform the test of the LSI whose test result is determined to be non-defective among the tests for the individual LSIs. Each time the determination is made, it is accumulated and stored sequentially, and is reflected in the prediction calculation of the time at which the measurement of all the LSIs formed on the wafer 40 currently being tested performed by the end time prediction calculation unit 26 is completed.

  The normal test time averaging unit 29 determines that the test result is a non-defective product based on the accumulated value of the normal test time sequentially stored in the normal test time accumulating unit 28 and the count value of the non-defective LSI counted by the measurement LSI counting unit 25. The average value of the normal test time of the non-defective LSI required to perform the test of the completed LSI is sequentially calculated at each timing when the test pass / fail judgment unit 24 performs the pass / fail judgment of each LSI.

  The end time prediction calculation unit 26 is based on the average value of normal test times of good LSIs sequentially calculated by the normal test time averaging unit 29 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25. The time when measurement of all the LSIs formed on the wafer 40 currently being tested ends is sequentially predicted and calculated for each timing at which the pass / fail judgment of each LSI is performed by the test pass / fail judgment unit 24, and the operation terminal 10 display screens.

  FIG. 2 is a flowchart for explaining the flow of the operation of FIG. First, the test execution unit 21 performs a predetermined test on each LSI formed on the wafer 40, and the test time measurement unit 23 measures the test time required for performing the test on each LSI. (SP1).

  The test pass / fail judgment unit 24 judges pass / fail of the test result every time the test for each LSI is completed (SP2).

  When the test result determination unit 24 determines that the test result is a non-defective product, the normal test time accumulating unit 28 sequentially accumulates and stores the test time required for testing the LSI whose test result is determined to be a non-defective product. The time averaging unit 29 sequentially calculates the average value of the non-defective LSI test times based on the accumulated value of the normal test time and the count value of the non-defective LSI counted by the measurement LSI counter 25 (SP3).

  The end time prediction calculation unit 26 is based on the average test time of the non-defective LSI calculated by the normal test time average unit 29 and the remaining number system value of the measurement LSI that must be tested by the measurement LSI counting unit 25. The time at which the measurement of all the LSIs formed on the wafer 40 is completed is sequentially predicted and calculated for each pass / fail judgment for the test result (SP4).

  The processing from step SP1 to step SP4 is repeatedly executed until the measurement of all the LSIs formed on the wafer 40 currently being tested is completed (SP5).

  If the test pass / fail determination unit 24 determines that the test result is a defective product, the process skips steps SP2 and SP3 and jumps to step SP4.

  By configuring in this way, the time at which the measurement of all the LSIs formed on the wafer 40 currently being tested is completed can be updated and predicted in real time with high accuracy based on the average value of the test times of non-defective LSIs. Since the wafer exchange schedule can be dynamically set based on this time, the operating rate of the tester can be improved and the waiting time of the operator can be reduced.

  In the above-described embodiment, an example in which individual LSIs formed on a wafer are tested has been described. However, the efficiency of test program change work associated with switching of LSI product lots performed on a wafer basis is also described. Similar effects can be obtained.

  Further, as shown in FIG. 3, by constructing a test system in which a plurality of testers TR1 to TRn based on the present invention are connected in parallel with being connected to the integrated terminal TC via a network, the operator can connect the integrated terminal TC. It is possible to know the predicted end times of all the testers TR1 to TRn on the display screen.

  Thereby, since the work preparation of the whole test system can be planned in advance, it is possible to increase the test execution operation rate of the whole test system without staying at the partial optimization of the tester alone.

  As described above, according to the present invention, it is possible to realize an LSI tester and a test system that can increase the operation rate by predicting the end time in high accuracy and in real time, which is also effective for reducing the test cost of the LSI. .

It is a block diagram which shows the specific example of this invention. It is a flowchart explaining the flow of operation | movement of FIG. It is a block diagram of the test system using the tester of this invention. It is a block diagram of a conventional LSI tester.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Operation terminal 20 Control part 21 Test execution part 23 Test time measurement part 24 Test pass / fail judgment part 25 Measurement LSI count part 26 End time prediction calculation part 28 Normal test time accumulation part 29 Normal test time average part 30 Test head 40 Wafer TR1- TRn tester TC integrated terminal

Claims (4)

An LSI tester for testing individual LSIs formed on a wafer,
An LSI tester configured to predict and calculate in real time the time at which measurement of all LSIs is completed each time the test of each LSI is completed. An LSI tester for testing individual LSIs formed on a wafer,
Means for measuring the test time of each LSI;
Means for determining pass / fail for the test result of each LSI;
Means for counting the number of tested non-defective products;
Means for obtaining a cumulative value of normal test times of LSIs determined to be non-defective products;
Means for obtaining an average value of normal test times based on a cumulative value of normal test times and a count value of non-defective LSIs;
Means for predicting and calculating the time at which measurement of all the LSIs currently formed on the wafer under test is completed based on the average value of normal test times and the remaining number of measurement LSIs to be tested;
An LSI tester characterized by comprising: A test system in which a plurality of LSI testers for testing individual LSIs formed on a wafer are connected to an integrated terminal TC via a network,
The LSI tester is
A test system configured to predict and calculate a time at which measurement of all LSIs is completed in real time every time an individual LSI test is completed. A test system in which a plurality of LSI testers for testing individual LSIs formed on a wafer are connected to an integrated terminal TC via a network,
The LSI tester is
Means for measuring the test time of each LSI;
Means for determining pass / fail for the test result of each LSI;
Means for counting the number of tested non-defective products;
Means for obtaining a cumulative value of normal test times of LSIs determined to be non-defective products;
Means for obtaining an average value of normal test times based on a cumulative value of normal test times and a count value of non-defective LSIs;
Means for predicting and calculating the time at which measurement of all the LSIs currently formed on the wafer under test is completed based on the average value of normal test times and the remaining number of measurement LSIs to be tested;
A test system characterized by comprising:

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