KR20090071765A - A test method of a wafer for reducing a site difference - Google Patents

Abstract

A test method of a wafer for reducing a site difference is provided to reduce the additional task about the wafer in which the site difference is generated by making the test equipment to remove the foreign material through the self automatic washing. The tested result is respectively stored in each site(502). The test error generation ratio is drawn by counting the test error respectively generated from the stored result(508). The difference of the test error generation ratio between the sites is compared with the standards which is set up in advance(516). If it is determined that the difference is greater than the standards, the retest is again performed about the site in which the error is generated(519). At least one of the test result or the retest result is displayed(522).

Description

A test method of a wafer for reducing a site difference}

The present invention relates to a method for testing whether or not a wafer on which a semiconductor contact element is formed is normally manufactured by using a test equipment having a probe.

In recent years, multi-site testing has been conducted in order to produce a variety of products that meet the needs of customers at a timely and competitive price. Multi-site testing refers to testing two or more chips simultaneously on a single probe, on a wafer on which multiple semiconductor chips (also called dies) are formed. This multi-site test can reduce the time and cost of the test and enable the efficient operation of the test equipment. However, compared to the single site test, which tests the individual chips separately, it uses several resources, so there are problems that depend on the result of various variables. For example, the abnormal behavior of hardware assigned to each site, or the difference in the flatness of a probe card needle, or the balance of a prober chuck on which the foreign matter attached to the probe or the wafer being tested is mounted. Even though the same test condition is given, the DC characteristic, the functional characteristic and the distribution of the BIN blocks are displayed according to the sites to be tested. This difference is called the site difference. 1 shows a wafer in which site differences are shown during a dual site test in which two chips are simultaneously tested. As shown in FIG. 1, the BIN 22 error 104 does not appear at the second site 102 of the two sites, and the BIN 22 error 104 appears only at the first site 100. FIG. 2 shows that a site difference occurs due to a left and right difference in the flatness of the probe 200 mounted on the upper block 202 or the chuck 206 on which the wafer 204 is mounted. Another reason is that the foreign material 303 is attached to the tip of the probe 302 in contact with the pad 300 is not shown the correct test results.

If it is discovered that such a site difference has occurred, the test must be run again or the faulty chip can be selected and tested again. This test flow is shown in the flowchart of FIG. 4. The wafers loaded in the test apparatus are all subjected to a primary test on the chips (402). Next, a second test is performed after selecting chips indicating a specific BIN error (404). In this case, the selection of a specific chip may be artificially set by the user on the test apparatus. After this procedure, it is determined whether a site difference has occurred (406). If no site difference is found, the test is terminated (410). If a site difference is found, the test must be restarted entirely by the user who confirmed the site difference, or the test should be performed on the chip in which the error occurred (408). That is, according to the conventional test method, after the test is completed or completed, the user can directly check and determine the problem, and there is a problem that it is not easy for the user to find and cope with the slight site difference.

The present invention has been made to solve the above problems, and relates to a test method for determining whether a site difference caused by a problem of a test device has occurred as a result of a test, and automatically performs an action in response thereto.

According to an aspect of the present invention, there is provided a multi-site test method for a wafer on which a plurality of chips are formed, the method comprising: (a) real-time storing the test results for each site for each site; (b) deriving a test error occurrence rate of each site by counting test errors generated for each site from the stored result; (d) comparing the difference in test error occurrence rates between the sites with a preset criterion; (e) re-testing the site where the error occurred if it is determined that the difference is greater than the reference; And (f) displaying at least one of the test result and the retest result.

In this case, step (d) is performed immediately before or after the test is performed on a chip set as a flag in the wafer in advance, and if the difference is greater than the reference as a result of the comparison in step (d), the test is performed. The method may further include cleaning the probe provided in the apparatus.

In addition, in the step (e), the retest may be performed only on a portion of the region within the predetermined wafer before the test.

On the other hand, after step (f) is completed, steps (a) to (f) are repeated again through the step of adjusting the flatness or contact distance between the probe of the test apparatus that performs the test and the chuck supporting the wafer. Can be performed

In the multi-site test by the conventional method, when the site difference occurs, the site difference detection and the solution cannot be suggested based on the digitized data. As a result, site differences caused additional retests, adding to the time and cost of product development. However, when the present invention is applied, the user can actively and actively respond to the warning when a site difference occurs. The site difference data also helps the test rig auto-clean itself to remove debris and set up chips to retest, thus reducing the additional manpower on the wafer with the site difference. In addition, by selecting regions that have severe site differences and retesting only those regions, unnecessary retests are prevented, and sites with severe site differences are prevented by discriminating overdrives.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

Conventional test apparatuses did not have the function to quantify and display the type and quantity of BIN errors for each site. Therefore, if the test apparatus can provide such functions, the information and site differences of each site may be changed without special data processing steps. Alerts can be easily identified by the user. In addition, this data can be stored in memory for processing while the wafer is being tested, creating an immediate user response. 5 is a flowchart showing step by step a test method according to an embodiment of the present invention. In this case, the test device stores the measurement results in real time in the memory for each site where the test is performed for the BIN error mode selected by the user, and tests the wafer to analyze the test results up to that point when a specific chip is reached in the wafer. . Here, a chip is defined as a flag indicating that the time point for analyzing the test result has been reached. These flags can be preset in various values according to the user's intention, and the test results can be analyzed until immediately before the test of the chip set with the flag or immediately after the chip set with the flag. In this embodiment, as shown in FIG. 6, a chip other than the last chip tested in the wafer, for example, a chip present in the middle portion is designated as the first flag 600, and a chip present in the last portion of the wafer is designated as the second flag. (602). In the case of testing the wafer set as described above, when the test device undergoing the test reaches the first flag 600, the test result is analyzed based on the test result up to the first flag. The same is true for the second flag 602.

In some cases, the wafer may be divided into regions before testing. This partitioning allows you to analyze or retest the results for specific areas only. In the present embodiment, as shown in FIG. 7, the wafer is divided into 30% up, down, left, right, and 40% of the center.

Hereinafter, the algorithm of the present invention will be described with reference to FIG. 5. In this embodiment, it is assumed that the BIN error mode is set to BIN 3 and that the site difference is allowed to 50% as a dual site test for testing two chips simultaneously. Once the test begins (500), the test apparatus continues the test until it meets the first flag set on the wafer (502). Next, when the first flag is encountered (504), the test apparatus performs a predetermined process by using the test results therebetween (506). For example, the total number of detected BIN 3 errors for each tested site and each divided region is counted and stored in an arbitrary variable, respectively. Next, a BIN 3 error occurrence rate of the first site and the second site is calculated and it is determined whether the difference between the BIN 3 error occurrence rate between the first site and the second site is 50% or more (508). If the result is more than 50%, this is an abnormal value and is most likely caused by a test device problem rather than a chip problem. Therefore, the test apparatus automatically cleans the probe as a measure for this problem (510). For example, if the number of BIN 3 errors occurred on the first site is 10 and the number on the second site is 30, then the BIN 3 occurrence rate on the first site is 25%, which is the result of dividing 10 by the total number of errors. Similarly, the second cyton is 75%. As a result, there is a 50% difference in error rate between sites. When the probe cleaning is completed, the test is continued again (512). If the difference in error generation is less than 50%, the test apparatus determines that there is no problem inside the test apparatus and immediately resumes the test without cleaning the probe (512). Next, when the test proceeds to meet the second flag (518), the predetermined process as described above is repeated. If the second flag is set to the chip to be tested as in this embodiment, the following process may be performed. If it is determined that the difference in occurrence rate of the total BIN 3 errors between the first site and the second site is less than 50% at the time when the test is completed, it is determined that there is no problem with the test apparatus and the test is terminated (530). However, if it is determined that 50% or more, it is determined that the test device is a problem and automatically retests the chip in which the BIN3 error occurs (519). In some cases, the test apparatus may calculate a difference in incidence rates of BIN 3 errors according to sites for each preset region, and automatically perform retesting only in an area in which the difference in incidence rates is greater than a predetermined criterion (520). In this case, since the part judged to be normally performed is excluded from the retest, the time required for the test may be shortened.

When the retest is completed as above, the test and retest results are displayed in operation 522. In some cases, if the display results indicate that there is a problem between the probe in the test device and the wafer under test, the user may adjust the flatness or contact distance between the probe and the chuck supporting the wafer, and then perform the test again. 524.

 It has been described so far limited to one embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

1 shows test results by a dual site test.

Figure 2 shows the occurrence of site differences due to the left and right flatness difference between the probe and the wafer support chuck provided in the test apparatus.

Figure 3 shows the generation between sites by the foreign matter attached to the tip of the probe.

4 is a step-by-step illustration of a conventional wafer test method.

5 illustrates step by step a multi-site test method according to the present invention.

Fig. 6 shows the setting of flags in the wafer.

7 shows a wafer divided into specific regions.

Claims (5)

In the multi-site test method of a wafer having a plurality of chips (a) storing the test results for each site in real time for each site; (b) deriving a test error occurrence rate of each site by counting test errors generated for each site from the stored result; (d) comparing the difference in test error occurrence rates between the sites with a preset criterion; (e) re-testing the site where the error occurred if it is determined that the difference is greater than the reference; And (f) displaying at least one of the test result and the retest result; Multi-site test method comprising the. The method of claim 1, The step (d) is performed immediately before or after the test is performed on a predetermined chip in the wafer, And if it is determined that the difference is greater than the reference as a result of the comparison in the step (d), cleaning the probe provided in the apparatus that performed the test. The method of claim 2, Wherein said chip is not the chip on which the test was last performed. The method of claim 1, In the step (e), wherein the re-test is performed only on a portion of the predetermined area in the wafer before the test. The method of claim 1, (g) adjusting the flatness or contact distance between the probe of the test apparatus performing the test and the chuck supporting the wafer; And (h) repeating steps (a) to (f) again Multi-site test method comprising the more.

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